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2024-02-02vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.hFelix Held
Provide 3 separate functions for each openSIL time point instead of one, so that we don't need the xSIM-api header file to be included in opensil.h to decouple the coreboot code more form the openSIL code. This will allow to create an openSIL stub implementation to already get most of the coreboot-side SoC code in place before the openSIL source code is done and released. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-02cpu/x86/smm/pci_resource_store: Allow devices with no resourcesPatrick Rudolph
When a device with no resource is passed it will keep overwriting the current slot. Remove the conditional and allow a PCI device to not have any resources. This is particular useful for the next commits that makes use of the PCI resource store to pass UBOX devices to SMM that allow to lock-down SMM from within an SMI handler. Those devices do not have any resources and cannot be hardcoded in SMM as their PCI segment group and bus number varies depending on socket count, CPU discovery and configuration. Change-Id: I1a1b5944c97da5be6b9794c653b5159683f492e5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80246 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-02-02drivers/intel/gma: Add missing parentheses to brightness ACPIJonathon Hall
Commit d25277666829 ("tree: Replace And(a,b) with ASL 2.0 syntax") replaced two instances of `And(var, mask) == 0` with `var & mask == 0`. This expression needs parentheses - `(var & mask) == 0`. Without parentheses, it is always false, since the masks are nonzero (`var & (mask == 0)`; `var & 0`; `0`). This caused brightness changes on Intel GMA to take longer than normal since the status was never checked. The brightness would change immediately, but another brightness change could not occur until the first change timed out. This was most noticeable in KDE, which waits for the brightness change to complete before accepting another brightness up/down keypress. Tapping brightness up/down repeatedly would take much longer to reach max/min brightness due to many presses being ignored. It is noticeable in GNOME as well but less obvious. Tapping brightness up/down repeatedly would handle all keypresses, but the display's actual brightness would lag behind and skip some intermediate steps. I tested both Librem 13v2 and Librem 14, as far as I know this would apply to all systems configuring brightness with Intel GMA. Test: Verify brightness keys respond quickly again on Librem 13v2 / 14. Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80260 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-01mb/google/brox: Enable HDA Codec ALC256Poornima Tom
On Brox, HDA Codec used is ALC256. Add verb table for the same. Also, add the related device tree changes for HDA related registers. Realtek High Definition Audio Configuration- Version : 5.0.3.1 BUG=b:317398558 BRANCH=None TEST=verified HDA on Brox. HDA Sound cards detected. Headphone working verified. Device listed under sysfs as below: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ID 256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79723 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-01soc/amd: factor out memmap from root_complexFelix Held
Now that the SoC-specific memory map is reported on the domain device instead of the northbridge device, factor out the read_soc_memmap_resources function from root_complex.c to new memmap.c file. For now each SoC still has its own memmap.c file, but the plan is to eventually have a common implementation that works for all AMD family 17h+ SoCs. For that I'll still need to look closer into the differences between the FSP and the openSIL integration though. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01soc/amd/phoenix/root_complex: make read_fsp_resources call conditionalFelix Held
Only call read_fsp_resources if PLATFORM_USES_FSP2_0 is selected in Kconfig. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic63e0904ad04dbecfac1be4d59abbb8d4f9f11d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resourcesFelix Held
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the legacy PCI config space access is needed on all AMD SoCs, implement a common add_pci_cfg_resources function that reports both and gets called from amd_pci_domain_read_resources and don't report those in the SoC- specific code any more. The only functional change is that on Genoa now the IO ports used for the legacy PCI config space access get reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01vc/amd/opensil/genoa_poc/memmap: pass resource index as pointerFelix Held
To make add_opensil_memmap match the other function that are directly or indirectly called by amd_pci_domain_read_resources, pass the resource index as a pointer instead of passing it by value and then returning the new resource index. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01soc/amd: rework DRAM and fixed resource reportingFelix Held
Introduce read_soc_memmap_resources which gets called by amd_pci_domain_read_resources for the first domain of the SoC to report the DRAM and PCI config space access resources to the allocator. For Genoa this allows to use amd_pci_domain_read_resources as read_resources in the genoa_pci_domain_ops instead of needing to wrap that call to be able to call add_opensil_memmap for the first domain. For the other family 17h+ SoCs the moves the reporting of the DRAM resources and the PCI config space access resources from the northbridge device to the domain device. TEST=Resources still get reported on Mandolin, but now under the domain instead of the northbridge PCI device Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib19fd94e06fa3a1d95ade7fafe22db013045a942 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80268 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-01soc/amd/*/root_complex: use unsigned long for resource indexFelix Held
Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f58e32a535326116460545287cc59aaf94166a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-01soc/amd/common/data_fabric/domain: use unsigned long for resource indexFelix Held
Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60ac0e30627001698565b7256421780f9a94bf65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80266 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-01vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource indexFelix Held
Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct and the functions to report the resources. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80265 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-01soc/amd/common,genoa_poc/domain: rework check for 1st domainFelix Held
Previously the code checked if the first downstream bus of the domain was bus 0 in segment group 0 to only run certain code for the first domain. Instead check if the domain number is 0 which should make the code a bit easier to understand. TEST=add_opensil_memmap still gets called exactly once on Onyx Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad Reviewed-on: https://review.coreboot.org/c/coreboot/+/79996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-31soc/intel/xeon_sp: Find VTD devices by PCI DEV IDPatrick Rudolph
Instead of manually crafting S:B:D:F numbers for every VTD device loop over the entire devicetree by PCI DEV IDs. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80092 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-31soc/intel/xeon_sp: Attach UBOX stacksPatrick Rudolph
Attach UBOX stacks on newer generation Xeon-SP. In order to use PCI drivers for UBOX devices, locating UBOX devices by vendor and device IDs and replacing device access by specifying S:B:D:F numbers, add a PCI domain for the UBOX stacks and let the PCI enumerator index all devices. Since there are no PCI BARs on the UBOX bus the PCI locator doesn't have to assign resources on those buses. Once all PCI devices on the UBOX stack can be located without knowing their UBOX bus number and PCI segment the Xeon-SP code can fully enable the multi PCI segment group support. Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID. Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80091 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-31soc/amd/noncar/memlayout.ld: Warn about incorrect reset vectorArthur Heymans
The x86 core always starts with an IP at 0xfff0. This needs to match in the code. Change-Id: Ibced50e4348a2b46511328f9b3f3afa836feb9a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31cpu/x86/smm/pci_resource_store: Store DEV/VEN IDPatrick Rudolph
Allow SMM to verify the list of provided PCI devices by comparing the device and vendor ID for each PCI device. Change-Id: I7086fa450fcb117ef8767c199c30462c1ab1e1b6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-31soc/amd/phoenix/chip: make FSP-S call conditionalFelix Held
Only call amd_fsp_silicon_init if PLATFORM_USES_FSP2_0 is selected in Kconfig. I'm not 100% sure about the data_fabric_set_mmio_np call yet, but since it doesn't depend on PLATFORM_USES_FSP2_0 to compile, I'll look into that one later. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-31device/device.h: Fix spelling mistakeArthur Heymans
Fix spelling mistake added in 3e99ba0 "device: Add a helper function to add a downstream bus". Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I66ae5000f6f5c0e5bfe42bdfbbbcedec6df0c520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80234 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31mb/google/rex/variants/deku: correct GPIO E08 and E22 configurationEran Mitrani
GPP_E08 and GPP_E22 were set incorrectly previously. This CL corrects these settings according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8e427350e1ee564f9d6566bdfe1f42c92c87a711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-31mb/google/brya: Correct Ti50 EC-is-trusted logiczengqinghong
With Cr50, the GPIO EC_IN_RW is used to determine whether EC is trusted. However, With the switch to Ti50, it is determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore in the Ti50 case get_ec_is_trusted() can just return 0. The current code of get_ec_is_trusted() only checks the GPIO, which causes the EC to be always considered "trusted". Therefore, correct the return value to 0 for TPM_GOOGLE_TI50. BUG=b:321172119 TEST=emerge-nissa coreboot chromeos-bootimage TEST=firmware_DevMode passed in FAFT test Change-Id: I308f8b36411030911c4421d80827fc49ff325a1b Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp- partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-30mb/google/rex/variants/deku: Add H58G66BK7BX067 to RAM ID tableTony Huang
Add RAM ID for H58G66BK7BX067 0 (0000) BUG=b:322528721 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: I31538988d1329d9e2f45d862eb0ae05c0d6a179e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-30mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblockTyler Wang
Check MTL EDS2, SOC_TCHSCR_RST(GPP_C01) default setting is NF1. Set SOC_TCHSCR_RST to output low in early_gpio_table. BUG=none TEST=Build and test on karis, touchscreen function works Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-30soc/intel: Unify the definition of TCO registersMarek Maslanka
Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-30mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSDTyler Wang
Follow reference design rex0, toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=none TEST=Build karis and try warm reboot from OS console. Check the DUT with WD SSD boots to OS again. Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-30mb/google/geralt: Increase VM18 LDO voltage to 1.9V for CiriCong Yang
The current panel voltage measured at mainboard side is 1.79V and the voltage at panel side is 1.74V. Since the panel requires 1.8V or more, increase the circuit voltage to 1.9V to meet the panel requirement. After adjustment mainboard side voltage is 1.89V and panel side is 1.84V. BUG=b:322080023 TEST=Check ciri vm18 ldo voltage BRANCH=None Change-Id: I6d6193d45409f53c0b656890c44ddaef253c5e01 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80198 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-30security/intel: Use write{64,32,16,8}p and read{64,32,16,8}pElyes Haouas
Change-Id: I4bdfcd0cc0e2d9b5f884ea7275659c12488715e0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80194 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-29malloc/memalign: Return NULL if the request is too largePatrick Georgi
It's what this function family is defined to do, we currently don't usually run into the case (see: not too many die() instances going around), it's more useful to try to recover, and the JPEG parser can run into it if the work buffer size exceeds the remaining heap, whereas its sole user (the bootsplash code) knows what to do when seeing a NULL. Use xmalloc() if you want an allocation that either works or dies. tl;dr: That code path isn't usually taken. Right now it crashes. With this patch it _might_ survive. There is a use-case for doing it like that now. Change-Id: I262fbad7daae0ca3aab583fda00665a2592deaa8 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-29device/device.h: Drop multiple linksArthur Heymans
Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-29soc/intel/xeon_sp/spr: Create CXL ACPI resources only forShuo Liu
CXL IIO stacks When an IIO stack is connected with CXL cards, its bus range will be divided by a PCI host bridge object and a CXL host bridge object, otherwise, all its range will be owned by the PCI host bridge object. Accordingly, CXL ACPI resources should be only created when the IIO stack is connected with a CXL card. TEST=intel/archercity CRB Change-Id: I6c1b1343991bc73d90a433d959f6618bbf59532f Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80087 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-29soc/amd/stoney: Match ACPI with resource allocationNico Huber
Currently resource allocation starts top down from the default value 0xfe000000. This does not match what ACPI reports, so adapt CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that. Change-Id: I32d08ffd5bbd856b17f7ca2775c5923957d92c85 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-29device: Add a helper function to add a downstream busArthur Heymans
Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-28soc/amd/*/acpi: drop CRAT TODOFelix Held
The CRAT (Component Resource Attribute Table) isn't used on the APUs from Renoir on and has also been marked as deprecated in version 6.5 of the ACPI specification. So remove the 'TODO: look into adding CRAT' comment from all SoCs from Renoir/Cezanne on. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80227 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: move acpi_add_fsp_tables implementation to common FSP codeFelix Held
Since the acpi_add_fsp_tables implementation is identical for all SoCs, factor it out and move it to the common AMD FSP code. Also guard the acpi_add_fsp_tables call in soc_acpi_write_tables with if (CONFIG(PLATFORM_USES_FSP2_0)) to properly handle the FSP dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8917a346f586e77b3b3278c73aed8cf61f3c9e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80225 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: factor out acpi_add_fsp_tablesFelix Held
Factor out acpi_add_fsp_tables from the soc_acpi_write_tables function and move the remaining parts of the soc_acpi_write_tables function to the SoC's acpi.c. This aligns the other family 17h/19h SoCs more with Genoa and only leaves the FSP-specific code in agesa_acpi.c which will be made common in a following patch. I decided against also renaming agesa_acpi.c to acpi_fsp.c, since that would have made the diff less readable and the files get deleted in a following patch anyway. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia87ac0e77c5e673e694703b85a4bab85a34b980e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-27soc/amd/picasso: factor out CRAT table generationFelix Held
Factor out the code to add the CRAT ACPI table into a separate file and add the acpi_add_crat_table function that can then be called from soc_acpi_write_tables to better isolate all code specific to the CRAT table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a7853748512811d3d4e124224fcd459e527522c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80223 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: use common ACPI_SCI_IRQ definitionFelix Held
ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd/*/acpi: use common soc_acpi_write_tables prototypeFelix Held
Since the definition is the same for all SoCs, move it to the common amdblock/acpi.h header. Since the Stoneyridge northbridge.c file also includes this prototype, remove the static attribute of the function there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9aa215f2b4ba58f43fed2c751d989f1719e0a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80221 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd/common/include/acpi: add missing device/device.h includeFelix Held
The southbridge_write_acpi_tables function uses a struct device type parameter, but device/device.h that provides the definition wasn't included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5245fa132ec9b84bbc483a31788bcd6fac0736e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-27soc/amd/common/fsp: use expected types for add_agesa_fsp_acpi_tableFelix Held
add_agesa_fsp_acpi_table should use the same type for the 'current' parameter and return value as the calling soc_acpi_write_tables does. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie9f770b1d847ea28e4dbd96298a723d794b91a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-27soc/amd: use expected function signature for soc_acpi_write_tablesFelix Held
A pointer to soc_acpi_write_tables gets assigned to the write_acpi_tables element of the device_operations struct, so make sure that the function has the expected function signature which in this case means using unsigned long as type for both the 'current' parameter and the return value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iee45badb904fa20c6db146edbc00c40ca09361d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80218 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: rename agesa_write_acpi_tables to soc_acpi_write_tablesFelix Held
It's not the AGESA code that generates most of the ACPI tables, so rename the function. This also aligns the other SoCs more with Genoa. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80217 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1Jan Samek
As a result of hardware changes on this board, the PHY previously routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake SoC. This patch changes the device PCI ID in the board's devicetree and accordingly, the GPIO configuration. BUG=none TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE are working, while PSE GbE 1 remains inactive (not listed by 'ip link') . Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2024-01-27mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 sMario Scheithauer
The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. The patch has already been made for mc_ehl3 and serves the purpose of standardization. commit c0221aa980d3 ("mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s") Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2024-01-27mb/google/nissa/var/anraggar: Enable BT audio offloadJianeng Ceng
This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:303157827 TEST=Build and boot to anraggar. Verify the config from serial logs. w/o this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 0 [SPEW ] Pin Muxing ``` w/ this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 1 [SPEW ] Pin Muxing ``` Change-Id: I9e6731c8ceaad6ee58b525d4246fa769bfe1b0c7 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80001 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27mb/google/brya/var/omniknight: Add WIFI SAR tablejamie_chen
Add WIFI SAR table for omniknight. BUG=b:320172979 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I70e79577612b3d5c4dc0f92211f87cbea0532d5d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80152 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-01-27mb/google/rex: Organize models configs alphabeticallySubrata Banik
This patch ensures the baseboard and variant configs (inside Kconfig and Kconfig.name) are organized in alphabetic order. TEST=execute make menuconfig and verify the google/rex variants order are alphabetically correct. Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80206 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCLDaniel Peng
Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:320137193 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80150 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-01-26mb/google/brox: Enable TouchscreenShelley Chen
BUG=b:300690448,b:319393777 BRANCH=None TEST=tested on a device with i2cdetect Also tested with evtest and make sure Wacom is listed Change-Id: I4f528b0d778c8c4a4e83774d5c167ccb2d6afd9a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79895 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/google/brox: Remove CNVi BluetoothShelley Chen
This is causing an assertion error on the devices that don't have CNVi enabled because CNVi is hidden behind a FW_CONFIG flag in the overridetree now. BUG=b:319188820 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure we can boot to kernel on device. Change-Id: Ifcfbc04825d4d4e7f2874a4c52f9c5cf3e657856 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80211 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/intel/common: Add lunarlake device IDsAppukuttan V K
Added Lunar Lake device IDs the device specific functions Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-01-26src, util: Clean up makefile.inc in text, help & commentsMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib69236fb5d68272f92405512dc231fa75ecccaa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26vc/amd: move verstage on PSP files to new psp_verstage folderFelix Held
Move the verstage on PSP files in vendorcode from the fsp subdirectory to a new psp_verstage subdirectory, since those files aren't specific to the case of the FSP being used for the silicon initialization. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80209 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-01-26mb/amd/onyx_poc: Add and use APCB configuration dataVarshit Pandya
This patch adds APCB blobs to the mainboard directory and it replaces CB:76445 Also this brings onyx_poc mainboard inline with how APCB are included in other AMD mainboard: commit 95d05d830162 ("mb/google/zork: Add and use APCB configuration data"), commit I352f58e0d39 ("mb/google/ skyrim: Add and use APCB configuration data") and commit I1c34528fa0f ("mb/amd/onyx_poc: Add and use APCB configuration data"). BUG=none TEST=build/boot onyx_poc Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80204 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/amd: factor out common acpi_add_ivrs_table implementationFelix Held
Instead of open-coding this functionality in all AMD SoCs, factor it out into a common implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80208 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-01-26mb/purism/librem_cnl: Set edk2 boot timeout for Librem MiniMatt DeVillier
As with other devices with only an external display, the Librem mini/ mini-v2 need a few extra seconds (vs an internal panel) for display init in order for the edk2 boot splash to be visible before the default boot target is booted. TEST=build/boot Librem Mini v2 w/edk2 payload, verify splash screen shown / user has time to enter setup menu. Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-26src, util: Update toolchain.inc references to .mkMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ieaf7894f49a90f562b164924cc025e3eab5a3f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-26lib/smbios: Add 32 bit entry point if below 4GMaximilian Brune
If the smbios table is not below 4G there is no need to have a 32 bit entry point. Even worse it could cause the payload to try to use the entry point. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4cb426bb0c45282ed03ff4c65d15004b7f985dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/76911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-26mb/google/brya: alphabetize model configsNick Vaccaro
Alphabetize the ordering of model configs and selects in Kconfig and Kconfig.name BUG=None BRANCH=None TEST='emerge-brya coreboot' and verify it builds. Change-Id: Id9347421337d451ce72fcf3984489b06f372f70c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26mb/google/rex/var/karis: Skip tcc_offset overrideSubrata Banik
This change eliminates the unnecessary override of the tcc_offset chip configuration to 10, as the default rex baseboard now handles this setting correctly. TEST=Successfully built and booted google/karis, confirming tcc_offset remains at 10. Change-Id: Ie40db1431fb0197ee360ad5656878e57f51c855b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-26mb/google/rex/var/screebo: Modify TCC_offset to 20Subrata Banik
Follow thermal team request, override tcc_offset to 20. TEST=Build and verified by thermal team using google/screebo. Change-Id: Idc76f9c0054f21f066b779e6404a1c175eb396a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-26soc/intel/commonlake: Re-add SATA to soc_api_name() listMatt DeVillier
Now that we've added an ACPI device for SATA, add the name back to the soc_acpi_name() list so the PEPD LPI constraint list generates a valid reference to the SATA device. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/intel/common/block/sata: Add ACPI stub for SATA deviceMatt DeVillier
Add an ACPI stub containing the SATA device in proper scope, along with the device status, so that there exists a device to be referenced from the PEPD LPI constraint list. Fixes a Windows BSOD INTERNAL_POWER_ERROR on devices with enabled SATA ports. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I951c62d09609ed73079fe97ea9ce49fdee333272 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26Revert "soc/intel/cannonlake: Add missing min sleep state for thermal device"Matt DeVillier
This reverts commit d64b66ba267a217d0b6716309019c36c8cfdf8c2: "soc/intel/cannonlake: Add missing min sleep state for thermal device." Reverting because commit e00523aae2ea ("soc/intel/cannonlake: Drop entries from soc_acpi_name()") removed the ACPI device name for the PCH thermal device, since there is no ACPI device defined for it. Removing the name without removing the minimum sleep state caused an invalid LPI entry to be created, which caused a Windows BSOD: INTERNAL_POWER_ERROR. TEST=build/boot Win11 on google/puff (wyvern). Change-Id: I2dfe76d5f72cde7742cee338fa24eaafb84c4604 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80057 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-25vc/amd/opensil/genoa_poc/mpio: don't add duplicate MPIO descriptorsFelix Held
When the device right below the MPIO chip driver has downstream devices without another chip in between, those downstream devices will also have their chip_ops entry set to vendorcode_amd_opensil_genoa_poc_mpio_ops. To avoid adding the same MPIO descriptor again for those additional downstream devices, make sure that the chip_info pointer of the device isn't the same as the one of the parent device, since that's only the case for those additional downstream devices. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6ba90fdc83ba089127e6722778bfef29dd480bb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25soc/amd/genoa_poc: rely less on boot state hooksFelix Held
Call setup_opensil, opensil_entry, and fch_init in the right order from the init method of the SoC's chip operations. This brings this SoC both more in line with the other SoCs and avoids using boot state hooks for this which also makes the sequence in which those functions are called easier to understand. Previously the boot states were used so that setup_opensil was run before configure_mpio which was run before opensil_entry(SIL_TP1), but since configure_mpio is called from setup_opensil, this is no longer necessary. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same. The FCH init code now runs before the resource allocation like on the AMD SoCs that rely on FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensilFelix Held
Instead of calling configure_mpio from the init function of the MPIO chip struct for the first device that has this struct as chip_ops, call if from setup_opensil. This will allow to do the calls into openSIL from the SoC's chip_ops init function instead of having to rely on boot state hooks. configure_mpio needs to be called after the xSimAssignMemoryTp1 call which sets up the openSIL data structures, but before the opensil_entry(SIL_TP1) call for which the MPIO data structures need to be filled for it to be able to initialize the hardware accordingly. Since the vendorcode_amd_opensil_genoa_poc_mpio_ops struct now no longer assigns configure_mpio to the init function pointer, we have to check if the device's chip_ops pointer points to vendorcode_amd_opensil_genoa_poc_mpio_ops instead of checking if the chip_ops' init function is configure_mpio to match for the devices below the MPIO chips in the devicetree. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc/opensil_console: fix host debug print functionFelix Held
Since we pass va_list list to the print function, we need to use vprintk instead of printk. Earlier versions of this code used vsnprintf and a local buffer, but when that code was reworked to not need the temporary buffer, it was replaced by printk instead of the correct vprintk. TEST=Now the console output from openSIL looks as expected: Example line from openSIL's console output when it prints the MPIO configuration from a log some commits before this patch: Host PCI Address - -1352681400:-1353251983:7 Same line with this patch applied looks how it's supposed to: Host PCI Address - 0:0:0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ia931cc80dea5b7eabb75cfb19f8baa9a09cd2dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/80203 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/rex/variants/deku: update USB-C port configurationTony Huang
This CL update setting according to schematic v0.4. BUG=b:320201111 BRANCH=firmware-rex-15709.B TEST=Built FW image correctly. Change-Id: Ia4570d26ee9fd175ed9099bd057cee3c30c95704 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80156 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-01-25soc/amd/common: Fix typoVarshit Pandya
Change-Id: Ida6e87908ae6996529057c8df12dbe046ee54b98 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-25mb/hp/snb_ivb_laptops: Add SMBIOS slot informationRiku Viitanen
Looking at photos and service manuals, all the WLAN slots are short (half-height) and WWAN slots long (full-height). Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-25mb/google/brya/var/*: Ensure LCD device has a valid addressMatt DeVillier
Some variants added the generic gfx driver with an LCD device without specifying the address, which is required for the backlight controls to be functional under Windows. Add the address value where missing. Address value used (0x80010400) is same as on other Brya variants which did properly set it, and is taken from the ACPI 6.5 spec section B.4.2, _DOD (display output device enumeration), table B-2: - bit 31 = use the ACPI-defined (vs vendor-defined) bit scheme for bits 15-0 - bit 16 = platform firmware can detect the device - bit 10 = display type is internal/integrated flat panel (aka LCD) TEST=build/boot Win11 on google/brya (osiris), verify ACPI backlight controls functional. Change-Id: Id24e330cfb7c993d12665a704e1ca78e2e38874f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-25mb/google/dedede/var/metaknight:Add fw_config probe for multi codecMorris Hsu
and amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:183305590 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/fizz: Update OEM name listMatt DeVillier
Endeavour and Karma were missing, leading those devices to have empty SMBIOS mainboard names. Fix by adding the missing entries. TEST=build/boot google/fizz (endeavour), verify SMBIOS name correctly shown via dmidecode. Change-Id: I1d4fb2473d27ff5611f9d2b962aae2d6bf6d1da0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80181 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/brox: Switch EC INT and WAKE GPIOsShelley Chen
There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79886 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/brya/var/pujjo: Add i2c device for Parade touch screenleo.chou
Add new i2c address 0x24 of touch IC for Parade touch panel. BUG=b:320731709 Test=emerge-nissa coreboot Change-Id: I51bd89beffd912fc147da11d19f38cb44cbe570a Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-24vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpioFelix Held
As a preparation for the following patch, rename mpio_config to configure_mpio to make it both a bit more descriptive and to match the naming scheme used for the functions that get called by setup_opensil. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4b1aa6e964cbbb4affb89cacd33af8b24871bb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-01-24*/mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth
Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/hp to mb/kontron: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icfdadfa6705a64655b38aca25be0818ec26429f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80110 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/sarien to zork: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib8a2ae26ed4380592d15e1a7b2d682639413af01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/google/oak to rex: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I85cda24aa7dec82d23e8a321dac03ec737f4c503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80108 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/gale to nyan_blaze: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92f8bd7e1c9fc6e4120fb94c2299a266304e19de Reviewed-on: https://review.coreboot.org/c/coreboot/+/80107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/daisy to foster: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I134acc26c0a79d974a6dd0a3b257f961db7e2d86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80106 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24drivers/mipi: Fine tune VFP, CLK and init code for IVO_T109NW41 panelRuihai Zhou
1. Adjust VFP and CLK to meet 60 +- 0.01 Hz 2. Fine tune init code for panel internal circuit Fixes: 520137f("drivers/mipi: Add support for IVO_T109NW41 panel") BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4d7c7bd4d79301fbb6d555117d190c358bceafcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80086 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-24soc/intel: Add Lunar Lake device IDsAppukuttan V K
Added Lunar Lake specific CPU and PCIE device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79899 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-01-24mb/google/rex/var/rex: Set TCC to 100°CSumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79992 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Peter Ou <peter.ou@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/asurada to cyan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5855f49984db59d786decad6142e3525b146a573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80105 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/51nb to mb/gigabyte: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I422cb475723006ca42be93508fb0bf4b1e4e84d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80104 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24device, security: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41f8a9b5d1bdb647a915da1a5e95161b2e34df28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80082 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24lib,console,sbom: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9eabe84d55fd9f434e4128866810c0e4970f2ae7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80081 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24driver/parade to /driver/wwan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cf3d2e2cd1b6ebe4e941ad64f27698379fef696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80080 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24driver/intel to /driver/ocp: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id47a5ef3c53f767d1e03c788e0022d05b21f5c28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24driver/i2c: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I358b878b97adfd9be156a5dd4a9cbaf9e81bca1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24driver/acpi to /driver/gfx: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f299920eb7c6d6f8888cfe5e223ae03093a1d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80077 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24superio: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41191f6971bdd8ecff2c56f4bfa2b57c87530b83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80076 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-01-24southbridge: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic80d27a963da8eddc3d1f0d9a3d59763028d4ed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80075 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>