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2022-03-29mb/google/brya/var/felwinter: Update GPP_E19 from NF to NCJohn Su
Configure GPIO according to b:224107199 comment#15. - GPP_E19 from NF to NC. BUG=b:224107199 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-03-29soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFORex-BC Chen
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8186. Therefore, we select this configuration to enable it. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de Reviewed-on: https://review.coreboot.org/c/coreboot/+/63114 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"Rex-BC Chen
The memory initialization reference code didn't support returning DRAM information in the old platforms, for example MT8192 and MT8195. So we have to add a new configuration USE_CBMEM_DRAM_INFO to make sure the common code will try to get DRAM information on new platforms supporting that. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek/mt8186: Fix pmif setting for low power modeZhiyong Tao
The current pmif register setting for low power mode is incorrect, which is causing suspend failure. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode() to correct the setting. This implementation is based on chapter 3.7 in MT8186 Functional Specification. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-29mb/google/cherry: support max98390 audio ampTrevor Wu
The Cherry follower projects may choose Max98390 for audio output so we have to add a new config CHERRY_USE_MAX98390. Also, the 'dojo' device is the first one to use it. BUG=b:204391159 BRANCH=cherry TEST=emerge-cherry coreboot TEST=Verify beep function through CLI in depthcharge successfully Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-29src/mainboard/starlabs: Remove unused <option.h>Elyes Haouas
Found using: diff <(git grep -l '#include <option.h>' -- src/) <(git grep -l 'sanitize_cmos(\|get_uint_option(\|set_uint_option(\|get_uint_option(\|set_uint_option' -- src/) |grep "<" Change-Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-28soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZEFelix Held
The Sabrina microcode update files are 3200 bytes large and not 5568 like it is the case on Cezanne where this file was originally copied from. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-03-28mb/google/skyrim: Implement mb_set_up_early_espiRaul E Rangel
This will setup the eSPI GPIOs in bootblock right before eSPI init. BUG=b:226635441 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-28mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BLRaul E Rangel
The eSPI CS function only exists on AGPIO30. We will need to rework all boards to make eSPI function. I also fixed the comments on the other eSPI pins. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-28nb/intel/sandybridge/acpi: Support setting PCI bars above 4GArthur Heymans
Although coreboot can allocate resources above 4G, Linux does not consider those allocation valid when there is no region above 4G in _CRS and disables the device. TESTED: x220 with and external GPU via the expresscard slot. Linux does not touch the BARs allocated above 4G. Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-28include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM valuesElyes Haouas
Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09. There is no affected board in coreboot tree. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-28soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER KconfigSubrata Banik
This patch uses the FSP event handler feature and updates with coreboot native debug implementation to unify the debug library between coreboot and FSP. BUG=b:225544587 TEST=Able to build and boot Brya with the same FSP debug log before and with this code changes. Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28soc/intel/alderlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28device/pciexp_device: Set resources for pciexp_hotplug_dummy_opsJohn Su
Without setting the set_resources field for pciexp_hotplug_dummy_ops, we will get an error during pciexp_hotplug_dummy. [ERROR] NONE missing set_resources Because the set_resources field is considered mandatory, explicitly set it as no-op noop_set_resources. BUG=b:220639445 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ifee7479c69cf16025dbd4e3924056ed7f8e253cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63101 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27mb/google/skyrim: Add DXIO descriptorsJon Murphy
Add Skyrim DXIO descriptors using info from AMD and skyrim bouard shematics. BUG=b:225179599 TEST=Boots to OS on Skyrim Board Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27mb/google/hatch/moonbuggy: Update GPIOsPablo Ceballos
Implement the GPIOs that have been changed from genesis. - Connect scaler UART on pins C12/C13 - Connect the HDMI redriver I2C on C18/C19 - Connect the iMX8 signals on D1/D2/D3/D21/D22 - Connect the EC interrupt on D14 (same as on scout) - Connect PCH_TYPEC_UPFB on E15 (same as on genesis) - Configure as not connected the following unused pins: D23, E11, E12, F11 -> F22, H0, H8, H9 BUG=b:200876872 TEST=moonbuggy boots Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Signed-off-by: Pablo Ceballos <pceballos@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-27mb/google/brya/var/banshee: Add mic mute switch settingFrank Wu
Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPOZhuohao Lee
Currently, we control the GPP_D0 in the flash_fp_mcu in order to program the component's firmware. If we set this pin to NC, then we can't control the GPP_D0 output low/high and that make the system fails to program the component's firmware. This patch sets the GPP_D0 to GPO to fix it. BUG=b:204679292 BRANCH=firmware-brya-14505.B TEST=program the component's firmware Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27soc/mediatek: Include 'console/console.h' when appropriateElyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-03-27src/soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27src: Remove unused <bootmode.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<" Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27mb/google/brya/var/brya0: Replace amp max98357 with max98360Amanda Huang
Based on Brya EVT schametic, replace audio amp max98357 with max98360. Add a new audio FW_CONFIG field to support ALC5682I+MAX98360. BUG=b:224423056 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-NUsha P
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP. BRANCH:NONE TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-27vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping tableFelix Held
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO lanes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27include/espi.h: Switch to types.hRaul E Rangel
We use bool in this file, so switch to using types.h. BUG=b:226635441 TEST=Build skyrim with DEBUG_ESPI Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I78b579de4e3832dd49a18413bf5d03870e347c91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63092 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27soc/mediatek/mt8195: Update audio and adsp power controlChun-Jie Chen
To control I2S in MT8195 for dojo project, we need to enable adsp power before audio power. Therefore, we need to update bus protection steps to correct the setting. TEST=build pass BUG=b:204391159 BRANCH=cherry Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung partsRobert Zieba
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This commit assigns them exclusive IDs 9 and 11 to facilitate this. BUG=b:224884904 Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-25vendorcode/amd/pi: Fix building with clangArthur Heymans
Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25amd/cimx/sb800: Fix building with clangArthur Heymans
These are all set but unused variable problems. Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25drivers/intel/fsp2_0: Add native implementation for FSP Debug HandlerSubrata Banik
This patch implements coreboot native debug handler to manage the FSP event messages. `FSP Event Handlers` feature introduced in FSP to generate event messages to aid in the debugging of firmware issues. This eliminates the need for FSP to directly write debug messages to the UART and FSP might not need to know the board related UART port configuration. Instead FSP signals the bootloader to inform it of a new debug message. This allows the coreboot to provide board specific methods of reporting debug messages, example: legacy UART or LPSS UART etc. This implementation has several advantages as: 1. FSP relies on XIP `DebugLib` driver even while printing FSP-S debug messages, hence, without ROM being cached, post `romstage` would results into sluggish boot with FSP debug enabled. This patch utilities coreboot native debug implementation which is XIP during FSP-M and relocatable to DRAM based resource for FSP-S. 2. This patch simplifies the FSP DebugLib implementation and remove the need to have serial port library. Instead coreboot `printk` can be used for display FSP serial messages. Additionally, unifies the debug library between coreboot and FSP. 3. This patch is also useful to get debug prints even with FSP non-serial image (refer to `Note` below) as FSP PEIMs are now leveraging coreboot debug library instead FSP `NULL` DebugLib reference for release build. 4. Can optimize the FSP binary size by removing the DebugLib dependency from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary size is reduced by ~100KB+ and FSP-S debug library size is also reduced by ~300KB+ (FSP-S debug and release binary size is exactly same with this code changes). The total savings is ~400KB for each FSP copy, and in case of Chrome AP firmware with 3 copies, the total savings would be 400KB * 3 = ~1.2MB. Note: Need to modify FSP source code to remove `MDEPKG_NDEBUG` as compilation flag for release build and generate FSP binary with non-NULL FSP debug wrapper module injected (to allow FSP event handler to execute even with FSP non-serial image) in the final FSP.fd. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-25sb/amd/hudson/spi.c: Use C over CPP conditionalArthur Heymans
Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25mb/*/BiosCallOuts.c: Fix unused variableArthur Heymans
This fixes clang builds. Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25soc/amd/pi: Use -Wno-pragma-packArthur Heymans
Agesa headers extensively use and override pragma pack which fails to compile with clang. Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/pi/amd_late_init.c: Fix implicit enum conversionArthur Heymans
This fixes building with clang. Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25amd/fam*/northbridge.c: Remove unused reset_memhole variableArthur Heymans
Change-Id: I9231e0399d0b3ac6a608282571fc6d4aefad9dfb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25amd/fam*/northbridge.c: Fix unused hest variableArthur Heymans
The variable actually makes to code look a lot better. TESTED: BUILD_TIMELESS=1 results in identical binaries Change-Id: Ie9104e4736a3c30b7592bb0e79a8ddc6af579800 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25vendorcode/amd/agesa: Add CFLAGS required by CLANGArthur Heymans
Vendorcode is messy so instead of trying to fix the warnings thrown by clang ignore them on AGESA platforms. Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfieldsArthur Heymans
Clang complains about this. Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25nb/intel/gm45/pm.c: Make clang happyArthur Heymans
Clang complains that the terniary '?' operator is executed before the bitwise '|'. This is true and desired in this case. Being explicit about won't hurt however. Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2Anil Kumar
FSP 2.3 spec introduced new version of NV storage HOB FSP_NON_VOLATILE_STORAGE_HOB2. This new HOB addresses the limitation of FSP_NON_VOLATILE_STORAGE_HOB which can support data length upto 64KB. FSP_NON_VOLATILE_STORAGE_HOB2 allows >64KB of NVS data to be stored by specifying a pointer to the NVS data. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated from FSP 2.3 onwards and is maintained for backward compatibility only. This patch implements the parsing method for FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue to search for FSP_NON_VOLATILE_STORAGE_HOB HOB. BUG=b:200113959 TEST=Verified on sapphire rapids and meteor lake FSP platform that introduces FSP_NON_VOLATILE_STORAGE_HOB2 for retrieving MRC cached data. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25soc/intel/*/meminit.c: Fix formatted printArthur Heymans
This fixes building with clang. Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25soc/amd/noncar/memmap.c: Fix formatted printArthur Heymans
Fixes building with clang. Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25soc/amd/dmi.c: Fix implicit enum typingArthur Heymans
Clang complains about implicit enum typing so make it explicit. Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25include/efi: Add EFI Status code definitionsSubrata Banik
This patch adds EFI status code macros in `efi_datatype.h` to implement FSP debug event handler natively in coreboot. Added `PiStatusCode.h` and `StatusCodeDataTypeId.h` files for `UDK base >= 2017`, as these files were added with UDK version 2017. BUG=b:225544587 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25include/efi: Add correct header file for EFI_PROCESSOR_INFORMATIONSubrata Banik
This patch resolves compilation issue of including `efi_datatype.h` in other stage files due to unresolved EFI_PROCESSOR_INFORMATION macro definition. EFI_PROCESSOR_INFORMATION defined in `Protocol/MpService.h` hence, included to resolve compilation issue. TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd Reviewed-on: https://review.coreboot.org/c/coreboot/+/63010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25soc/mediatek/i2c.c: Remove unused variablesArthur Heymans
Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-25mb/google/skyrim: Increase RW_MRC_CACHE FMAP region sizeKarthikeyan Ramasubramanian
ABL generates memory training data whose size is ~80KiB. So increase the RW_MRC_CACHE region size to accommodate that. BUG=b:224618411 TEST=Build and boot to payload in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume BUG=b:194990818 TEST=Build guybrush Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25soc/amd/sabrina: update soft fuse bit 15 definitionFelix Held
For SoC that don't support LPC any more the definition of the PSP soft fuse chain bit 15 has changed. Earlier SoCs that still supported a physical LPC bus used this bit to determine if the I/O port 0x80 POST code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a physical LPC bus any more and on those this bit selects if the PSP debug output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that the needs to be decoded to eSPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25mb/google/brya: Adjust FMD file to chromeos.fmd for kanoDavid Wu
The separate FMD file for Kano is no longer required, as it was only required for early prototype testers, and those devices will be retired soon, therefore switch back to the original FMD file. BUG=b:226018550 TEST=Build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15Eric Lai
Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-25mb/dell/snb_ivb_workstations: Add Precision T1650 supportMichał Żygowski
Precision is a Mid Tower chassis platform with very similar mainboard to OptiPlex 9010. It has one more PCIe port and a PCI port. It also incorporates C216 chipset instead of Q77 and enables DRAM ECC support. Other changes are related to subsystem ID and fan control initialization. TEST=Boot Dell Precision T1650 and launch Debian 10. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-25mb/dell: Convert OptiPlex 9010 into directory with variantsMichał Żygowski
New boards like Dell Precision T1650 will be added as variants, in subsequent commit. They share most of the code, except some EC initialization tables, PCIe port configuration and subsystem ID. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-03-24soc/intel/common: Add APIs to check CSE's write protection infoSridhar Siricilla
The patch add APIs to check CSE Region's write protection information. Also, adds helper functions to get the SPI controller's MMIO address to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read protection details. During the coreboot image build, write protection is enabled for CSE RO. It is enabled through a Intel MFIT XML configuration. TEST=Verify write protection information of CSE Region Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-24drivers/net/r8168: Add support for Realtek RTL8111KRaihow Shi
The Realtek RT8168 and RTL8111K have a similar programming interface, therefore add the PCI device ID for the RTL8111K into driver for support. BUG=b:226253265 TEST=emerge-brask coreboot chromeos-bootimage. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-24driver/wifi: Add _DSM method for DDRRFIMVarshit B Pandya
coreboot needs to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This will be consumed by the Wi-Fi driver and it will act according to CB enablement configuration. This patch adds _DSM method for that. Add support for following 2 functions in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable Note: Wifi Dsm already has provision for SAR. This patch will add additional support to return RFIM structure based on UUID. BUG=b:201724512 TEST=Build, boot brya0 and dump SSDT entries Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x09 }) } If ((Local1 == One)){} If ((Local1 == 0x02)){} If ((Local1 == 0x03)) { Return (Zero) } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-24mb/google/brya/var/gimble: Include 4 new SPDsMark Hsieh
Add the four SPD files for LPDDD4 memory parts below to gimble: 1. Hynix H54G56CYRBX247 2. Hynix H54G46CYRBX267 3. Samsung K4UBE3D4AB-MGCL 4. Samsung K4U6E3S4AB-MGCL BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I143207cda066603051803b9008eb2e2364f16e46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILEKarthikeyan Ramasubramanian
This will allow configuring the concerned config through an external defconfig file. BUG=None TEST=Ensure that AMDFW_CONFIG_FILE is configurable. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 73331 -> 94623 VDD offset: 1893 -> 1847 SOC scale: 31955 -> 29904 SOC offset: 852 -> 756 BUG=b:217963719 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23amdfwtool: Change the some FW's level for A/B recoveryZheng Bao
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-23mb/google/skyrim: Fix Backlight GPIOJon Murphy
Backlight GPIO was set to HIGH, when it should have been set LOW to enable the backlight in the embedded display. BUG=b:224618411 TEST=load on Skyrim proto1, observe backlight Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °CJoey Peng
Change settings according to thermal team test results BUG=b:215033682 TEST=build and tested fan works normally on taniks Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfgZheng Bao
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B recovery. Both bootloader can be put in the fw.cfg. The amdfwtool decides which booloader is dropped in the directory. Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-03-23mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugsMichał Żygowski
Fix the HWM sequence matching to the chassis. HWM sequence for SFF was incorrectly passed to MT chassis HWM initialization. Vendor code also applies a fix-up for MT/DT chassis. This fixup was missing one register read compared to the vendor code. Add the missing read and guard the fixup depening on the returned value to match the vendor code behavior. Not doing so resulted in increased fan speeds on Dell Precision T1650 compared to Dell's firmware. TEST=Boot Dell Precision T1650 and hear the fans are as silent as on Dell's firmware Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-03-23soc/amd/common/psp_verstage: Write postcodes after ESPI initKarthikeyan Ramasubramanian
On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mohan Viswanathan Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23mb/google/dedede/var/beadrix: Enable LTE function by FW_CONFIG optionTeddy Shih
Enable/disable LTE function based on LTE field of FW_CONFIG. 1. GPIO control 2. USB port setting BUG=b:213582491 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62801 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23soc/intel/adl-n: Add device ID for TCSS XHCIMaulik V Vaghela
This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-23drivers/pc80/tpm/tis.c: Use fixed TPM ACPI pathMichał Kopeć
Windows 11 installer expects the TPM to reside under \\_SB_.PCI0 in ACPI device hierarchy, otherwise the TPM is not detected. Hardcode the path to fix the issue. TEST=Boot Windows 11 on Clevo NV41MZ and see the TPM is detected correctly TEST=Boot Ubuntu 20.04 on Clevo NV41MZ and see the TPM is detected correctly Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23mb/google/brya/var/primus{4es}: add delay time to rtd3-coldTerry Chen
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:224648680 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage test suspend stress 2500 cycles passed on primus Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23src/mediatek/mt8186: Implement sdram_size() to get real dram sizeXi Chen
Originally, dram size is hard-coded to 4GB by default. To support different dram size, calculate it from the mem chip info stored in CBMEM. BUG=b:206014043 TEST=Output "dram size: 0x100000000" on Kingler Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-23soc/mediatek: Save dram info to cbmemXi Chen
Store dram info in cbmem for ramstage or payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-22lib/device_tree.c: zero-initialize new DT nodesSergii Dmytruk
Prevents bad things from happening later when these new nodes are used. This issue is hard to observe because: 1. Heap is zero-initialized, so you need to use allocated memory filling it with non-zero values, free, allocate it again, use uninitialized. 2. Most of allocated memory is not freed. 3. Implementation of free() does something only for one last malloc'ed block, making most of freed memory unavailable for future allocation. Change-Id: I38a7ec1949d80f7a2564fac380ce94de6056a0c7 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62928 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22mb/google/brya/var/moli: Fix overridetreeTim Wawrzynczak
Commit 5a0ad1186 missed one chip config member that got converted to snake case in commit 215a97ee1. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Martin L Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfgTim Wawrzynczak
cr50_get_board_cfg() may be called in ramstage for some mainboards in order to determine the BOARD_CFG register's value. The code was written assuming that the firmware version was already retrieved, but for boards calling this in ramstage, this is not the case. Therefore, instead of using the cached cr50_firmware_version (which is all 0s in ramstage at that time), use the cr50_get_firmware_version function instead. BUG=b:225206079, b:220685274 BRANCH=firmware-brya-14505.B TEST=boot on brya0 and see: [INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94 [INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support in the logs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-22mb/google/brask/variants/moli: init overridetree for moliRaihow Shi
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf BUG=b:220814038 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22mb/google/brya/variants/crota: set up gpioTerry Chen
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC deviceFelix Held
Despite the SMBus device being function 0 of the FCH PCI device, the MMIO resource of the FCH IOAPIC is on the LPC device which is function 3 of the same PCI device, so move the FCH IOAPIC initialization code to the LPC device. Since the HPET was enabled in the same function, also move it to the LPC device initialization. TEST=On Mandolin both IOAPICs are still correctly detected by Linux. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22mb/google/brya/var/kinox: Modify DDR4 to non-interleavedDtrain Hsu
Kinox is designed to 8-layer PCB. In order to reduce the length of memory singals, the DDR4 is designed from interleaved to non-interleaved. BUG=b:210094309 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-22mb/google/brya/var/taeko: Disable GL9763e PCIE port L0sKevin Chang
GL9763e doesn’t support L0s state, so disable L0s at the root port. BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22soc/intel/{adl,common}: Add ASPM setting in pcie_rp_configKevin Chang
This change provides config for devicetree to control ASPM per port BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles on taeko. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919 Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin L Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22mb/google/brya/var/taeko: Enable Genesys L1 max entry delayKevin Chang
The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763EBen Chuang
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will be changed to expected value by sdhci-pci-gli driver in Linux v5.14. BUG=b:220079865 TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is 0x3FF. Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-03-21mb/google: Remove unused cpu deviceYu-Ping Wu
The cpu device listed in MediaTek platforms' devicetree.cb doesn't actually do anything, except causing an error during device initialization: CPU: 00 missing read_resources Therefore, remove it from the devicetree. BUG=b:224419346 TEST=emerge-corsola coreboot TEST=Krabby booted up successfully BRANCH=none Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21mb/amd/chausie: add APCB binaries if availableFelix Held
The APCB files that provide the firmware components running on the PSP some mainboard-specific information like the DRAM interface configuration. Those files aren't yet in the upstream 3rdparty/blobs repository, so only add those files if they are present and print that no APCB was added and the image won't boot if they aren't present. TEST=Both cases behave as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MBNikolai Vyssotski
To have enough space in the A/B RW sections, increase those sizes to 4 MByte and decrease the RO section size to 6 MByte to free up the space needed for that. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21ec/starlabs/merlin: Don't store EC values on changeSean Rhodes
Since CB:62741, the EC values are backed up to the CMOS when entering S3, S4 and S5. Consequently, they don't need to be stored when they're changed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If0ea392afae4a4d3c605cdea3c5896fbff606215 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-21ec/starlabs/merlin: Always store EC valuesSean Rhodes
The EC values will be changed when entering S3, S4 or S5, so move the function that stores the current settings outside of logic that restricts it to S4 or S5. This means the state isn't lost when entering S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-21mb/google/brya/var/banshee: Add WiFi SAR tableFrank Wu
Add WiFi SAR table BUG=b:225285426 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8fa833409bd69e080fda735c89015b9548252190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-21soc/intel/common: Add IOE P2SB for TCSSJohn Zhao
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB sideband access and exposes API for TCSS usage. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-21mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS=
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:211672259 BRANCH=firmware-zork-13434.B TEST=ALC5682I-VS audio codec can work Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-21mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS=
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:215292608 BRANCH=firmware-zork-13434.B TEST=ALC5682I-VS audio codec can work Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-21mb/google/brya/vell: Move WWAN devices for vellRobert Chen
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are add to overridetree.cb where WWAN is present for vell. BUG=none BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTORSridhar Siricilla
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. BUG=b:190588098 BRANCH=firmware-brya-14505.B TEST=Build the coreboot for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21mb/google/corsola: Revise power-on sequence of PS8640Rex-BC Chen
Although the panel initializes fine and the fw recovery screen is displayed without issues, the current power-on sequence of the PS8640 violates the spec of the PS8640, which can be confirmed by measuring it with an oscilloscope. The sequence is: - set VDD12 to be 1.2V - set VDD33 to be 3.3V - pull hign PD# - pull down RST# - delay 2ms - pull high RST# - delay more than 50ms (55ms for margin) - pull down RST# - delay more than 50ms (55ms for margin) - pull high RST# This flow will increase 110ms if firmware display is enabled in krabby. For normal booting flow, the firmware will not be enabled, so it will meet boot time requirements of Chrome OS. (Less than 1s.) Datasheet name: PS8640_DS_V1.4_20200210.docx. Chapter: 14. BUG=b:222650141 TEST=show fw display normally in krabby. TEST=result of waveform meets the spec. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-19mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLEDFelix Held
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, PSPP will be reenabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-03-19mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLEDFelix Held
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 14:05:39 +0000