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2024-11-14southbridge/intel/common: Improve ACPI _PRT method generationYuchi Chen
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be reused for multiple domains. Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-14soc/intel/alderlake: Display early Sign of Life for CSE FW SyncKarthikeyan Ramasubramanian
This will ensure that the user is informed about an ongoing CSE FW Sync. BUG=b:378458829 TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed during CSE FW Sync. Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-11-14soc/intel/xeon_sp: Reserve PRMRRGang Chen
PRMRR (Protected Region Memory Range Region) are not accessible as normal DRAM regions and needs to be explicitly reserved in memory map. Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-14cpu/x86/mtrr: Use fls/ffs from lib.hShuo Liu
Definitions of __fls/__ffs from lib.h and fms/fls from cpu/x86/mtrr.h are duplicated. Use definition from lib.h which is more generic. Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Suggested-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13vc/google: Refactor config to set Fn key scancodeKapil Porwal
Create a new config option to indicate that a board has Google Strauss keyboard. The scan code for Fn key will be set to 94 if the new config is selected. Previously each board was setting the integer config option for Fn key scan code which was not scalable. The new option is a bool and can be easily selected by different boards. BUG=none TEST=Verify coreboot.config before and after this change. Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13mb/google/fatcat/var/francka: Add HDA verb tablesIan Feng
We use ALC256 as HDA codec on francka, add the verb table. BUG=b:370668037 TEST=emerge-fatcat coreboot Change-Id: I579c9fd23c763d6791944732889021ffa03da448 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85036 Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwireVarun Upadhyay
This change adds support for the ALC721 codec in the device tree and enables it based on the fw_config. BUG=b:368495490 TEST=Boot on google fatcat board Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-13mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BTRui Zhou
When we use PCIE wifi7, CNVI BT and BT offload should be turned off. BUG=b:378053901 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-13soc/intel/alderlake: Use CSE sync in ramstage configSubrata Banik
This patch updates the eSOL rendering logic to use the SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of SOC_INTEL_CSE_LITE_SKU. The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to determine whether to render eSOL during ramstage. The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically indicates whether CSE synchronization is performed during ramstage, making it a more appropriate choice for this purpose. This change ensures that eSOL is rendered correctly during ramstage on platforms that require CSE synchronization. TEST=Able to render eSOL during ramstage for google/trulo. Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-13soc/mediatek/mt8196: Enable lastbus debug hardwareXiwen Shao
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out on the serial console for bus hanging analysis. TEST=build pass, and check log with: [INFO ] ******************* MT8196 lastbus ****************** [INFO ] --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 --- [INFO ] 00402504 [INFO ] c34b00d6 [INFO ] 61804050 [INFO ] 00051840 [INFO ] 10401610 BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com> Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-13mb/google/rauru: Pass reset gpio parameter to BL31Yidi Lin
Pass the reset gpio parameter to BL31 to support SoC reset. BUG=b:334753311 TEST=run reboot command Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84933 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13mb/google/rauru: Configure TPMYidi Lin
1. Add Google Ti50 TPM support 2. Configure I2C speed to I2C_SPEED_FAST_PLUS 3. Pass GPIO_GSC_AP_INT_ODL to the payload 4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now BUG=b:317009620 TEST=build pass, boot ok and there is no CR50 TPM timeout log Pass log: [INFO ] Probing TPM I2C: done! DID_VID 0x504a6666 [DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a) Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84932 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-13soc/mediatek/mt8196: Map LPDDR type to mem_chip_typeCrystal Guo
Implement map_to_lpddr_dram_type to convert MT8196 specific DRAM_DRAM_TYPE_T values to mem_chip_type. BUG=b:357743097 TEST=Firmware shows the following log: LPDDR5 chan0(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan0(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank1: density 12288mbits x16, MF 06 rev 0800 Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85099 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13mem_chip_info: Add LPDDR5 enums to mem_chip_typeCrystal Guo
Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85034 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13soc/mediatek: Obtain LPDDR type from trained memory infoCrystal Guo
Add lpddr_type to ddr_base_info struct to obtain LPDDR type from trained memory info. BUG=b:357743097 TEST=build pass Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85033 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-13soc/mediatek/mt8196: Add dram calibration supportJarried Lin
Add support for MT8196 DRAM calibration. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h. As MT8196's dramc_param struct size is different from other MediaTek SoCs, replace the hardcoded RW_MRC_CACHE size in common code with a constant derived from chromeos.fmd. The common emi.c can be reused for MT8196 as well, so remove the duplicate mt8196/emi.{c,h}. Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob. Test=Build pass BUG=b:317009620 Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85098 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16KJarried Lin
Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge RW_MRC_CACHE from 8K to 16K. TEST=Build pass BUG=b:317009620 Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85094 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-12drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP dataFelix Held
The basic flash parameter table described in JESB216F can be up to 23 DWORDs (92 bytes) long which is larger than the 47 byte SPI data buffer in the AMD SoCs which also contains the data from the command buffer except the command byte. TEST=Calling 'read_sfdp_data' with a data length of 256 bytes which is larger than the buffer of the AMD SPI host controller now works and returns the SFDP data expected from the W74M12JW SPI flash: 0x00: 53 46 44 50 06 01 02 ff 00 06 01 10 80 00 00 ff SFDP............ 0x10: 84 00 01 02 d0 00 00 ff 03 00 01 02 f0 00 00 ff ................ 0x20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ ... 0x80: e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb . ......D..k.;B. 0x90: fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 ..........@.. .R 0xa0: 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 ....6........cv3 0xb0: 7a 75 7a 75 f7 bd d5 5c 19 f7 4d ff e9 30 f8 80 zuzu...\..M..0.. 0xc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xd0: 00 00 f0 ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xf0: 38 9b 96 f0 a5 ad a5 ff ff ff ff ff ff ff ff ff 8............... Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-11-12drivers/spi: add RPMC info to spi_flash structFelix Held
Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info from the SFDP table. TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct has the expected entries (RPMC available, OP2 extended status as polling method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-11-12drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parametersFelix Held
JESD216F.02 and JESD260 were used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85008 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-12drivers/spi/spi_flash_sfdp: add basic SFDP supportFelix Held
Add basic support for the Serial Flash Discoverable Parameters (SFDP) standard which can be used to discover the parameters to interact with any SPI flash chip that supports this mechanism. This commit adds functionality to find specific SFDP parameter headers and print all SFDP parameter headers, but not to parse any SFDP parameter table. This is a preparation for a follow-up patch that adds support to parse the RPMC SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in the next patch, it's marked as static inline in this commit so that the code still build; the 'inline' keyword will be removed again in that follow-up patch. For now, only the legacy access protocol using single bit SPI transfers is supported, but this should cover most of the SPI NOR flash chips. In any other case, the code will error out. It's also assumed that the SFDP data blocks read from the SPI flash chip are small enough to fit into the SPI host controller buffer and don't need to be broken up into multiple transfers. This limitation will be addressed in a follow-up patch. JESD216F.02 was used as a reference. TEST=On a board with a W74M12JW SPI flash chip, calling 'spi_flash_print_sfdp_headers' prints this on the console output: Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 SF: Exiting 4-byte addressing mode SFDP header found in SPI flash. major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3 SFPD header with index 0: table ID 0xff00, major rev 0x1, minor rev 0x6 table pointer 0x80, table length DWORDS 0x10 SFPD header with index 1: table ID 0xff84, major rev 0x1, minor rev 0x0 table pointer 0xd0, table length DWORDS 0x2 SFPD header with index 2: table ID 0xff03, major rev 0x1, minor rev 0x0 table pointer 0xf0, table length DWORDS 0x2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-11-12soc/mediatek/**/spi.h: Enclose complex macros in parenthesesYu-Ping Wu
Fix the checkpatch error: Macros with complex values should be enclosed in parentheses Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-12mb/google/fatcat/var/francka: Override DRAM FreqSubrata Banik
Due to the hardware limitation on francka, reduce the memory speed to 7467 MT/s. BUG=b:373394046 TEST=emerge-fatcat coreboot Change-Id: I9c45c90952e20fc96943df03f591075338624e88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85102 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-12soc/intel/pantherlake: Add config option to limit DRAM frequencySubrata Banik
This patch adds a new config option to limit the maximum DRAM frequency for Pantherlake platforms. The mainboard code should try to set `max_dram_speed_mts` from override device tree if required. BUG=b:373394046 TEST=Able to build and boot google/fatcat. Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101 Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-12mb/google/brox: Do not select HAVE_ACPI_RESUMEKarthikeyan Ramasubramanian
Brox mainboard does not reliably support S3 entry/exit. Hence do not select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board reset if the system resumes from S3. BUG=b:337274309 TEST=Build Brox BIOS image and boot to OS. Ensure that the _S3 name variable is not advertised in the DSDT. Trigger a S3 entry and ensure that on S3 exit, the board reset is triggered. Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-12soc/intel/alderlake: Optimize reset handling for non-UFS bootSubrata Banik
This patch optimizes the reset handling in the Alder Lake romstage while disabling the UFS controller in an uni-boot scenario (a unified AP firmware image can boot both UFS and non-UFS systems). It introduces a check in `mainboard_expects_another_reset()` to skip unnecessary resets when a CSE slot switch is due, meaning CSE is not booting from the RW slot. This saves one reset for non-UFS SKUs when a CSE slot switch is pending. The patch also relocates the `cse_fw_sync()` call after disabling the UFS controllers to ensure the system reset flow can be better optimized and combined with any expected resets due to CSE synchronization. TEST=Able to build google/trulo eMMC sku and able to save one reset. Without this patch: 1. Warm reset after disabling UFS (1st reset) 2. Global reset after CSE sync (2nd reset) 3. Warm reset after disabling UFS (3rd reset) 4. Boot to OS With this patch: 1. Skip disabling UFS if CSE sync is due, aka no reset. 2. Global reset after CSE sync (1st reset) 3. CSE is booting from slot RW meaning CSE sync is done, perform UFS disabling and issue a warm reset after disabling UFS (2nd reset) 4. Boot to OS Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-12soc/intel/cmn/pmc: Perform PM register init for CSESubrata Banik
Before entering FSP-M, AP firmware must ensure the PM1_CNT register reflects the correct sleep state if a global reset occurred. This is crucial when Intel CSE has reset the system, as indicated by the global reset bit and wake status register. If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP firmware must enforce an S5 exit path before handing control to FSP-M for CSE initialization. This ensures proper system initialization and avoids potential issues caused by an inconsistent sleep state. Additionally, clears the PM1 status register (PM1_STS) after retrieving the power state. This prevents stale status information from persisting across power cycles, which could lead to confusion during subsequent boots. BUG=b:265939425 TEST=Verified that `prev_sleep_state` holds the correct value (5 for S5) after CSE performs a global reset. Fixes: Inconsistent sleep state after CSE reset. Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-11soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) configSubrata Banik
This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs (ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type for the RAMTOP range. Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was crucial to ensure data consistency, as WB caches both reads and writes. However, since the RAMTOP range now relies on WC MTRR, the role of CLFLUSH becomes less critical. Removing CLFLUSH in this scenario can improve performance, as it avoids unnecessary cache invalidations. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-11soc/intel/common: Apply Intel recommendation for early ramtop cachingSubrata Banik
Configuring the Early Caching Ramtop range as Write-Back (WB) before memory initialization is NOT RECOMMENDED. Speculative execution within this WB range can lead to issues. WB configuration should be applied to this range ONLY AFTER memory initialization is complete. To enable Ramtop caching before memory initialization, use Write-Combining (WC) instead of Write-Back (WB). This change applies the recommendation by always configuring the early ramtop caching range as WC. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85027 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-11-11soc/intel/common: Add RAMTOP size in ramtop_tableSubrata Banik
This patch adds a new field, `size`, to the `ramtop_table` structure to store the size of the RAMTOP region. The RAMTOP size is calculated as the difference between the cbmem top and the FSP reserved memory base address, aligned up to the nearest 4MB boundary. This change allows for more accurate tracking of the RAMTOP region and improves compatibility with different memory configurations. Previously, the RAMTOP size was always assumed to be 16MB. This could lead to boot hangs on systems with different memory configurations, where the actual RAMTOP size exceeded 16MB. By dynamically calculating and storing the RAMTOP size, this patch ensures that the correct memory range is used for intermediate caching, preventing boot hangs and improving boot speed. The `update_ramtop()` function is updated to write the calculated RAMTOP size to CMOS along with the RAMTOP address. The `early_ramtop_enable_cache_range()` function is also updated to use the RAMTOP size from CMOS to set the correct MTRR range. BUG=b:373290479 TEST=Built and booted successfully on various platforms. Verified that the RAMTOP size is correctly calculated and stored in CMOS Change-Id: I16d610c5791895b59da57d543c54da6621617912 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85003 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-11-11nb/via/cx700: Add south module devices to chipset.cbNico Huber
Change-Id: Ibd7a7b8c9e1461fa665bb72082489b9a48da63c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82767 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-11cpu/via: Implement cache as RAMNico Huber
The overall procedure is taken from the original code that was removed in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the start and end was updated (expect timestamp and BIST result in `xmm*' registers), stack is aligned to 16B, and linker symbols are now used for the CAR and cached XIP ranges. Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82766 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-11via: Start template for VIA C7 w/ CX700 northbridgeNico Huber
The first steps to bring C7 and CX700 support back mainline. Most is skeleton copied from the `min86' example. The romstage entry is placed in the northbridge code, as that's where we'll perform raminit. Support to read the FSB frequency is added right away, same for a reset function (using CF9 reset), as both are required for a minimal build test. A mainboard VIA EPIA-EX is also introduced for build testing, and in later stages boot testing as well. Links: DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-11mb/google/nissa/var/rull: Add ELAN touchscreen to devicetreeRui Zhou
Add Elan touchscreen override devicetree for rull based on the latest schematic NB7559_MB_SCH_V1_2024_1010.pdf. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. touchpanel function is normal and 'evtest' command displays the touch point Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85015 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-11soc/mediatek/common: Increase DEV_MEM memory range to 16GBJarried Lin
Map a proper DRAM range for memory test during calibration. TEST=memory test passed on Rauru BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/85035 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-11mb/google/var/riven: Optimize the stop delay for touchsreenKapil Porwal
Reduce stop delay for touchscreen based on the latest spec (EKTH6915 Product Spec_V1.0). This will optimize the touch response time to keep the S0ix resume time under 500ms. BUG=b:378012214 TEST=Verify improvement in resume time on Riven. Change-Id: Id7dcbc393bfae9bb62b5700bb9042a543152e968 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85039 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-11soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KBJarried Lin
Increase the bootblock size to support TPM. TEST=Build pass BUG=b:317009620 Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-11soc/intel/pantherlake: Update SAF base addressAnil Kumar
BUG=b:357011633 TEST=build and boot coreboot image on Google/Fatcat board. Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-10mb/hardkernel/odroid-h4: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I401e94b107612f8b7e8a73b3dbc12d7a5227ef01 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-10mb/google/fatcat: Fix typo and missing carriage return characterJeremy Compostella
Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca96 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-11-10device/device.h: Remove static.h includeNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h") and commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h to static.h"), sources that require access to the devicetree should directly include static.h. This allows static.h to be removed from device.h, eliminating many unnecessary dependencies on the devicetree for objects that only need the device types and function declarations. Now that static.h has been included throughout the tree where necessary, it can be removed from device.h. Change-Id: Ie72840c71ffca2ada82456dda6a2c813f6a6c3ad Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84590 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-10tree: Include static.h for remaining devicetree usagesNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h") and commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h to static.h"), sources that use code generated from the devicetree should directly include static.h. This allows static.h to be removed from device.h, eliminating many unnecessary dependencies on the devicetree for objects that only need the device types and function declarations. Add static.h to the includes of all remaining files that require static devicetree access through config_of_soc(), the sconfig generated names, or DEV_PTR(). Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84591 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-10mb/google/*: Explicitly include static.h for DEV_PTRNicholas Chin
As per commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h to static.h"), sources that require access to devicetree static devices should directly include static.h. This allows static.h to be removed from device.h, eliminating unnecessary dependencies on the devicetree for objects that only need the device types and function declarations. The DEV_PTR macro resolves to names declared in static_devices.h, which is then included in static.h, so include the header whenever the macro is used. Change-Id: I05662e601af00866b7f26f4c6c6794b491bf676e Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84678 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-10soc/*: Explicitly include static.h for DEV_PTRNicholas Chin
As per commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h to static.h"), sources that require access to devicetree static devices should directly include static.h. This allows static.h to be removed from device.h, eliminating unnecessary dependencies on the devicetree for objects that only need the device types and function declarations. The DEV_PTR macro resolves to names declared in static_devices.h, which is then included in static.h, so include the header whenever the macro is used. Change-Id: Ie281e9a9c015b19bfc96b83021a6e3afd98abcc3 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84677 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-10sconfig: Move (WEAK_)DEV_PTR from device.h to static.hNicholas Chin
Similar to commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), move these macros to static.h to separate dependencies on device.h and static.h. These macros resolve to device alises that are declared in the generated static_devices.h header, so move them to static.h which includes static_devices.h. Since static.h remains included in device.h, any source that uses these macros should still compile correctly. Subsequent commits will add static.h to files that need them, after which static.h can be dropped from device.h. Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84676 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-10soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-09arch/x86: Define macros for hard-coded HPET registersYuchi Chen
HPET General Capabilities and ID Register at offset 0x0 and Timer 0 Configuration and Capability Register at offset 0x100 are used to determine the generation of HPET ACPI tables. This patch adds macro definitions for these registers and fields. Definitions are from IA-PC HPET (High Precision Event Timers) Specification Revision 1.0a. Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-09soc/intel/common/block/imc: Add Integrated Memory Controller driverYuchi Chen
Intel common IMC contains an embedded SMBus controller for SPD data access. This patch implements IMC based SPD access supports through MMIO. Register definitons are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Tested-by: Yuchi Chen <yuchi.chen@intel.com> Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-09include/spd_bin.h: Add SPD IO layerYuchi Chen
By default, PCH SMBus codes will be called to retrieve SPD data. This patch adds a SPD IO layer so that SoC could implement its specific SPD IO layer functions such as using Integrated Memory Controller to get SPD data. Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84201 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-09include/device/pci_def.h: Add PCIe SRIOV definitionsYuchi Chen
Add SRIOV related definitions from section 9.3 of PCI Express Base Specification Revision 6.2. Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-09soc/intel/common/systemagent_server: Add server platform system agentYuchi Chen
Intel server processors have a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83318 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-09mb/google/fatcat: Add ISH support with FW_CONFIG toggleSubrata Banik
This patch adds support for the Integrated Sensor Hub (ISH) on the Fatcat mainboard. ISH can be enabled or disabled via FW_CONFIG bit 24. This allows for flexible configuration depending on the system requirements. The GPIO configuration for ISH is also updated based on CBI settings, ensuring correct initialization and communication. Verified that the device tree correctly probes ISH based on the FW_CONFIG setting: * FW_CONFIG with bit 24 set: ISH is probed successfully. * FW_CONFIG with bit 24 cleared: ISH is not probed. BUG=b:370984186 TEST=Verified ISH probing behavior with different FW_CONFIG settings using CBI. Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-08soc/intel/pantherlake: Update power limits configJamie Ryu
This updates power_limits_config for Panther Lake U and H. Source: Intel PTL PDG 813278 Intel PTL FSP Power limit profiles table BUG=b:357011633 TEST=Build fatcat and boot with Panther Lake SoC and RVP. Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2024-11-08device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0Jamie Ryu
This patch adds new DID0 PCI device IDs for Intel PTL-H. Additionally, updates the System Agent driver's `systemagent_ids` list and Panther Lake SoC bootblock to support these new IDs. Source: Intel PTL-FAS. Document Number 812562 BUG=b:347669091 TEST=Build fatcat and boot with Panther Lake SoC with newly added MCH ID. With patch, coreboot log: `[DEBUG] MCH: device id b004 (rev 00) is Pantherlake H` `[DEBUG] MCH: device id b00a (rev 00) is Pantherlake H` Change-Id: I56e795696f661d88828d7549f856eee19c46c942 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2024-11-08mb/google/rauru: Enable ChromeOS ECYidi Lin
1. Configure ChromeOS EC 2. Pass GPIO_EC_AP_INT_ODL to the payload TEST=build pass BUG=b:317009620 Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84931 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-11-08soc/mediatek/mt8196: Add SPI driver supportLiya Li
Add SPI controller driver code with support for 8 buses (SPI0 to SPI7). Test=Build pass, verify the wavefroms for SPI0~7 are correct. BUG=b:317009620 Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84930 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/mediatek/mt8196: Add PLL and clock init supportGuangjie Song
Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com> Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-08soc/intel/xeon_sp: Reduce stack usage by 18KiBPatrick Rudolph
Reduce stack usage of acpi_fill_srat_memory() by 18KiB. Directly write the SRAT table entries instead of using a temporary buffer on the stack. FIXES: Crash on ocp/tiogapass when writing SRAT table TEST: Still boots on intel/archercity_crb Change-Id: I91a6787ade8b465da7837b241c0aab00251f7de4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84832 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not namedPatrick Rudolph
When soc_acpi_name() returns NULL do not create the AML code. This prevents errors on the OS side when it tries to parse the AML code and doesn't find a name string for the device: ACPI Warning: Invalid character(s) in name (0x44415F08), repaired: [*_AD] Change-Id: I72225a975663a1028283437cac3b9231b7c77ead Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-08soc/intel/xeon_sp: Create SSDT for Gen6 LPC controllerLu, Pen-ChunX
In coreboot, LPC ACPI objects with its attached devices are usually provided by static DSDT. For Xeon-SP Gen6 LPC, its logical attached devices are created from dynamic SSDT (e.g. super IO). Create a simple SSDT for LPC in dynamic way as well to complete the device relationship chain. Fix below issues during Linux OS boot. The issue will block Windows OS boot as well. [ 22.986142] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.DI00.LPCB], AE_NOT_FOUND (20230628/dswload2-162) [ 22.986792] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) [ 22.987786] ACPI: Skipping parse of AML opcode: Scope (0x0010) Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84842 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/intel/xeon_sp/gnr: Enable IRQ routingShuo Liu
Enable IRQ routing per PCH IRQ usage convention and report domain _PRT. Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84328 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08mb/google/nissa/var/riven: Configure Acoustic noise mitigationDavid Wu
Follow the power team’s recommendation: - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:376165743 TEST=built firmware and verified by power team, the acoustic noise can be improved a lot. Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-08mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8Robert Chen
Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/intel/[tiger|cannon|meteor]lake: Fix uninitialized usb_cfg pointerKarthikeyan Ramasubramanian
This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/meteorlake/fsp_params.c: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild for GOOGLE_HATCH, GOOGLE_VOLTEER, GOOGLE_KARIS Change-Id: I169b6d3a979c4db78e7c0932a126d8b0a9306da7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85026 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-11-07soc/intel/cmn/block/cse: Add API to check the current boot partitionSubrata Banik
This patch introduces an API to check whether CSE is booting from the RW slot. This information can be used to determine if a CSE firmware update is pending, which would help to optimize the boot flow by knowing if any reset is expected due to CSE sync. TEST=Able to build google/brox. Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for RPL platforms. This patch selects the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_RAPTORLAKE is chosen. BUG=b:281846937 TEST=Able to build and boot google/brox and verify MRC version in CBMEM. Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07drivers/spi/spi_flash: introduce 'spi_flash_cmd_multi'Felix Held
A following patch that adds some support for reading the serial flash discoverable parameters (SFDP) data structures needs to send more than just the one command byte that 'spi_flash_cmd' supports. To be able to do this, introduce the 'spi_flash_cmd_multi' function which supports sending multiple bytes before reading back some bytes. The prototype is added to drivers/spi/spi_flash_internal.h since only other files in the same directory are supposed to be using that function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84789 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/amd/common/psp/rpmc: bring debug output in line with fmap sectionFelix Held
Call the PSP RPMC NVRAM 'PSP RPMC NVRAM' instead of 'PSP NVRAM' in the debug console output to not be misleading, since the RPMC feature uses the 'PSP_RPMC_NVRAM' fmap section and not the 'PSP_NVRAM' fmap section. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie89dfcfe4b8780f422c222477bb627e03bd3662d Reviewed-on: https://review.coreboot.org/c/coreboot/+/85007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-11-07mb/google/rauru: Add new board variant HyliaYang Wu
Add a new Rauru follower 'Hylia'. BRANCH=rauru BUG=b:376357839 TEST=emerge-rauru coreboot chromeos-bootimage Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-07mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)Mate Kukri
- Boots Linux 6.11 (Debian) - GRUB and SeaBIOS payloads work - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/admin/repos/deguard,general - Audio works - All USB ports work - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82053 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-07soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routedLu, Pen-ChunX
acpigen_write_PRT_pre_routed writes _PRT covering all direct subordinate child devices based on interrupt line/pin info from their PCI configuration spaces. It is required that IRQ routing and PCI configuration space update to be done ahead of time. TEST=Build and boot on intel/archercity CRB Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82253 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-11-07soc/mediatek/common: Use write32p and read32p for trackerYidi Lin
TEST=emerge-geralt coreboot Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84959 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/mediatek/common: Refactor `struct tracker`Yidi Lin
Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-07mb/cwwk/ald: Remove DIMM_MAXArthur Heymans
For ADL DIMM_MAX is a soc property and not a mainboard property. Change-Id: I834b631ffb9b7b2272ec631122de61136e55651a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84207 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07mb/google/nissa/var/rull: Add Fn key scancodeRui Zhou
The Fn key on rull emits a scancode of 94 (0x5e). BUG=b:372211281 TEST=Flash rull, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-07mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifiRui Zhou
The previous method made cnvi wifi6 configuration cumbersome and unusable. And delete unused pins. We abandoned the fw_config judgment method and changed to the better rtd3. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. wifi7&wifi6 function is normal Change-Id: Ia95dc9f6b707db63840de9b15b38bdaea48ea192 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85000 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-07mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXARTRui Zhou
Add Synaptics&PIXART init cpnfig, enable touchpad function BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. touchpad function normal Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84999 Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-07mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3Rui Zhou
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-07mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3HFabian Groffen
This board is based off ga-b75m-d3h, which uses the same SuperIO chip. It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with 2 SATA3 ports next to the 4 SATA2 ports. Flashing notes: These boards come with dual-BIOS feature. This is set of two unremovable what appears to be identical chips marked M_BIOS and B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have a payload and setup ready to boot a Linux system with iomem=relaxed or similar. Immediately use flashrom -p internal to flash the same firmware again. If you skip this step your next boot will show weird exception traces in either coreboot or your payload. Flashing from there via the chip is very difficult (you have to try many times in order to get a booting run), which can all be remedied by doing a flash from internal. I suppose the dual-BIOS feature is somewhat in the way here. Tested with: - CPU Core i7-3770S - RAM single bank 4GB CL11, two banks 4+4GB CL11 - OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload - Intel ME stripped - Integrated graphics with libgfxinit - (boot from) SATA2, SATA3 ports - Rear and mainboard connector USB ports, supporting boot - Atheros GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS events) - S3 suspend/resume - PWM FAN control, FAN speed readings - Temperature sensor readings Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Reviewed-on: https://review.coreboot.org/c/coreboot/+/77046 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07mb/asrock: Add Asrock Industrial IMB-1222 motherboardMaxim Polyakov
ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX motherboard [1]. Working: - Dual Channel DDR4 2933/2666/2400 MHz; - Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver); - DP (both), HDMI; - PCIe x16 Slot (Gen3); - SATA ports; - USB 2.0 ports; - USB 3.2 ports; - M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi); - M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1); - M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3); - LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps; - LAN2 Intel I219LM, 10/100/1000 Mbps; - Realtek ALC887 HD Audio (line-out, mic-in); - COM 1/2/3/4 ports; - onboard speaker; - HWM/FANs control (fintek f81966); - S3 suspend and wake; - TPM; - disabling ME with me_cleaner [2]; Payload: - Linux as payload; - LinuxBoot; - SeaBIOS; - edk2 [3]. Bootable OS: - Ubuntu 22.04 (Linux 6.5.0-15-generic); - Ubuntu 24.04 (Linux 6.8.0-41-generic); - Microsoft Windows 10 Pro (10.0.19045.4780, 22H2 2022); - Andoid 13, Bliss OS x86_64 (16.9.7, Linux 6.1.112-gloria-xanmod1). Unknown/untested: - USB3.0 in M.2 Key-B 3042/3052 slot; - eDP/LVDS; - PCIe riser cards; - SPDIF. There is no schematic/boardview, reverse engineering only. This port is based on system76/bonw14 because it has a similar topology. [1] https://web.archive.org/web/20220924171403/https:// www.asrockind.com/en-gb/IMB-1222 [2] XutaxKamay's me_cleaner fork, https://github.com/XutaxKamay/me_cleaner, v1.2-9-gf20532d [3] MrChromebox's edk2 fork, https://github.com/mrchromebox/edk2 uefipayload_2408 branch Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/intel/alderlake: Fix uninitialized usb_cfg pointerKarthikeyan Ramasubramanian
This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/alderlake/fsp_params.c:936:48: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84939 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/brox: Hint romstage init about upcoming resetKarthikeyan Ramasubramanian
Add support for the mainboard to check for any potential firmware component update and hence the assosicated reset. This indication can be used to avoid any redundant resets during the boot flow. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are provided correctly and 2 redundant resets are filtered out. Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-06ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_infoKarthikeyan Ramasubramanian
An unintended suffix got added in google_chromeec_get_pd_chip_info. Fix the typo by removing that suffix. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-06mb/google/brox: Reduce PL4 only for battery disconnected scenarioSowmya Aralguppe
This patch reduces PL4 only for no battery condition i.e. when battery is disconnected or not physically present. BUG=b:377305625 TEST=Build Brox and boot when the battery is disconnected Change-Id: I59a1028ce9cd3a6cf98f865d9c085a64f391f201 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h headerRonak Kanabar
This patch is to add FspProducerDataHeader.h header file to support MRC version Info in RPL. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06soc/intel/alderlake: select UDK_202305_BINDING for RPLRonak Kanabar
RPL FSP v5311 uses 202305 Edk2. Select UDK_202305_BINDING Kconfig for RPL SoC. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: I8dcc7d85cddadcce148ded5a81658253e8598413 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84722 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-06vendorcode/intel: Add edk2-stable202305 supportRonak Kanabar
Add edk2-stable202305 support for MTL and RPL FSPs. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202305 https://github.com/tianocore/edk2.git commit hash: ba91d0292e593df8528b66f99c1b0b14fadc8e16 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add following fixes from older Edk2 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements cf4c6fd225 Remove FSPM_ARCH_UPD config guard dc781d3a83 Define FSP_SIG macro for FSP 2.x compatibility d045074b91 Remove wchar_t asserts Change-Id: I96f0d0e393d31b325f9e42e3494556a2f6e1228e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8Hualin Wei
Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:366383364 TEST=Tested on Awasuki with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06soc/intel/jasperlake: add support for RP LTR mechanismLawrence Chang
Reserve Root Port LTR mechanism in FSP, in case some devices need to optimize LTR. BUG=366383364 TEST=Tested on Awasuki with RTL8852BE use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable bit is offset 68h[10]. 00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01) 00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20 20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08 50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00 60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00 a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00 e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00 f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84 Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84866 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Ruth <druth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xbRobert Chen
ext_vr_update should be run after board version 0xb, but skipped by return. Drawper LTE board version was set after 0x9, but there are more board added after that. Specific Drawper board version as 0xa, 0xb and 0xf. BUG=b:376828839 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage and test on DUTs. Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-11-06soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN configSubrata Banik
This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/screebo with single and dual displays, no redundant boot splash. Change-Id: Ifb0416df53a453ce16815f9fd52ec6b53fade5e2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81034 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/intel/coffeelake_rvp/cml_u: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. As I do not own this board, I cannot test whether is change is "functionally correct". However, I believe it is more likely that the original authors forgot to update the verb table size, rather than them adding additional verb data which was not meant to be used. TEST=`_Static_assert()` mentioned above does not fail anymore. Change-Id: I8df44e056bc841bfb344749ba214e6fb71a1955b Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/nissa/var/glassway: Add initial LTE related settingsDaniel Peng
1. Add DB_1C_LTE 4 on DB_USB fw_config. 2. Implement WWAN power sequencing. 3. Disable LTE-related GPIOs based on fw_config. 4. Add I2C SX9324 (P-sensor) support. Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf BUG=b:374666995 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Confirm the device node i2c-STH9324:00 created correctly, and command for # i2cdump -f -y 11 0x28 is workable. Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-11-06soc/mediatek/mt8196: Disable irq2axi featureRunyang Chen
Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/mediatek/mt8196: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 58ms in bootblock. (78ms -> 20m) BUG=b:361729697 TEST=check cbmem Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84897 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/rauru: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. BUG=b:361728592 TEST=The boot time improves 62ms Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-06mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configurationFelix Held
Looking at Intel document 759603 revision 001, Alder Lake N only has 5 PCIe clock outputs and clock request pins. I only have the version 2 of this board which has a significantly different USB port configuration to version 1, but there the Ethernet controller on RP 11 and the E key m.2 slot on RP 12 share the last PCIe clock output. The on-board TUBF0304 clock buffer chip takes the clock output form the last PCH PCIe clock generator output and drives the clock inputs of both the last Ethernet chip and the E key m.2 slot. Since the last clock output is always active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the non-existent clock output and request for RP 12 didn't break things. ASPM L0s might still work though, since that one doesn't involve switching off the PCIe reference clock, but haven't tested that yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83911 Reviewed-by: coreboot org <coreboot.org@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05mb/lenovo: Add ThinkCentre M920q (Coffee Lake)Maciej Pijanowski
It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here. Works: - Serial adapter from daughter board (COM1 connector) - USB ports front and back - USB-C port (charging, data) - HDMI - Ethernet - SATA - NVMe - internal speaker - TPM2.0 - PCIe x8 port (x8 riser tested, x4 not) Does not work: - front audio jacks Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05soc/amd/common/psp_smi_flash: refactor SPI controller busy checkFelix Held
Since the functions that call 'spi_controller_available' end up checking if the SPI controller is busy, refactor the function into 'spi_controller_busy' to simplify the logic on the caller's side. Also move printing of the notice that the SPI controller is busy to 'spi_controller_busy' to not have that duplicated in caller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc21ab6eacf07c4adffdb4658142c2f9dfcbf2a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84920 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05soc/amd/common/psp_smi_flash: factor out get_flash_deviceFelix Held
Since the RPMC-related functions will only need the spi_flash struct, but not the region_device struct of the store region corresponding to the 'target_nv_id', factor out 'get_flash_device' from 'find_psp_spi_flash_device_region'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84905 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ana Carolina Cabral
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 22:58:27 +0000