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2013-12-21haswell: add option to change DqPinsInterleavedStefan Reinauer
Some mainboards will need to have this set. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0 Reviewed-on: https://gerrit.chromium.org/gerrit/65722 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21wtm2: disable SDcard USB portDuncan Laurie
This is causing hangs in depthcharge (again?) so for now turn that port off so the resulting coreboot images are at least useful. Change-Id: I32c7774a95b0020b97105e0fa42c21ccb617c718 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65615 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Misc updates from 1.6.1 ref codeDuncan Laurie
These programming sequences were changed in the latest code. Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: Fix EC wake events in S5Duncan Laurie
The SMI handler code was setting S3 wake events when going into S5 and enabling a key press to wake the system. Change-Id: I6413ef1341e0149187df9f4f7e0c314d4c9e9c6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65323 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add a specific post code for S3 resume failuresDuncan Laurie
If the firwmare is flashed and the MRC cache is blown away then it is not possible to resume. Right now this can be inferred from the event log but it can be made very clear by adding a unique post code for this event. 1) boot falco 2) flash firmware 3) suspend and then resume 4) check for post code 0xef in log 0 | 2013-08-08 16:27:47 | Log area cleared | 4096 1 | 2013-08-08 16:27:47 | ACPI Enter | S3 2 | 2013-08-08 16:27:55 | System boot | 48 3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure 4 | 2013-08-08 16:27:55 | System Reset 5 | 2013-08-08 16:27:55 | ACPI Wake | S5 Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add Kconfig options to override Subsystem Vendor and Device IDDuncan Laurie
These can typically be set in the devicetree but we need a way to override those values with a Kconfig setting so as not to expose the Vendor ID before the product has launched. Change-Id: Ib382e6d9359d24b128c693a657ffde52604efad3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65310 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4455 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Force enable ASPM on PCIe Root Port 1Duncan Laurie
Boot on falco and look in /sys/firmware/log for the string "PCIe Root Port 1 ASPM is enabled" Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Add devicetree config option to force enable ASPMDuncan Laurie
The PCIe root port has ASPM settings/workarounds that are only applied based on the value of an undocumented bit in PCI config register 0x32C. If that bit is not set for some reason then the settings are not applied. This devicetree config option will force the ASPM settings for each port based on the bit map. Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Disable some verbose messagesDuncan Laurie
The default ME output is quite verbose and not all that useful unless you are actively debugging the ME and then you can enable the CONFIG_DEBUG_INTEL_ME option. This commit silences the firmware capabilities and the MBP output. Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4452 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Disable unused clocksDuncan Laurie
CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used and can be disabled. I couldn't test this directly without a scope so instead I used a modified commit that also disabled PCIe Port 0 and saw that that correctly disabled the WLAN port. Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4451 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Support ICC clock enables messageDuncan Laurie
This message allows unused clocks to be disabled based on a devicetree setting in each mainboard. Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65250 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4450 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Allow for more than MKHI MEI messagesDuncan Laurie
The original ME code was assuming that the only type of messages it would send were MKHI type and so it had some embedded checks for that header and that type of message. In order to support ICC messages this needs to change to handle different header types, so now the header will be sent first and then the data will follow, rather than the two both being sent in the same low-level function. This change has no real affect on the system, subsequent commit will add new ICC messages. Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4449 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Enable EC controlled throttlingDuncan Laurie
When the EC requests the host to throttle (for charging or thermal related reasons) the package power consumption will be limited. Right now this is set at 12W but that is somewhat arbitrary and may need tuning. 1) define the THRT method in \_TZ scope for EC to call 2) enable SCI events for throttle start and stop 3) define the power limit at 12W and set it in NVS 1) Enable CONFIG_ACPI_DEBUG=y in the kernel 2) Enable the Debug object event in acpi module acpi.debug_layer=0x7f acpi.debug_level=0x2f 3) Using EC console generate host event for throttle start > hostevent set 0x20000 4) Check dmesg for throttle start events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988) [ACPI Debug] String [0x12] "EC: THROTTLE START" [ACPI Debug] String [0x10] "Enable PL1 Limit" 5) Using EC console generate host event for throttle stop > hostevent set 0x40000 6) Check dmesg for throttle stop events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0) [ACPI Debug] String [0x11] "EC: THROTTLE STOP" [ACPI Debug] String [0x11] "Disable PL1 Limit" Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63989 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4416 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21chromeec: Add event methods for EC requested throttleDuncan Laurie
Two new events possible from the EC for starting and stopping throttle. These are handled in a per-board method that is defined under the thermal zone. This is not quite where I wanted it but the scoping rules in ACPI don't let me have a defined external object in the same scope. Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63988 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4415 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Drive GPIO59/LTE_DISABLE_L low on S3/S5Duncan Laurie
Try to prevent WWAN from causing spurious wakes. Change-Id: Ifcc44063de0eb1634cab9dd244737071568e3455 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63987 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4414 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Add missing elements to the edid data structureGabe Black
When the edid data structure changed a while ago, it caused hangs on snow which were fixed by adding those missing members. Unfortunately we didn't realize that pit needed the same fix. Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63646 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4389 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21tpm: provide explicit tpm register accessAaron Durbin
An issue was observed using a specific vendor's TPM in that it chokes on access to registers that are not explicitly defined in the PC client specification. The previous driver used generic access functions for reading and writing registers. However, issues come to play when reading from the status register. It read it as a 32-bit value, but that read address 0x1b which is not defined in the spec. Instead of using generic access functions for the tpm registers provide explicit ones. To that end provide more high level wrapper functions to perform the semantic access required. Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4388 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Bump the EC SPI bus speed up to 5 MHzGabe Black
That speed is used with U-Boot instead of the more conservative 500 KHz. Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63193 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4386 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Fix some clock settingsGabe Black
Some registers and bit fields were wrong, but the difference is mostly academic since the code that uses them are never called. Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63189 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4385 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Fix the clock divisor maskGabe Black
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide. Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63188 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21arm: Don't use const pointers with the write functionsGabe Black
This functions are by definition changing the data pointed to by their arguments, so they shouldn't by const. Change-Id: Id29b3f76526aba463f8bb744f53101327f9c7bde Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63777 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4400 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Get rid of the PWM code like on the 5250Gabe Black
The timer code was supposed to be using the mct, and also using the monotonic timer infrastructure instead of the get_timer function. This change had been made for the 5250 but not yet for the 5420. Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64159 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4418 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Get rid of the PWM timer code we shouldn't be using anymoreGabe Black
This code was left over from U-Boot and was superceded by the MCT. Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63778 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4401 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Apply pwm const fix to the 5420 as wellGabe Black
When the const was removed from write function arguments, a related bug in the 5250 code was fixed so that it would still compile. Unfortunately, that same change needed to be made to the 5420. Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64154 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4417 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Fix consts in the pwm codeGabe Black
The code generally intended to make the pointer const instead of the thing it pointed at, but it had const backwards. Sometimes both the pointer and the data could be const, but sometimes there were writes where only the pointer should be. Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63775 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4397 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21falco: add rtd2132 settings to device treeAaron Durbin
Now that the rtd2132 device has the full settings the panel timings need to be implemented. Sadly, the Tx timings in the rtd2132 aren't 1:1 with the panel's Tx timings. Below is the table equivalent: RTD2132 | Falco Panel --------+------------ T1 | T2 --------+------------ T2 | T8+T10+T12 --------+------------ T3 | T14 --------+------------ T4 | T15 --------+------------ T5 | T9+T11+T13 --------+------------ T6 | T3 --------+------------ T7 | T4 --------+------------ Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65858 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21rtd2132: implement full configurationAaron Durbin
It has been disseminated that the RTD2132 chip needs to be fully programmed for settings to take affect. Most of the settings are note documented very well and present themselves as magic values. Also, the wait time for starting the sequence needs to be bumped from 2ms to 60ms. Lastly, expose all the known settings through devicetree. Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65857 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Remove PS/2 keyboard initialization on resume from S3Martin Roth
When we go through the resume path, there shouldn't ever be a need to initialize the PS/2 keyboard. The OS is going to reinitialize it anyway, and it just slows the resume. Verified Code flow in normal boot/S3 resume with print statements. Verified Keyboard was correctly disabled and flushed by booting to recovery mode screen while pressing keys on the integrated keyboard. Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63648 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4396 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add simple hexdump functionStefan Reinauer
- prints hex and ascii - detects duplicate all zero lines Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62655 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4392 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: set PWM to external on ParadeRonald G. Minnich
The PWM is controlled externally from the APU. Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61513 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4363 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: move parade writes to mainboard.cRonald G. Minnich
What gets written into the parade is highly mainboard-dependent. So the parade_writes array needs to be there. Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61486 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21peppy: Drive WLAN_DISABLE_L / BT_ON low in S3 and S5.Shawn Nematbakhsh
When the board is in S3 and S5 the WLAN_DISABLE_L signal can leak power into the WLAN power well since the GPIO controlling WLAN_DISABLE_L is in the suspend well. Therefore, drive WLAN_DISABLE_L low to avoid the power leak. This is a clone of a Falco change: I1a0df80dd47fdbd535aca7a9d49253794c480606. Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63220 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4383 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Added structure members x_mm and y_mm to edid decodingFurquan Shaikh
Change-Id: I9a628cec4da127a3f072d9611259dad99dfa9d29 Reviewed-on: https://gerrit.chromium.org/gerrit/63125 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4382 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21FUI: Fill in link_m and link_n valuesFurquan Shaikh
... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Slippy: remove unneeded code in i915io.cRonald G. Minnich
This code is left over from what the VBIOS did; It is redundant. Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62290 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4380 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: Route USB to XHCI on resumeDuncan Laurie
Turn on the pei_data flag that will instruct the reference code binary to route all USB ports to the XHCI controller on resume and disable the EHCI controller(s). Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63798 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4404 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Add pei_data field for USB routingDuncan Laurie
The linux kernel will unconditionally route all USB ports to the XCHI controller at boot. The EHCI controller can then be disabled, and it should be left disabled by the reference code when this is done. However not all OS may do this unconditional route, so provide an option to the reference code binary to enable this behavior. Change-Id: Iedf5af54182bf109cd1119c1999e46300665d41e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63797 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4403 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell boards: fix SATA interrupt in ACPIDuncan Laurie
SATA is routed to PIRQG which should be interrupt 22 and not interrupt 21. The kernel uses MSI with this device so this is only seen when booting with pci=nomsi Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63796 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Update microcode revisionDuncan Laurie
CPUID 306C3 Haswell MOB C-0 microcode to 12h CPUID 40651 Haswell ULT C-0 microcode to 15h localhost ~ # grep microcode /proc/cpuinfo microcode : 0x15 microcode : 0x15 Change-Id: Ibdfe2b8ef0969b1ccc6dd1642a9fc352b5d11f27 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: update ACPI C-state settingsDuncan Laurie
Since these boards do not support C10 we should not bother advertising that state in the ACPI _CST. Instead use this map: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Avoid any ME device communication in S3 pathDuncan Laurie
The management engine is occasionally hanging the system on resume when it is accessed. Since we actually don't need to do anything with it on resume it can be disabled early in the resume path and avoid assigning resources just to remove them later. suspend/resume on falco and check /sys/firmware/log to ensure that device 00:16.0 is disabled early and that no resources are probed or assigned and that the device init path does not execute. Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint me: add support for mbp clear wait in finalize stepDuncan Laurie
The management engine is slow, requiring at least 500ms between when the Dram Init Done message is sent (right after memory training) to when the MBP will report that it is successfully cleared and that the ME can finally be sent the EOP message. Currently this is adding 100-150ms to the boot time. If we defer waiting for the MBP Clear indicator until the finalize step we can gain back that lost time. boot on falco with SMI debugging enabled to ensure that the ME is locked down in the finalize step: Finalizing Coreboot SMI# #0 SMI_STS: PM1 APM ME: MBP cleared ME: mkhi_end_of_post ME: END OF POST message successful (0) Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint xhci: Add ACPI D0/D3 workaroundsDuncan Laurie
There are specific programming requirements for the usb3 ports on all LynxPoint chipsets when transitioning to D0 or D3. LynxPoint-LP has additional workaround steps needed involving resetting the disconnected ports when transitioning to D0. The workarounds are implemented in ACPI code so the controller can transition properly into D3 at runtime. Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62632 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4374 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Revert "lynxpoint: Move ME lock down to ramstage"Duncan Laurie
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965. Deferring this step until the finalize stage will allow us to defer waiting for the MBP clear indicator and speeding up the boot. Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559 Reviewed-on: https://gerrit.chromium.org/gerrit/62631 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: power management setup tweakDuncan Laurie
Updated from 161 ref code Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c Reviewed-on: https://gerrit.chromium.org/gerrit/62128 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4372 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21SLIPPY: final changes for FUIRonald G. Minnich
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back that we need. There are two new files for slippy annotated with comments about how it needs to evolve. That said, this code has been tested on 3 different panels. Both dev and non-dev usages work. physbase initialization to static value removed. Moved spin calls to intel_dp_* Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61136 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4370 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21peppy: Duplicate SPD data for 2GB configurations.Shawn Nematbakhsh
Peppy SPD table has 4GB configurations followed by 2GB configurations. Current implementation does remapping to point 2GB configuration to the same SPD index as the 4GB. This is different than Falco, which simply duplicates the SPD data for all configurations. To simplify probing in mosys, copy the Falco implementation of duplicating SPD data. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idb185a437f3cf4f40d2dae1ae59c30235df8f489 Reviewed-on: https://gerrit.chromium.org/gerrit/61847 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Jay Kim <yongjaek@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4369 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21chromeos: Check for recovery reason code in shared dataDuncan Laurie
When using RW firmware path the proper recovery reason can be retrieved from the shared data region. This will result in the actual reason being logged instead of the default "recovery button pressed" reason. 1) build and boot on falco 2) crossystem recovery_request=193 3) reboot into recovery mode, check reason with <TAB> 4) reboot back into chromeos 5) check event log entry for previous recovery mode: 25 | 2013-07-15 10:34:23 | Chrome OS Recovery Mode | Test from User Mode Change-Id: I6f9dfed501f06881e9cf4392724ad28b97521305 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61906 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4368 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21haswell boards: Use PECI temp sensor id 0Duncan Laurie
The EC temperature sensors were renumbered and now PECI is at index 0. 1) boot on falco 2) check /sys/class/thermal/thermal_zone0/temp 3) check 'temps' on ec console Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61896 Reviewed-on: http://review.coreboot.org/4367 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21falco: Enable RTD2132 spread spectrum at 1.0%Duncan Laurie
This may need further tuning but will start at 1.0%. boot on falco and check /sys/firmware/log localhost ~ # grep RTD2132 /sys/firmware/log RTD2132: Enable 1.0% Spread Spectrum I2C: 01:35 (Realtek RTD2132 LVDS Bridge) Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61895 Reviewed-on: http://review.coreboot.org/4366 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21rtd2132: Add driver for Realtek RTD2132 LVDS bridgeDuncan Laurie
This driver allows the mainboard to enable spread spectrum clocking at 0.5%, 1.0%, and 1.5% with devicetree settings. Change-Id: I59c61e67aa8e951fd9904ad951deb6d0ba29669e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61894 Reviewed-on: http://review.coreboot.org/4365 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21lynxpoint: Add LPT-LP device id and smbus_write_byteDuncan Laurie
This is needed for SMBUS drivers to write to devices. It was copied from existing intel southbridge driver. Change-Id: Id0ce2393b2946a9c741413bca563a1a4dc0a4f5e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61893 Reviewed-on: http://review.coreboot.org/4364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21bolt: make the gpio interrupts edge sensitiveAaron Durbin
The drivers in the kernel expect the devices using gpios to generate interrupts to be edge sensitive. Make it so. Change-Id: I920ef621682d33ba081f737e97f0239f903db2f7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61678 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4361 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-20armv7: Remove SYS_TEXT_BASE config.Hung-Te Lin
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory layout, remove it from current configurations. Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b Reviewed-on: https://gerrit.chromium.org/gerrit/61853 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4371 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-19ec/lenovo/h8: Enable 3G modemVladimir Serbinenko
Just like bluetooth and wlan it need to be enabled in EC. Set the appropriate bit in EC if CMOS config says so. Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4516 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-18lynxpoint: Don't write to non-existent EHCIDuncan Laurie
The LynxPoint-LP chipset only has one EHCI controller so we should not attempt to write into the second one that only exists on LynxPoint-H. Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-17cpu/intel: Do not rely on CBFS microcode having a terminatorAlexandru Gagniuc
Up until now, a dummy terminator was required for CBFS microcode files. This was a coreboot only requirement in order to terminate the loop which searches for updates. Figure out where the microcode file ends, and exit the loop if we pass the end of the CBFS without finding any updates. Change-Id: Ib61247e83ae6b67b27fcd61bd40241d4cd7bd246 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4505 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-17device/dram/ddr3: Move CRC calculation in a separate functionAlexandru Gagniuc
Calculating the CRC of a SPD may be useful by itself, so split that part of the code in a separate function. Change-Id: I6c20d3db380551865126fd890e89de6b06359207 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4537 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-16X60/T60: Implement "next display output" button.Vladimir Serbinenko
Most of the code needed for this is already in the tree with X201 patch series but code didn't know where to send the next screen notification and so was disabled. Define right video device. Tested by: Sam Noble Change-Id: I4ff0d220afdca342617ce43c6e5d0164ad8eba27 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4494 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-16qemu/videoinit: Set required fields in fake EDIDVladimir Serbinenko
x_resolution, y_resolution and bytes_per_line were not inited. Without them coreboot sweared that screen is 1108630x1142817 and payload tried to draw on such a big screen. Change-Id: I0d0277a20c7e1976c27af4a57651ab2be0f9c5d7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4535 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-15lenovo/x201: Add support for Lenovo X201 (Calpella-based laptop)Vladimir Serbinenko
Was extensively tested on my X201. More info on the wiki Change-Id: I503d77749780422e446b48224ca98a1f22a2c180 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4514 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-15ec/lenovo/h8: Fix peripheral init without CMOS configVladimir Serbinenko
Currently H8 skips important init if unable to access CMOS config. Change default to enable all features to have a sane system without using CMOS config. Change-Id: I4448ccd21beae8ad23eb22391770c6fe3b83e3b4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4515 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-15intel/cougar_canyon2/Kconfig: Remove HAVE_ACPI_RESUME as S3 is unsupportedPaul Menzel
According to the commit message for the board Cougar Canyon 2 (48a749a8) resuming from S3 is currently unsupported. The FSP does not support S3 at this time. S3 may be added when it is available in the FSP. Mirror that in the configuration by not selecting the Kconfig option `HAVE_ACPI_RESUME`. Change-Id: I894f103ffa7d8db6342f99fff0867b02bc750752 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4519 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-14drivers/pc80: Add ACPI description.Vladimir Serbinenko
AT controller needs an ACPI node, otherwise FreeBSD doesn't detect keyboard and mouse. Currently each SuperIO adds its own description. This one should be used in the future instead. Change-Id: Iaad5ed3846c6d9f467a02a286a1e6f60a3607af5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4518 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-13cpu/amd: Remove error messages on non-matching microcode patchesKyösti Mälkki
Microcode update file contains patches for various processor revisions, it is not an error to have those. Change-Id: Ifbca26276b66f17092afe249a2cfc229713a9fec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4520 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates from a CBFS file is supported, however, the name implies that microcode is present in CBFS. This has recently caused confusion both with contributions from Google, as well as SAGE. Rename this option to SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is "hey, the code we have for this CPU supports loading microcode updates from CBFS", and prevent further confusion. Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4482 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2013-12-12EDID: add fields specialized to the needs of framebuffersRonald G. Minnich
Now that we have horizontal display areas that are not multiples of 32 bytes, things are more complex. We add three struct members (x, y resolution and bytes per line) which are to be filled in by the mainboard as it sets the mode. In future, the EDID code may take a stab at initializing these but the values are context-dependent. Change-Id: Ib9102d6bbf8c66931f5adb1029a04b881a982cfe Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60514 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4336 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12bolt: Initial mainboard commitDuncan Laurie
BUG=chrome-os-partner:20448 BRANCH=none TEST=emerge-bolt chromeos-coreboot-bolt Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59843 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4330 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12HDA: Enable Mini-HDA and fix up PCH-HDA initDuncan Laurie
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0 which uses the same verb table init sequence as the southbridge. In order to avoid two copies of the verb table loading code I separated out the HDA verb table functions into a file that can be re-used and then added a minihd driver to the haswell northbridge. The minihd verb table is the same across devices so it can live within the minihd driver rather than needing to be specified in each separate mainboard. I also fixed up the driver for lynxpoint HDA by following the reference code. Without HDMI cable plugged in driver does not find any codec, and it does not seem to re-probe when HDMI is connected. We may be missing kernel patches for this. hda-intel 0000:00:03.0: no codecs found! With a basic kernel patch to add 0x0a0c device ID to HDA driver and with HDMI cable connected it is much happier: snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9 snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10 input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11 Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12slippy/falco/peppy: make GPIO interrupts be edge triggeredDuncan Laurie
The drivers are designed to work with an edge triggered interrupt. Change-Id: I35a121ecfb6409bb9049f4d1e034185bb3bb7557 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4360 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12EXYNOS5250: be less chatty at critical momentsRonald G. Minnich
The 5250 DRAM code is *really* chatty. That's not a great idea in time critical code, and DRAM init is generally very sensitive about such things. Finally, for those things that are errors, print them at an error level, not a debug level. Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60100 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4359 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12falco: drive WLAN_DISABLE_L low in S3 and S5Aaron Durbin
When the board is in S3 and S5 the WLAN_DISABLE_L signal can leak power into the WLAN power well since the GPIO controlling WLAN_DISABLE_L is in the suspend well. Therefore, drive WLAN_DISABLE_L low to avoid the power leak. Change-Id: I1a0df80dd47fdbd535aca7a9d49253794c480606 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61421 Reviewed-on: http://review.coreboot.org/4358 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12exynos5250: Correct DDR3 Phy-reset value names.Hung-Te Lin
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real phy-reset is a low-active pin, so "off(0)" will trigger "start to reset". To prevent confusion, we should rename the constants to "RESET_ENABLE" and "RESET_DISABLE". Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9 Reviewed-on: https://gerrit.chromium.org/gerrit/61081 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4357 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12haswell: Fix up GPU power management setupDuncan Laurie
New/more magic values from latest ref code. Change-Id: Ia2655333b4daca86c2f2a76f5edcd55cdaf3f851 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61334 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4356 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
These are needed to enable workarounds/features on specific CPU types and stepping. The older northbridge function and defines from sandybridge/ivybridge are removed. Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61333 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4355 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12exynos5420: Setup clocks for MMC bus controller.Hung-Te Lin
To configure source clocks on Exynos 5420 for MMC drivers. Some registers are different from the 5250. FSYS now has two parts and MMC uses FSYS2. The MMC block uses MPLL as the clock source. The "high-speed" MMC interface runs as 52MHz, so divider is set accordingly. Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller Interface) to DWMCI (DesignWare MMC Controller Interface). Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60858 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4354 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: Add backward-compatible RAM_ID table.Shawn Nematbakhsh
Make use of google_chromeec_get_board_version to determine board version, and apply proper RAM_ID table to load correct SPD. Change-Id: I6a2d54759cf2ce98bf53df0db396c6e09368c714 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61192 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-on: http://review.coreboot.org/4353 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12Peppy: Update Realtek ALC283 verb tableMartin Roth
Update peppy's verb tables for the Realtek ALC283 Audio Codec. ALC283 Configuration: Digital Mic - NID 12h: Disabled Speakers - NID 14h: Enabled Mono out - NID 17h: Disabled Mic 1 - NID 18h: Disabled Mic 2 - NID 19h: Headphone Jack Line1 - NID 1Ah: Internal Mic Line2 - NID 1Bh: Disabled PCBEEP - NID 1Dh: Enabled SPDIF - NID 1Eh: Disabled HP-OUT - NID 21h: Headphone Jack Mic 1 doesn't seem to really be available, but the documentation refers to NID 18h as MIC1, so it's being disabled as it's not being used. The onboard microphone has been moved to line 1. I had my peppy modified to attach the mic to line1 and mic1 now works with this patch. Mic2 looks harder to rework, so I think that will have to wait for the DVT boards. Change-Id: I7d6ce6b428806b6aed1d36e7e25302fa5ae14b21 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/58880 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12chromeec: Allow get_board_version to be called from romstage.Shawn Nematbakhsh
We will soon need to call google_chromeec_get_board_version to determine correct DDR SPD. We must do so before DDR is initialized, so allow this function to be called from romstage. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I882d84e38d11bf66067193a6f408f941f2cf8a81 Reviewed-on: https://gerrit.chromium.org/gerrit/61191 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12falco: fix usb port settingsDuncan Laurie
USB2 Port A set to 6.4" and Back Panel USB2 Port B set to 5.2" and Back Panel USB2 Port C set to 12.3" and Internal Other devices all set to Internal. build and boot on falco and check settings. Based on the config settings all ports end up with tuning param 1 == 5 and param 2 == 2 U2ECR[0] = 0x00059501 U2ECR[1] = 0x00059501 U2ECR[2] = 0x00059501 U2ECR[3] = 0x00059501 U2ECR[4] = 0x00059501 U2ECR[5] = 0x00059501 U2ECR[6] = 0x00059501 U2ECR[7] = 0x00059e01 Change-Id: I6b9e6df2679036a501355e6b389a486a6f178f99 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61297 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4350 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12Log device path during resource allocationDuncan Laurie
Systems are hanging in dev_configure() without a log to indicate which device is being processed. Add some logging points to save the device path before talking to the device so we can narrow in on which device is the problem. Change-Id: I3751c19a1ea68cdccbc33e4f6b2eeddd1bd9f2e4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61296 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4349 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12haswell: Update ULT microcode to rev 14hDuncan Laurie
localhost ~ # grep ^microcode /proc/cpuinfo microcode : 0x14 microcode : 0x14 Change-Id: I839f29cff61abf798a619b30ad945e25c79f548f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60658 Reviewed-on: http://review.coreboot.org/4348 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12falco: Remove thermal thresholds that use CTDPDuncan Laurie
This CPU does not support Configurable TDP and so far does not need to use Controllable TDP. Change-Id: I15599cd4e6890dd5c9d9f99bc4e95307a8dcc827 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60657 Reviewed-on: http://review.coreboot.org/4347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12armv7: Fix dcache_clean_by_mva.Hung-Te Lin
The OP assigned by dcache_clean_by_mva must be handled in dcache_op_mva. Change-Id: Ia7631a08be6afacb13dfff406ac4db20efc98926 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61076 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4343 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12PIT: remove a comment that is incorrect.Ronald G. Minnich
The is_resume comment is wrong for this board. It only applies to the older 5250 cpu. In fact, the is_resume parameter is not needed for ddr init and will likely be removed soon. Change-Id: I4e3c92fcaaa75d3c9223d90acccf053f61406307 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60103 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4342 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12snow: Fix the edid data structure definition so depthcharge works again.Gabe Black
Some new fields were added to the edid data structure, and the edid code was changed to put estimated values into those fields which were ultimately passed into depthcharge or other payloads. On snow we do things different and just declare an edid structure statically which didn't have those members. The rows and columns of the graphics console were 0, and that confused the framebuffer driver and made it loop forever. Change-Id: I6ca3bd948482b347a6a981e83b82b10dca995e5e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61057 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: RAM_ID + storage changes for next build.Shawn Nematbakhsh
- Update RAM_ID table. - Add DEVSLP0 signal to NGFF SATA port. Note: After this change, old Micron 2GB boards will no longer boot. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id68a1d6ace2702cca9c37305726cd55a0bde5005 Reviewed-on: https://gerrit.chromium.org/gerrit/60167 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org> Reviewed-on: http://review.coreboot.org/4340 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: Disable audio codec enable GPIO in S3 + S5.Shawn Nematbakhsh
To save power, disable audio codec in S3 + S5. Also, refactor Lynxpoint GPIO code slightly to allow usage in SMM binary. Change-Id: I55c4248c89a258b5e4cecf8579eb58f1c15430c0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60950 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4339 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-09Refactor usage of walkcbfs to permit access to CBFS headersAlexandru Gagniuc
walkcbfs() is used only with ROMCC. Besides finding stages during the bootblock, it's also used when applying microcode updates during the bootblock phase. The function used to return only a pointer to the data of the CBFS file, while making the header completely inaccessible. Since the header contains the length of the CBFS file, the caller did not have a way to know how long the data was. Then, other conventions had to be used to determine the EOF, which might present problems if the user replaces the CBFS file. This is not an issue when jumping to a stage (romstage), but can present problems when accessing a microcode file which has not been NULL-terminated. Refactor walkcbfs_asm to return a pointer to the CBFS file header rather than the data. Rename walkcbfs() to walkcbfs_head(), and reimplement a new walkcbfs() based on walkcbfs_head(). Thus current usage of walkcbfs() remains unaffected. The code has been verified to run successfully under qemu. Subsequent patches will change usage of walkcbfs() to walkcbfs_head where knowing the length of the data is needed. Change-Id: I21cbf19e130e1480e2749754e5d5130d36036f8e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4504 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-07snprintf: lockless operationVladimir Serbinenko
Instead of having global variables put them on the stack. Change-Id: I462e3b245612ff2dfb077da1cbcc5ac88f8b8e48 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4288 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07vtxprintf: Introduce vtxdprintf for the ease of closuresVladimir Serbinenko
It was suggested to eliminate the lock for sprintf. One way to do it is to make the fake tx_byte into a closure. This patch allows it. It's a bit tricky since we need to preserve compatibility with romcc. Change-Id: I877ef0cef54dcbb0589fe858c485f76f3dd27ece Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4287 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-07haswell: VR controller configurationAaron Durbin
Configure the VR controller. This enables the PSIx levels as well as C-state ramping. PSIx thresholds are: - PSI3: 1A. - PSI2: 5A. - PSI1: 15A. Before: 0x601 0x0000000000000100 0x603 0x0036000000262626 0x636 0x000000000000006f After: 0x601 0x4010140f00000100 0x603 0x0036000000262626 0x636 0x000000000000006f Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60931 Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/4338 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07Add kernel-derived support functions for DDI.Ronald G. Minnich
Newer mainboards that use haswell -- and, presumably, chipsets to come -- need some support functions. Add them in the drivers/intel/gma directory. Currently, this is one file: intel_ddi.c, but more may come. Compilation of this file is controlled by INTEL_DDI, defined in the Kconfig as default n and used in the Makefile.inc Change-Id: I501ee291c0d4589925ed3e478f67106337fcad31 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60612 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4337 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07haswell: Add ACPI support for Controllable TDPDuncan Laurie
Add ACPI Methods to enable and disable power limiting with PL1. This can be used in ACPI Thermal Zone or in EC ACPI _QXX events. This commit adds new unused methods and is fully tested with the subsequent commit that makes use of these methods. Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60546 Reviewed-on: http://review.coreboot.org/4334 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
1) fix enable of power aware interrupt routing 2) set BIOS_RESET_CPL to 3 instead of 1 3) mirror PKG power limit values from MSR to MMIO on all SKUs 4) mirror DDR power limit values from MMIO to MSR 5) remove DMI settings that were from snb/ivb as they do not apply to haswell 1) verify power aware interrupt routing is working by looking in /proc/interrupts to see interrupts routed to both cores instead of always to core0 BEFORE: 58: 4943 0 PCI-MSI-edge ahci AFTER: 58: 4766 334 PCI-MSI-edge ahci 2) read back BIOS_RESET_CPL to verify it is == 3 localhost ~ # iotools mmio_read32 0xfed15da8 0x00000003 3) read PKG power limit from MMIO and verify it is the same as the MSR value localhost ~ # rdmsr 0 0x610 0x0000809600dc8078 localhost ~ # iotools mmio_read32 0xfed159a0 0x00dc8078 localhost ~ # iotools mmio_read32 0xfed159a4 0x00008096 4) read DDR power limit from MSR and verify it is the same as the MMIO value (note this is zero based on current MRC input) localhost ~ # rdmsr 0 0x618 0x0000000000000000 localhost ~ # iotools mmio_read32 0xfed158e0 0x00000000 localhost ~ # iotools mmio_read32 0xfed158e4 0x00000000 Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60544 Reviewed-on: http://review.coreboot.org/4333 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07peppy: Enable power limiting for thermal controlDuncan Laurie
Limit power to 12W at 73C and remove limit at 68C. To have the CPU consume maximum power it is necessary to stress both the CPU and the GPU. Bastion (chrome.supergiantgames.com) and/or webglsamples.googlecode.com can be useful for this. Testing this properly requires a script to report the running average power readings. The watch_power.sh script is attached to this issue in the partner tracker. 1) Run watch_power.sh continuously: localhost ~ # watch -n 0 bash -e /tmp/watch_power.sh 2) Start Bastion (or other stress apps). The power draw should be close to 15W if under enough load. 3) Watch until temperature climbs above 73C and is caught by the thermal zone 10 second poll, this can be sped up by blocking or removing the fan. 4) The ACPI thermal zone states should change to reflect that active[2] is now enabled and power consumption should drop to 12W. 5) Stop the stress apps and wait until the CPU cools off again, enable the fan again if it was removed. 6) The ACPI thermal zone state should switch back to active[3]. Change-Id: Ie6714a8543d4f06edf8513086fc9c968273bdb23 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60545 Reviewed-on: http://review.coreboot.org/4335 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07elog: handle ROM_SIZE differences from detected flash sizeAaron Durbin
The elog code calculates flash offsets and their equivalent addresses in the memory address space. However, it assumes the detected flash size is entirely mapped into the address space. This can lead to incorrect calculations. Add code to allow ROM_SIZE to be less than detected flash size. The underlying assumption is that the first ROM_SIZE bytes are programmed into the larger device. Change-Id: Id848f136515289b40594b7d3762e26e3e55da62f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60501 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4332 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07src/vendorcode/amd: remove Visual Studio remnants.Idwer Vollering
Delete files that (were overlooked and) are probably needed to build with Visual Studio. Remove doxygen helper files as well. Change-Id: I6b6cece178917ad9da1081eb6b1bb9be33066a77 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4489 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 02:47:25 +0000