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2013-12-29via/epia-m700: Drop RAMINIT_SYSINFOKyösti Mälkki
Option is for AMD K8 only. Change-Id: Ic55288b3cae2c9bf4f347037e7bf5d9bfcf16689 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD K8: Socket implies K8_REV_F_SUPPORTKyösti Mälkki
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1). Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-27via: Write »access« without »m« at endPaul Menzel
The comment was copied around so fix all occurrences using the following command. $ git grep -l accessm | xargs sed -i 's/accessm/access/g' Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD AGESA: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-26vortex86ex: Cleanup earlymtrr.c includeKyösti Mälkki
No MTRRs on this platform. Change-Id: Iaef57c8013ae9d40f3b063aae284b3faeeaa43dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4572 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-23usbdebug: Add option to disable console for romstageKyösti Mälkki
If there is trouble setting up usbdebug, it may be useful to delay usbdebug init to run in ramstage. Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4488 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-22Fix linking microcode with more than one microcode fileAlexandru Gagniuc
When assembling microcode , the rule to link individual object files into one larger file only passed the first dependency to the linker. As a results only microcode from one object file would actually get linked. This is fixed by replacing $^ with $+ inside the make rule. Change-Id: I65c0565f2e03777af23e530c08d1241804ca19b1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-22vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.Andrew Wu
Originally, Vortex86EX PCI S/B internal resource reservation functions can only support one big legacy I/O device space (0-0xfff). Change function signature to support other non-legacy I/O device space in the future. Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3976 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-21lynxpoint: XHCI: Don't put device in D3 in _PS0 MethodDuncan Laurie
The end of the _PS0 method that is supposed to transition the XHCI device to D0 state is instead putting it in D3 state. This triggers a PME_B0 GPE which causes a Notify to the XHCI ACPI Device in the kernel and that increments the wakeup counter and causes aborted suspends. Instead if we just leave the device in D0 where it should be after executing this function then the PME_B0 is not generated and the kernel does not see a wakeup on XHCI. Similarly I changed the _PS3 method to always put the device in D3 at the end of the method, rather than depending on the state to be D3 at the start. Before this change the kernel would see the following sequence when trying to suspend when the XHCI controller is in D3cold: kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8 kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: PM: Wakeup pending, aborting suspend kernel: last active wakeup source: 0000:00:14.0 Now it does not get a notification (due to PME_B0) when going to D0 on the way into suspend. XHCI goes from D3cold to D0 (in order to be able to read mmio) and then back to D3hot before suspend. kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000) kernel: xhci_hcd 0000:00:14.0: PME# enabled kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65236 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4448 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Fix an issue clearing port change status bitsDuncan Laurie
The coreboot and ACPI code that clears USB3 PORTSC change status bits was not properly preserving the state of the PED (port enabled or disabled) status bit, and it could write 0 back to this field which would disable the port. Additionally add back the code that resets disconnected USB3 ports on the way into suspend (as stated in the BWG) but take care to clear the PME status bit so we don't immediately wake. suspend/resume with USB3 devices 1) suspend with no devices, plug in while suspended, then resume and verify that the devices are detected 2) suspend with USB3 devices inserted, then suspend and resume and verify that the devices are detected 3) suspend with USB3 devices inserted, then remove the devices while suspended, resume and ensure they can be detected again when inserted after resume Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65733 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: XHCI: Advertise D3 as lowest wake stateDuncan Laurie
The recommended value in docs is D2, but lynxpoint XHCI does not even support D2 state which causes the kernel to think this device cannot be used as a wake source: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Device does not support D2 kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI Additionally this means the kernel will never put the device into D3 state by itself. There is SMI code that will put the device into D3 before suspend so advertising D3 here should be correct. With this change the kernel will put the controller into D3 on suspend and back to D0 on resume, including executing the ACPI methods for _PS0/_PS3 that contain chipset specific workarounds. In addition add a _PSC method to directly return the D state from the device registers. With ALL USB devices removed the XHCI controller goes into D3 state and the kernel can have a hard time determining the state of the device at boot. A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see what ACPI methods are executed: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50) kernel: ACPI: Preparing to enter system sleep state S3 ... kernel: ACPI: Waking up from system sleep state S3 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> meld with s3d Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472 Reviewed-on: https://gerrit.chromium.org/gerrit/63916 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4409 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Fix issues with XHCI initDuncan Laurie
- Put the device into D0 and not D3 so memory bar is available and the subsequent commands actually do something useful - Remove set of 818Ch[7:0]=FFh (gone in ref code) - Fix reg 0x40/0x44 mixup Verify that expected bits are set: localhost ~ # pci_read32 0 0x14 0 0x10 0xe0500004 localhost ~ # mmio_read32 0xe0508144 0x000003ff localhost ~ # mmio_read32 0xe050816c 0x000f0038 Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63801 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4408 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Route all USB ports to XHCI in finalize stepDuncan Laurie
This commit adds a new Kconfig option for the LynxPoint southbridge that will have coreboot route all of the USB ports to the XHCI controller in the finalize step (i.e. after the bootloader) and disable the EHCI controller(s). Additionally when doing this the XHCI USB3 ports need to be put into an expected state on resume in order to make the kernel state machine happy. Part of this could also be done in depthcharge but there are also some resume-time steps required so it makes sense to keep it all together in coreboot. This can theoretically save ~100mW at runtime. Verify that the EHCI controller is not found in Linux and that booting from USB still works. Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63802 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4407 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Move USB SMI sleep code to separate USB filesDuncan Laurie
Move this to the existing USB source files so they can share some helper functions and keep the main smihandler code cleaner. The XHCI sleep prepare code now implements the actual sleep preparation steps from the ref code instead of the docs. Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63800 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4406 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: disable LCD FETs before doing any graphics initDavid Hendricks
This ensures that the LCD FETs are off before we do graphics init. FIXME: The location of the code is sub-optimal and should probably be done in romstage, but there are __PRE_RAM__ considerations to take into account. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df Reviewed-on: https://gerrit.chromium.org/gerrit/64305 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Assign corect parent PLLsDavid Hendricks
Assign correct parent PLL's for the following clocks: ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz) PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz) MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz) ACLK_266 (DPLL->MPLL) (300 -> 266MHz) ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz) ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz) ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz) MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz) MUX_MPHY_REFCLK (MPLL->OSC) MUX_UNIPRO (MPLL->OSC) MUX_MIPI1 (EPLL->OSC) MUX_DP1_EXT_VID (EPLL->OSC) MUX_FIMD1_OPT (EPLL->OSC) MUX_IPLL(IPLL->OSC) This also corrects the clock dividers for few of the clocks, as the clock parent changes affect the final frequency of the clocks. This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8 Reviewed-on: https://gerrit.chromium.org/gerrit/65620 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: don't assume MPLL for i2c parent clockDavid Hendricks
This reads the clock select field for MUX_ACLK_66_SEL in the CLK_SRC_TOP1 register in order to obtain the source clock rate for I2C peripherals. Before we were always assuming that the source was the MPLL. Unfortunately not all fields in the CLK_SRC_TOPn registers are enumerated the same with regard to clock select. So this is just a one-off for now. This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f Reviewed-on: https://gerrit.chromium.org/gerrit/65611 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Set SPLL to 400MHzDavid Hendricks
Increase SPLL to 400MHz from 300MHz as we set SPLL as the switching parent for ARM and KFC. This value is as per recommendation of the hardware team. This is ported from https://gerrit.chromium.org/gerrit/62618 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223 Reviewed-on: https://gerrit.chromium.org/gerrit/65432 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4464 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: re-factor clock_get_periph_rate()David Hendricks
This re-factors clock_get_periph_rate() to be a simpler and also make a few corrections along the way. To summarize: - clk_bit_info is no longer used. It had numerous errors and was really painful anyway since it was just a bunch of opaque magic numbers that made bugs non-obvious. - Clock source bitfields for peripherals handled in the switch statement are 3 bits, not 4. Some divider values are 3 bits, some are 4. The earlier code always assumed 4 bits for both which included reserved bits in many cases. - UART source clock and divider shift values were wrong. - PWM clock divider was being read from the wrong register. - SPI3 divider value was being read from the wrong register. - There was a really confusing calculation for SDMMC0 and SDMMC2 clock rates, but it was never actually used since the switch statement never handled PERIPH_ID_SDMMC{0,2} and would thus return if they were ever passed into this function. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b Reviewed-on: https://gerrit.chromium.org/gerrit/65284 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: add a peripheral clock select --> PLL decoderDavid Hendricks
This adds a helper function to translate between peripheral clock select fields in clock source registers and PLLs. Some of this was already done to handle a few special cases, this generalizes the earlier work so that follow-up patches can do further clean-up. Unfortunately, the PLLs represented by clock select fields in various modules are not uniformly ordered. So for now we focus on peripheral clock sources only. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff Reviewed-on: https://gerrit.chromium.org/gerrit/65283 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4462 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: add CPLL and DPLL to the known list of PLLsDavid Hendricks
This patch adds CPLL and DPLL to the known list of PLLs. This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af Reviewed-on: https://gerrit.chromium.org/gerrit/65282 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: correct the PMS value for CPLLDavid Hendricks
This patch matches the User Manual Table 7-2 about the PMS value for CPLL. This doesn't change the PLL frequency (before and after both make 666MHz) but this is the suggested PMSK values for obtaining 666. (Suggested as per user manual). This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia33e1971ab88da761000d443792560476514626b Reviewed-on: https://gerrit.chromium.org/gerrit/65281 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Configure the UART pins unconditionallyGabe Black
Configure the pins for the UART unconditionally in the mainboard code (when we know which UART to configure) instead of in the UART driver. This also means the UART will work if later software wants to use it without setting up the pins. Built and booted on pit with the serial turned off and some serial init in the kernel decompression stub fixed. Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65299 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Implement support to boot with USB A-A firmware uploadJulius Werner
This patch implements the basic infrastructure required to use the USB A-A firmware upload feature on Exynos5 processors with Coreboot. It will require a corresponding host-side script that activates the feature and uploads the correct image parts in the correct order to harcoded target addresses, as described in the comments of alternate_cbfs.c. Also fixes a bug in the Google Snow mainboard where it would not correctly initialize the pinmux configuration for the SPI flash bus. During a normal SPI boot the IROM would already do that for you, but when booting from USB you have to do it yourself. Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64875 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7: Allow accessing ACTLR (Auxiliary Control Register)Hung-Te Lin
The ACTLR provides implementation defined configuration and control options for the processor. Change-Id: I74df1ed7887eb3f16a1b8297db998ec2f8b18311 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65107 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: re-factor the SDMMC GPIO config routinesDavid Hendricks
The existing GPIO config routines for SDMMC0-2 are over-generalized and somewhat confusing as a result. It would work nicely if all SDMMC ports were configured in the same fashion, but there are a few exceptions. For example, the inner function runs differently if we're using 8 bits of data instead of 4, so a big chunk is skipped for SDMMC2. SDMMC0 requires SD_0_CDn to be an output rather than alternate function and must have a value set. This patch trades some verbosity for simplicy. Now the SDMMC GPIO configuration a straight-forward sequence of GPIO operations without any exceptions. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: If75075b24c6588c4c1b3be3fb9b1aa95e2fac2d1 Reviewed-on: https://gerrit.chromium.org/gerrit/65248 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4446 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: configure SD_0_CDn as VDDEN for eMMCDavid Hendricks
On Exynos5420 the MMC channel 0 is connected to eMMC Which does not have a card detection pin. Also this pin is connected as VDDEN to PMIC. This is ported from https://gerrit.chromium.org/gerrit/#/c/60732/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I19048d22b7dd00df1716b6b5b332a7eb70fe0836 Reviewed-on: https://gerrit.chromium.org/gerrit/65247 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4445 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7: Add CPU & MP primitive instructionsHung-Te Lin
To configure multi-processors, we need the intrinsic functions to get core ID, put core into idle state, and to wake up cores. Change-Id: I87a62dab6efd6c8bb0c8e46373da7c7eb7b16b35 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65112 Reviewed-on: http://review.coreboot.org/4444 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: init APLL at 1800MHzDavid Hendricks
This initializes the APLL at 1800MHz. Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a Reviewed-on: https://gerrit.chromium.org/gerrit/64745 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4443 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5xxx: use oscillator clock when changing ARM frequencyDavid Hendricks
Switch ARM clock source when changing the APLL frequency to avoid stability issues. This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8 Reviewed-on: https://gerrit.chromium.org/gerrit/64838 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4442 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: set L2ACTLR parameters for A15 coresDavid Hendricks
This patch does the following for the A15 cores: - Disable clean/evict push to external - Enable hazard detect timout - Prevent gating the L2 logic clock This is ported from https://gerrit.chromium.org/gerrit/#/c/60154 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536 Reviewed-on: https://gerrit.chromium.org/gerrit/64862 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4441 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21snow: Set up the i2s0 pins during bootGabe Black
Change-Id: I6729a139091b40d8fd9ba2aa7a8c4e14216d95c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64879 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Add a pinmux function to set up i2s bus 0Gabe Black
This bus is hooked up on snow and, as it's the only bus hooked up on some other boards, having it available in firmware to test is handy. Change-Id: Icb48b9af4a67d382bd6fbce1e4c6a320d811d365 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64877 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4438 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7: add wrappers to read/write L2ACTLRDavid Hendricks
This adds inline wrappers to read the L2 cache auxiliary control register (L2ACTLR). Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f Reviewed-on: https://gerrit.chromium.org/gerrit/64861 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4437 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21ARM: Don't inject nobits since we actually want to load these bitsGabe Black
Change-Id: I128e3ecc3773fe7c28616e93ef60b48c5862f302 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64839 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4436 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21ARM: Remove (NOLOAD) from the .car sectionGabe Black
On ARM, if the .car section is marked as NOLOAD, there's nothing that sets it to zero. Some code in the cbmem console depends on a global variable being zero initially, and if that's not true bad things happen. Change-Id: Ic72a9fb0ee0c5a608190be6f24d0d7de7c34fc1f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64769 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4435 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: minor correction to CPU frequency printDavid Hendricks
This divides the CPU frequency by 1,000,000 instead of 2^20. serial console shows "CPU: S5P5420 @ 800MHz" instead of claiming 762MHz. Change-Id: I70cc5b62f689c5553b57c82be61233fb9f733f6e Reviewed-on: https://gerrit.chromium.org/gerrit/64743 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4434 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7/exynos: Fix and remove memory reset workaroundsHung-Te Lin
The memory corruption problem in Exynos suspend/resume process is caused by two things together: PHY_RESET and MRS command. After stop sending MRS on resume, we can now remove the workaround of skipping PHY_RESET. Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c Reviewed-on: https://gerrit.chromium.org/gerrit/64736 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: graphicsRonald G. Minnich
This includes the new dp code, which is better, and the fimd code, which is changed and improved. We took the chance to remove un-needed files, and also to remove some foolish u-boot habits, but not all of them. That will take time. With these changes we get graphics. Since the only mainboards we have with 16 bit graphics are 5:6:5, adjust edid.c to just use that format. If at some future time we need 4:4:4, which seems unlikely, we'll need to add a function to adjust the lb_framebuffer. Note that you can't just divine this from the EDID, as the graphics pipe format need not match the actual final format used. The EDID reading works. We've been requested to support hard-coded EDIDs and that will come in the next revision. Currently the hard-coded EDID is ignored for testing. Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64240 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby is dead. long live the arm pit.Stefan Reinauer
Remove kirby from our tree. It's dead. BUG=none BRANCH=none TEST=none Change-Id: I0768a9ea40be5d70d845a46f6e28036a133b7aa6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/176030 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4548 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Snow: correctly disable trust zone hardwareRonald G. Minnich
The kernel assumes that trust zone is disabled. Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64722 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4431 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: correctly initialize trust zoneRonald G. Minnich
This ensures that various trust zone things are reset, which is important because the kernel assumes they are. Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64697 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4430 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21ARMv7: Fix location of CBMEM console in romstageStefan Reinauer
The CBMEM console pointer in romstage is actually a zero byte array. This means CBMEM area has to live at the end of the allocations or else CBMEM console will overwrite whatever comes after it. Change-Id: Icc59e982b724a2d396370c3a5abd8898e08baf26 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4428 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: update PMIC write sequence in romstageDavid Hendricks
This update the PMIC write sequence to be correct for newer board revisions. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I2210b0d1945fb19c96a674c8fad1b0ff5a4a381e Reviewed-on: https://gerrit.chromium.org/gerrit/64304 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: update set_cpu_id()David Hendricks
The current function seems to be outdated... Signed-off-by: David Hendricks <dhendrix@chromium.org> built and booted. Now we see "CPU: S5P5420 @ 762MHz" instead of "CPU: S5PC420 @ 762MHz" Change-Id: Ieb103a5fa62bda9a6b2cbd9a82fb4f72c5dd6466 Reviewed-on: https://gerrit.chromium.org/gerrit/64302 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4425 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21snow: TPS69050 -> TPS65090David Hendricks
This corrects a minor typo used for a part number. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8583cbfc3b4a6c3ad06419f5aab3ba7a8f685575 Reviewed-on: https://gerrit.chromium.org/gerrit/64301 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4424 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby: pit: Fix up wakeup_need_resetGabe Black
In a previous commit the contents of wakeup_need_reset were removed because the GPIO it referred to wasn't connected to anything on pit. I didn't realize at that time that that could have been because we hadn't tried getting suspend/resume working on pit and hadn't updated that file. On snow, the GPIO is the recovery mode pin. This change updates pit to have the right GPIO, kirby to read that GPIO, and makes the comments for both pit and kirby more explicit and spells out the fact that this is the recovery mode GPIO. Having a check here at all may still be a holdover from snow that isn't applicable to pit or kirby, but since there is a parallel as far as the recovery mode GPIO we might as well make them match while waiting for more information. Change-Id: Ic1f3f605a0fddf89e8f5668c7a8df30bdfb91d94 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64164 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4421 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Get rid of the mostly unnecessary exynos5420.hGabe Black
Like on kirby, this header had a single constant in it that was actually used. This change moves that constant inline and gets rid of the header file. Change-Id: Ibe380396f72fddb121fb6ceb3cee24f1b9a85738 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64163 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4420 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Add mct_start to the timer init blob in timer_monotonic_getGabe Black
A previous change removed init_timer from timer_monotonic_get because its old implementation set up the PWM based timer which was going away. It would still be a good idea to initialize the timer at that point, just not the pwm. Change-Id: I4816710ec2c9d5ca53b704c6b9397bcfac183fdc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64160 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4419 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby: Clean some cruft from mainboard.cGabe Black
1. Kirby doesn't have a backlight enable GPIO on the AP since that's handled entirely by the DP-to-LVDS bridge. 2. There is no tps65090 on the other side of the EC who's settings need to be adjusted. If we need to turn on the LCD or backlight power manually, it will have to be done in a different way. 3. The PMIC doesn't provide a 32KHz output for the audio codec. Change-Id: Iadc5f3aec4818805edf3f2517da9e6fee87085dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63883 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4413 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby: Neutralize wakeup.c and delete the mostly unused exynos5420.hGabe Black
The function in wakeup.c isn't applicable on kirby. The only constant in exynos5420.h that was used was the speed of the 4th i2c bus. Instead of having a whole header file for that one constant used in one place, the constant is just moved inline along with the comment it had in the header. Change-Id: I5ad50c5eeaecbbf7865d76afb31a12d36c3371ee Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63882 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4412 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add a kirby board which is mostly a copy of pitGabe Black
Change-Id: Ic78c65486816015f7574a13affc6e54acbbea73e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63875 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4411 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21arm: Remove __image_copy_end from the ARM linker scriptGabe Black
That symbol isn't used by anything and doesn't appear in other linker scripts. Change-Id: Iab54ecb3be2e262d7674ef8ee7ed13ea2e5b56f3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63776 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5420: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63657 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4391 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5250: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59326 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4390 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7: Prepare tables code for dynamic CBMEMPatrick Georgi
The CBMEM API is different for dynamic CBMEM, so hide the functions that get in the way (but our compiler complains about) Change-Id: I7634a202059548e56c74fe3fe6eff57bc60f1a1b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4546 Tested-by: build bot (Jenkins)
2013-12-21google/pit: disable SYSMMU for graphicsRonald G. Minnich
It's not needed and it's a potential problem source. Change-Id: Ic4cafe74e7fc3a9031d852895ad7fd5e5cd64d11 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62279 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4410 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21max77802: update headerDavid Hendricks
This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6 Reviewed-on: https://gerrit.chromium.org/gerrit/64303 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4426 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Refactor code containing aux callsFurquan Shaikh
Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4429 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flagsFurquan Shaikh
Depending upon the values decoded from edid, the function decides the appropriate bits to be set in flags parameter (Important for fastboot to work correctly in kernel) Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856 Reviewed-on: https://gerrit.chromium.org/gerrit/64265 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4423 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add cpu transcoder attribute to intel dpFurquan Shaikh
Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4422 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Calculate transcoder flags based on pipe configFurquan Shaikh
Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Enable CAR migration on Exynos 5250 and 5420Stefan Reinauer
Despite calling romstage memory CAR in this case, the variables actually do live in SRAM on the Exynos CPUs. However, in order to share as much generic code as possible, we're using the same infrastructure here. Change-Id: I85173c37099a25f3e55980e88120401826cdf29c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62188 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4394 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21peppy: Set optimal DTLE register valuesShawn Nematbakhsh
Empirical testing shows that 0x5 is the optimal setting for DTLE DATA / EDGE on Peppy. Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65717 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Add configuration option for SATA gen3 DTLE registersShawn Nematbakhsh
Allow DTLE DATA / EDGE registers to be configured in board-specific devicetree. Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65716 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: add option to change DqPinsInterleavedStefan Reinauer
Some mainboards will need to have this set. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0 Reviewed-on: https://gerrit.chromium.org/gerrit/65722 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21wtm2: disable SDcard USB portDuncan Laurie
This is causing hangs in depthcharge (again?) so for now turn that port off so the resulting coreboot images are at least useful. Change-Id: I32c7774a95b0020b97105e0fa42c21ccb617c718 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65615 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Misc updates from 1.6.1 ref codeDuncan Laurie
These programming sequences were changed in the latest code. Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: Fix EC wake events in S5Duncan Laurie
The SMI handler code was setting S3 wake events when going into S5 and enabling a key press to wake the system. Change-Id: I6413ef1341e0149187df9f4f7e0c314d4c9e9c6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65323 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add a specific post code for S3 resume failuresDuncan Laurie
If the firwmare is flashed and the MRC cache is blown away then it is not possible to resume. Right now this can be inferred from the event log but it can be made very clear by adding a unique post code for this event. 1) boot falco 2) flash firmware 3) suspend and then resume 4) check for post code 0xef in log 0 | 2013-08-08 16:27:47 | Log area cleared | 4096 1 | 2013-08-08 16:27:47 | ACPI Enter | S3 2 | 2013-08-08 16:27:55 | System boot | 48 3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure 4 | 2013-08-08 16:27:55 | System Reset 5 | 2013-08-08 16:27:55 | ACPI Wake | S5 Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add Kconfig options to override Subsystem Vendor and Device IDDuncan Laurie
These can typically be set in the devicetree but we need a way to override those values with a Kconfig setting so as not to expose the Vendor ID before the product has launched. Change-Id: Ib382e6d9359d24b128c693a657ffde52604efad3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65310 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4455 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Force enable ASPM on PCIe Root Port 1Duncan Laurie
Boot on falco and look in /sys/firmware/log for the string "PCIe Root Port 1 ASPM is enabled" Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Add devicetree config option to force enable ASPMDuncan Laurie
The PCIe root port has ASPM settings/workarounds that are only applied based on the value of an undocumented bit in PCI config register 0x32C. If that bit is not set for some reason then the settings are not applied. This devicetree config option will force the ASPM settings for each port based on the bit map. Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Disable some verbose messagesDuncan Laurie
The default ME output is quite verbose and not all that useful unless you are actively debugging the ME and then you can enable the CONFIG_DEBUG_INTEL_ME option. This commit silences the firmware capabilities and the MBP output. Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4452 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Disable unused clocksDuncan Laurie
CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used and can be disabled. I couldn't test this directly without a scope so instead I used a modified commit that also disabled PCIe Port 0 and saw that that correctly disabled the WLAN port. Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4451 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Support ICC clock enables messageDuncan Laurie
This message allows unused clocks to be disabled based on a devicetree setting in each mainboard. Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65250 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4450 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Allow for more than MKHI MEI messagesDuncan Laurie
The original ME code was assuming that the only type of messages it would send were MKHI type and so it had some embedded checks for that header and that type of message. In order to support ICC messages this needs to change to handle different header types, so now the header will be sent first and then the data will follow, rather than the two both being sent in the same low-level function. This change has no real affect on the system, subsequent commit will add new ICC messages. Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4449 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Enable EC controlled throttlingDuncan Laurie
When the EC requests the host to throttle (for charging or thermal related reasons) the package power consumption will be limited. Right now this is set at 12W but that is somewhat arbitrary and may need tuning. 1) define the THRT method in \_TZ scope for EC to call 2) enable SCI events for throttle start and stop 3) define the power limit at 12W and set it in NVS 1) Enable CONFIG_ACPI_DEBUG=y in the kernel 2) Enable the Debug object event in acpi module acpi.debug_layer=0x7f acpi.debug_level=0x2f 3) Using EC console generate host event for throttle start > hostevent set 0x20000 4) Check dmesg for throttle start events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988) [ACPI Debug] String [0x12] "EC: THROTTLE START" [ACPI Debug] String [0x10] "Enable PL1 Limit" 5) Using EC console generate host event for throttle stop > hostevent set 0x40000 6) Check dmesg for throttle stop events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0) [ACPI Debug] String [0x11] "EC: THROTTLE STOP" [ACPI Debug] String [0x11] "Disable PL1 Limit" Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63989 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4416 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21chromeec: Add event methods for EC requested throttleDuncan Laurie
Two new events possible from the EC for starting and stopping throttle. These are handled in a per-board method that is defined under the thermal zone. This is not quite where I wanted it but the scoping rules in ACPI don't let me have a defined external object in the same scope. Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63988 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4415 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Drive GPIO59/LTE_DISABLE_L low on S3/S5Duncan Laurie
Try to prevent WWAN from causing spurious wakes. Change-Id: Ifcc44063de0eb1634cab9dd244737071568e3455 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63987 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4414 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Add missing elements to the edid data structureGabe Black
When the edid data structure changed a while ago, it caused hangs on snow which were fixed by adding those missing members. Unfortunately we didn't realize that pit needed the same fix. Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63646 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4389 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21tpm: provide explicit tpm register accessAaron Durbin
An issue was observed using a specific vendor's TPM in that it chokes on access to registers that are not explicitly defined in the PC client specification. The previous driver used generic access functions for reading and writing registers. However, issues come to play when reading from the status register. It read it as a 32-bit value, but that read address 0x1b which is not defined in the spec. Instead of using generic access functions for the tpm registers provide explicit ones. To that end provide more high level wrapper functions to perform the semantic access required. Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4388 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Bump the EC SPI bus speed up to 5 MHzGabe Black
That speed is used with U-Boot instead of the more conservative 500 KHz. Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63193 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4386 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Fix some clock settingsGabe Black
Some registers and bit fields were wrong, but the difference is mostly academic since the code that uses them are never called. Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63189 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4385 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Fix the clock divisor maskGabe Black
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide. Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63188 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21arm: Don't use const pointers with the write functionsGabe Black
This functions are by definition changing the data pointed to by their arguments, so they shouldn't by const. Change-Id: Id29b3f76526aba463f8bb744f53101327f9c7bde Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63777 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4400 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Get rid of the PWM code like on the 5250Gabe Black
The timer code was supposed to be using the mct, and also using the monotonic timer infrastructure instead of the get_timer function. This change had been made for the 5250 but not yet for the 5420. Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64159 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4418 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Get rid of the PWM timer code we shouldn't be using anymoreGabe Black
This code was left over from U-Boot and was superceded by the MCT. Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63778 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4401 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Apply pwm const fix to the 5420 as wellGabe Black
When the const was removed from write function arguments, a related bug in the 5250 code was fixed so that it would still compile. Unfortunately, that same change needed to be made to the 5420. Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64154 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4417 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Fix consts in the pwm codeGabe Black
The code generally intended to make the pointer const instead of the thing it pointed at, but it had const backwards. Sometimes both the pointer and the data could be const, but sometimes there were writes where only the pointer should be. Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63775 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4397 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21falco: add rtd2132 settings to device treeAaron Durbin
Now that the rtd2132 device has the full settings the panel timings need to be implemented. Sadly, the Tx timings in the rtd2132 aren't 1:1 with the panel's Tx timings. Below is the table equivalent: RTD2132 | Falco Panel --------+------------ T1 | T2 --------+------------ T2 | T8+T10+T12 --------+------------ T3 | T14 --------+------------ T4 | T15 --------+------------ T5 | T9+T11+T13 --------+------------ T6 | T3 --------+------------ T7 | T4 --------+------------ Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65858 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21rtd2132: implement full configurationAaron Durbin
It has been disseminated that the RTD2132 chip needs to be fully programmed for settings to take affect. Most of the settings are note documented very well and present themselves as magic values. Also, the wait time for starting the sequence needs to be bumped from 2ms to 60ms. Lastly, expose all the known settings through devicetree. Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65857 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Remove PS/2 keyboard initialization on resume from S3Martin Roth
When we go through the resume path, there shouldn't ever be a need to initialize the PS/2 keyboard. The OS is going to reinitialize it anyway, and it just slows the resume. Verified Code flow in normal boot/S3 resume with print statements. Verified Keyboard was correctly disabled and flushed by booting to recovery mode screen while pressing keys on the integrated keyboard. Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63648 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4396 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add simple hexdump functionStefan Reinauer
- prints hex and ascii - detects duplicate all zero lines Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62655 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4392 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: set PWM to external on ParadeRonald G. Minnich
The PWM is controlled externally from the APU. Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61513 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4363 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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