| Age | Commit message (Collapse) | Author |
|---|
|
Change-Id: I1268a8f886ff395ff822b14a5427a5031260c541
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83389
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It's a slow CPU.
Change-Id: I0bf75f410c1d9134f05a2d11b8d011499a7cf794
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82772
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Icba7586145fbfd859d738ecd7a407739a7024ebb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82771
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This brings the old raminit implementation for CX700 back. It was
removed in commit e99f0390b9b8 (Remove VIA CX700 northbridge sup-
port). The code is mostly unchanged, three minor issues are fixed:
* A shift (>>= 2) was missing when reading tRRD from SPD byte 28.
The fixed value matches what the vendor BIOS of a VIA EPIA-EX
board programs. The code also suggests that we are looking for
a small value (<= 19 for DDR2-533).
* We allow the board port to specify which clock outputs should
be enabled now. This is necessary for the VIA EPIA-EX, which
needs the ALL_MCLKO setting (instead of the previously hard-
coded MCLKO2.
* When programming the DQS output delays, we considered the 1~2
rank values only for single-rank configurations. Changing the
`< 2` to `<= 2` brings us closer to the vendor values on the
VIA EPIA-EX.
Otherwise a lot of cosmetics changed. Partly because the original
code was to be #included into another C file, but also to satisfy
checkpatch. Also, all the #if'd code was removed (32-bit width
option, ECC, etc.).
Change-Id: Ibc36b4f314cdf47f18c8be0fcb98218c50938e94
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This northbridge provides a lot of knobs for fine-grained tuning of the
FSB drivers. The programming manual calls this "Host AGTL+ I/O Driving
Control". We program the known good values for use with a VIA C7 CPU,
and warn about use with different CPUs.
The numbers were pulled out of raminit of the original CX700 port.
Originally, there was a write to 0x83 as well, to set bit 1 which
triggers a soft reset of the CPU. It was amidst a table, so it
seems unclear if it was put there intentionally.
Change-Id: I24ba6cfaab2ca3069952a6c399a065caea7b49f2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Disable a timer (GP3) that is always running by default. And enable
SMBus, which is useful this early as a console. The SMBus controller
is mostly compatible to the Intel one.
Change-Id: I77f179433b280d67860fc495605b5764ed081a6c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
- Drop duplicated fields
- Drop fields filled with constant values
- Drop SRAT prefix for sysmemmap entries
- Print all zeros when concatenating two hex numbers
Change-Id: I379aeb6fcd2e28665c7d592b0639db3c1b4caa9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85189
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The power limit parameters were defined for 378775630#comment5
by the power team.
BUG=b:378775630
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I069869fa01dc157cf2544e72468f43ce1bb64035
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85209
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
|
|
Add RAM ID for DDR MICRON MT62F1G32D2DS-023 WT:B
BUG=b:378821948
BRANCH=None
TEST=boot to kernel success
Change-Id: I22e00cffaf6007c64d0c9ffa5f5dde528e3d8952
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Remove "include <bootstate.h>" when it is not used.
Change-Id: Ic27acf9f8dfbbccb8f48a139032b1463e7185030
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85216
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Add initial board commit based on HP 8200 SFF and HP Z220 SFF.
* Add documentation.
Tested on HP 8300 SFF.
Change-Id: Ib5322acc0210f000b53954e2925549358f86d5c8
Signed-off-by: Michał Zieliński <michal.zielinski@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67666
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
|
|
Only advertise C-state C1 and C6.
TEST: On ocp/tiogapass Linux no longer complains about advertised
but unsupported C-states.
Change-Id: I184c337478f97e2d36f6e89b764dbe1da1b91697
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85190
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix ISCLK register definitions
Reference: 813032 - Panther Lake H I/O Registers
BUG=b:357011633
TEST=check camera functionality on fatcat
Change-Id: Ie9f1f639970344eb359dee37914ee26a02dcfb4b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85058
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
This patch updates Kconfig that selects ME specification version for
Pantherlake SoC from version 18 to version 21.
BUG=b:362647201
TEST=Able to build fatcat with SOC_INTEL_COMMON_ME_SPEC_21 selected.
Change-Id: Ibfebd7c093240aa7f1d6337f3e4dd6e5d34bed1d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85187
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch introduces Kconfig support for Intel's Management Engine
(ME), version 21. When 'SOC_INTEL_COMMON_BLOCK_ME_SPEC_21' is selected
it sets the ME_SPEC configuration to 18 because ME version 21 is
compatible with version 18 in terms of Host Firmware status registers.
BUG=b:362647201
TEST=Able to build fatcat after selecting SOC_INTEL_COMMON_ME_SPEC_21
Change-Id: I90c946751ac530dac1af4ff9c3c921b5faf82448
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add const qualifier for input of dev_is_active_bridge so that
dev_is_active_bridge could be used for both struct device * input
and const struct device * input.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ia4231534c87cd13d4e6e4d606733f9eb11221ac1
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
This patch enables coreboot to perform CPU feature programming for both
the Boot Strap Processor (BSP) and Application Processors (APs) on
Intel Panther Lake platforms.
This change eliminates the need for the following FSP modules:
- CpuMpPpi
- CpuFeature
By handling CPU feature programming within coreboot, we reduce reliance
on external FSP binaries and improve code maintainability.
BUG=b:376092389, b/364822529
TEST=Built and booted google/fatcat successfully. Verified CPU features
are correctly programmed.
Change-Id: I73321485327f6a02ec8338fcfa1faf1e71008ba6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
Create the felino variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:379797598
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FELINO
2. Run part_id_gen tool without any errors
Change-Id: Iff7989c19e775d65d5fb04aa4489854150390a35
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85185
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Walk the devicetree to collect all PCI IOAPICs. When found read
the IOAPIC base address from hardware.
TEST: On ocp/tiogapass all IOAPICs are found and advertised.
Change-Id: I2835c202e56849655795b96bc83862cb18e83fc0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84851
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
CPX uses the same PCU IDs as SKX.
Change-Id: I1bc96232e120b9cd9cb4f5b7b5df7d7db62fcbc4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84852
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On 1st and 2nd gen Xeon-SP the VTD PCI device is not at DEVFN 0.0.
Fix the DEVFN address and thus fix an assertion in vtd_probe_bar_size().
Change-Id: Ie879e95436af92fca1fee49135938ca2b005d579
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Drop DMAR_X2APIC_OPT_OUT since coreboot is able to enable X2APIC.
TEST: Works fine on OCP/tiogapass, thus drop the opt out.
Change-Id: Ia0443a39a9bf392976cfd1a7ccf6a335d5f0bd70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Set _PXM in ACPI to indicate which socket the PCI domain belongs to.
TEST: Booted on 2S ocp/tiogapass and checked dmesg that PCI domains are
advertised in the correct Proximity Domain.
Change-Id: I39cec0307b0dce0a4da5df5be5095b8d90758997
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Enable GBE and 10GBE region since it's used on vendor firmware.
TEST: Able to include gbe.bin and 10gbe.bin blobs into ROM.
Change-Id: Ia868d6b42e5e557d2abd60be4b2f318a1313b039
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85171
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently coreboot hardcodes the same IOAPIC IDs as used on UEFI native,
however FSP does not program the IOAPIC IDs, except for PCH IOAPIC.
Drop existing code that hardcodes PCI addresses and IOAPIC IDs and
detect the IOAPIC inside the domain automatically, read the IOAPIC
base address and let existing code figure out the IOAPIC ID by reading
it back from HW.
Change-Id: I2543a46dcc4a98ec8629530ca87882a7106c9ed1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84850
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Drop soc_get_stack_for_port() and move a comment.
Change-Id: I9d7615b633b344783150b3e1f3d98634630ed354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84844
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
General Purpose Memory Range registers are only used if extended BIOS
region is enabled now, this patch wraps the related code with Kconfig
item `CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW`.
Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one
of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning
PIRQ for a given device and INT pin.
Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
The current design has the emit_wifi_sar_acpi_structures() function
load and unload the SAR binary. Since DSM and Bluetooth SAR data
structures are used outside this function, they are being copied into
data structure located in the calling function stack. This overhead is
unnecessary as loading and unloading the SAR binary could be done by
the calling function.
In addition, we are about to add several Bluetooth related data
structures which, under the current design, would require to add even
more data structure copy operations.
BUG=b:346600091
TEST=Wifi/Bluetooth SAR ACPI tables are identical before and after
this commit
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e207
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This change removes the GPIO configuration for Type C DP HPD, as the
Type C port does not require HPD setup.
BUG=b:366156678
TEST=Build and boot google/orisa. Test Type C port for external usb and
DisplayPort functionality.
Change-Id: I59ec5c19dbbd053bda25f4260321220524d785b3
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This change removes the GPIO configuration for Type C DP HPD, as the
Type C port does not require HPD setup.
BUG=b:366156678
TEST=Build and boot google/trulo. Test Type C port for external usb and
DisplayPort functionality.
Change-Id: Iad602c9a15c65d37a37d06d486843f45e341b6bc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch calls `xhci_host_reset()` function to perform XHCI
controller reset. This is proactively pulled in to avoid any potential
timeouts when PMC sends an IPC command to disconnect the active USB
ports.
BUG=b:364158487
TEST=Build Brox BIOS image and boot to OS. Perform warm reset, cold
reset and suspend/resume cycle.
Change-Id: I33fd3aa13e81c7b1ae1ebf6674cc8ac1437ecc03
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
|
|
Remove <assert.h> when it is not used.
Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
This to fix Wimplicit-function-declaration error:
src/soc/qualcomm/sc7280/socinfo.c:67:2: error: call to undeclared function 'die'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
67 | die("could not match jtagid\n");
| ^
src/soc/qualcomm/sc7280/socinfo.c:81:2: error: call to undeclared function 'die'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
81 | die("could not match jtagid\n");
| ^
Change-Id: If930e39d0c7231975c1a11179fa7dbd9fcc0d1d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85166
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Properly scan all logical stack when creating PCI domains.
Fixes PCI bus ranges being used on other stacks, since they look
unused, as not all stacks are checked.
Change-Id: I13c8b389a585dbccec182d3c98021f1d9d648b2c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Do not enable SMIs on GPIOs since there's no SMI handler.
Without an SMI handler this will just slow down the platform once
the SMI asserts since it's never cleared. Once the protocol between
BMC and x86 has been implemented in an SMI handler, this can be reverted.
TEST: Booted on OCP/tiogapass without massive slowdown when SMIs are enabled.
Change-Id: If16c2c427f9b160f78a768a01a60128a6ed2c53f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
Add RAM ID for DDR Hynix H58G56BK8BX068
BUG=b:378821948
BRANCH=None
TEST=boot to kernel success
Change-Id: I4c4ad191a5e9703ee0f3bed150c816bfb098daf5
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85117
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
BUG=b:366291025
TEST=emerge-rex coreboot pass
Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Add support for Realtek audio codec ALC5682I-VS and Realtek audio amp
ALC1019.
BUG=b:366291025
TEST=emerge-rex coreboot pass
Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85100
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update initial overridetree settings, it's basically copied from karis.
This patch includes:
1. USB port related settings
2. Display Port Configuration
3. DPTF settings
4. PCIE settings for NVME
5. Settings of MIPI camera HI556
6. Settings of ELAN9004 touchscreen
7. Settings of ELAN and PIXA touchpad
8. PCIE settings for WLAN card
9. Settings of NUVOTON FPMCU
BUG=b:368501705
TEST=emerge-rex coreboot pass
Change-Id: I468ca388f495b2e527841145f8162b21074058cc
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Initial GPIO config for kanix, it's copied from karis.
Will update more GPIO config in future.
BUG=b:368501705
TEST=emerge-rex coreboot pass
Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85042
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add kanix supported memory parts in mem_parts_used.txt, generate
SPD id.
1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT
5. MICRON MT62F512M32D2DR-031 WT:B
BUG=b:378390643
TEST=Use part_id_gen to generate related settings
Change-Id: I6ce92bac8d8e7ed64135c26387f52b7cc488c391
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85040
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add override devicetree based on schematic_20241104.
BUG=b:376245884
TEST=emerge-fatcat coreboot
Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
1. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka.
2. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka.
3. Set TPM I2C bus to 0x01 for francka.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: I5890a1f02ef88c591973c71a2adb2bba889733e7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85115
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure GPIOs according to schematics_20241112.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
GPE route for GPE0_DW0 was not being programmed (i.e. 0) which made it
route to GPP_B since a value of 0 means GPP_B. GPE route for GPE0_DW1
is also being programmed to GPP_B which makes the overall configuration
invalid.
The fix is to program the GPE0_DW0 route to a GPIO group which is not
already being used for GPE0_DW1 & GPE0_DW2 i.e. GPP_A.
Additionally, the common GPE route configuration is moved to baseboard.
BUG=b:378455259
TEST=Verify wake from S0ix when charger is connected
Change-Id: I674cf7db160b6bc1ec3d620f9c99ea91041c48bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85157
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This commit adds an assertion to ensure that the values of
pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the
soc_intel_<soc>_config structure are unique.
This check helps to catch potential configuration errors early on,
preventing unexpected behavior during system initialization.
TEST=Built and booted normally. No assertion failure observed.
Able to catch the hidden issue due to overlapping Tier 1 GPE
configuration.
[DEBUG] CPU: Intel(R) Core(TM) 3 N355
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a
[DEBUG] CPU: AES supported, TXT supported, VT supported
...
...
[DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
[DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c',
line 163
Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Enable upd to reduce size of the memory test.
TEST=Able to build and boot google/fatcat.
w/o this patch:
951:returning from FspMemoryInit 3,452,595 (365,930)
w/ this patch:
951:returning from FspMemoryInit 3,442,823 (353,928)
Change-Id: I67f10e234019e260923a28a2d71b83786dcb39ee
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The lower_basic_mem_test_size SoC setting (LowerBasicMemTestSize UPD)
request FSP-M to reduce the size of memory tested after memory
training. This option reduces the boot time. This is considered a safe
option to enable on a well validated board.
BUG=b:357011633
TEST=LowerBasicMemTestSize UPD is set when lower_basic_mem_test_size
is set
Change-Id: I465e9c138ac8f2079bfd506add4667201a8fa533
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85130
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Include missing <types.h>.
Change-Id: I04d18e601e010b64c46f2eb52874d3eb5664b0e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Add console.c to SMM stage as well. Fixes the build failure:
"undefined reference to `get_uart_baudrate'" when CONFIG_DEBUG_SMI
is set.
Change-Id: I2587287b0074a56c49b7434553c69cae97aaa1b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Limit the ACPI OpRegion to cover only MBOX3. This seems to fix
BSOD errors seen on Windows 10/11 as reported at [1].
1: https://ticket.coreboot.org/issues/327
Change-Id: Ia2affa799e5cd84c0a03330e0f78919755f0e8ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81295
Reviewed-by: Joel Linn <jl_coreboot@conductive.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Remove unused include <console/console.h>.
Change-Id: I2a7cafd7b755a5c3e2bbfa9fc814bf2686c1ccf1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85163
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a helper function to identify PCI IOAPICs.
Will be used in the following commits.
Change-Id: Ibe50934260b025575440fd52eace73fe2327a193
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Update microcode on BSP before MPinit and on all APs if necessary.
When the APs already have a MCU loaded, MPinit will skip the update.
This aligns the code with other platforms that attempt to update the
microcode in MPinit even when FIT already has loaded a MCU.
Drop the UPD PcdCpuMicrocodePatchBase to prevent FSP-S from updating
MCU before MPinit runs.
Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.
Change-Id: I7df6f82055a879a738fd29092e750084557bbd5c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84848
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use Kconfig symbol CPU_BCLK_MHZ as done on CPX.
Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.
Change-Id: I8a0a51d4280e4370e0e8695f8b9d8f2ed943d9e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Since SKX and CPX are using the PCH, copy the code from CPX and
lock the PMC in the same place.
Reduced code differences between SKX and CPX and will allow to
merge the codebase into one.
Change-Id: I9495456fc2650b25ba164b336dc10ea0b88989aa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84846
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use get_platform_thread_count() instead of duplicated
get_thread_count(), that is also less precise.
Change-Id: I70c095c284aab6898b8351e82243f534963f333b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84845
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Lock all PCU registers on all sockets. The same code can be found
on CPX, which is basically the same CPU. Once the differences between
CPX and SKX are minimal, the platforms can be merged into one codebase.
Change-Id: I73eaa0905e8a418fc9dfe515c42cd257c041cf61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84843
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Fn key on telith emits a scancode of 94 (0x5e).
BUG=b:372506691
TEST=Flash telith, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85045
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The DPTF parameters were defined by the thermal team.
Based on thermal table in 377955793#comment2
BUG=b:377955793
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate different hardware configurations.
Specifically, GPP_E07 is not connected (NC) on google/fatcat boards
with the Microchip EC AIC. However, it is required for google/fatcat
boards with Nuvoton/ITE AICs.
BUG=b:378603337
Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85106
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The current WWAN(LTE) does not require any sar setting from RF team's
suggestion, and sar sensor will be removed from DVT schematic.
To reserve the extendibility, add the fw_config DB_1A_LTE_SAR:
field DB_USB 11 12
option DB_1A 0 (None LTE)
option DB_1A_LTE 1 (LTE without sar sensor)
option DB_1A_LTE_SAR 2 (LTE with sar sensor)
end
Base on the fw_config to enable/disable related functions:
0)Disable WWAN and Sar if DB_USB = DB_1A
1)Enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE
2)Enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR
BUG=b:375341992
TEST=Build and verify on jubilant by DB_USB= 0,1,and 2 of fw_config
Check sar sensor and WWAN module from commands:
ls -l /sys/bus/i2c/devices
i2cdetect -y -r
lsusb
Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85107
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be
reused for multiple domains.
Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This will ensure that the user is informed about an ongoing CSE FW Sync.
BUG=b:378458829
TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed
during CSE FW Sync.
Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
PRMRR (Protected Region Memory Range Region) are not accessible as
normal DRAM regions and needs to be explicitly reserved in memory
map.
Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Definitions of __fls/__ffs from lib.h and fms/fls from
cpu/x86/mtrr.h are duplicated. Use definition from lib.h which is
more generic.
Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create a new config option to indicate that a board has Google Strauss
keyboard. The scan code for Fn key will be set to 94 if the new config
is selected.
Previously each board was setting the integer config option for Fn key
scan code which was not scalable. The new option is a bool and can be
easily selected by different boards.
BUG=none
TEST=Verify coreboot.config before and after this change.
Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We use ALC256 as HDA codec on francka, add the verb table.
BUG=b:370668037
TEST=emerge-fatcat coreboot
Change-Id: I579c9fd23c763d6791944732889021ffa03da448
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85036
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds support for the ALC721 codec in the device tree
and enables it based on the fw_config.
BUG=b:368495490
TEST=Boot on google fatcat board
Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
When we use PCIE wifi7, CNVI BT and BT offload should be turned off.
BUG=b:378053901
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch updates the eSOL rendering logic to use the
SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of
SOC_INTEL_CSE_LITE_SKU.
The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to
determine whether to render eSOL during ramstage.
The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically
indicates whether CSE synchronization is performed during ramstage,
making it a more appropriate choice for this purpose.
This change ensures that eSOL is rendered correctly during ramstage on
platforms that require CSE synchronization.
TEST=Able to render eSOL during ramstage for google/trulo.
Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out on the serial
console for bus hanging analysis.
TEST=build pass, and check log with:
[INFO ] ******************* MT8196 lastbus ******************
[INFO ] --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 ---
[INFO ] 00402504
[INFO ] c34b00d6
[INFO ] 61804050
[INFO ] 00051840
[INFO ] 10401610
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Pass the reset gpio parameter to BL31 to support SoC reset.
BUG=b:334753311
TEST=run reboot command
Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84933
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. Add Google Ti50 TPM support
2. Configure I2C speed to I2C_SPEED_FAST_PLUS
3. Pass GPIO_GSC_AP_INT_ODL to the payload
4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now
BUG=b:317009620
TEST=build pass, boot ok and there is no CR50 TPM timeout log
Pass log:
[INFO ] Probing TPM I2C: done! DID_VID 0x504a6666
[DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a)
Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84932
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Implement map_to_lpddr_dram_type to convert MT8196 specific
DRAM_DRAM_TYPE_T values to mem_chip_type.
BUG=b:357743097
TEST=Firmware shows the following log:
LPDDR5 chan0(x16) rank0: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan0(x16) rank1: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan1(x16) rank0: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan1(x16) rank1: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan2(x16) rank0: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan2(x16) rank1: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan3(x16) rank0: density 12288mbits x16, MF 06 rev 0800
LPDDR5 chan3(x16) rank1: density 12288mbits x16, MF 06 rev 0800
Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85099
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum.
BUG=b:357743097
TEST=build pass
Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85034
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add lpddr_type to ddr_base_info struct to obtain LPDDR type
from trained memory info.
BUG=b:357743097
TEST=build pass
Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85033
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add support for MT8196 DRAM calibration. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h. As MT8196's
dramc_param struct size is different from other MediaTek SoCs,
replace the hardcoded RW_MRC_CACHE size in common code with a constant
derived from chromeos.fmd.
The common emi.c can be reused for MT8196 as well, so remove the
duplicate mt8196/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.
Test=Build pass
BUG=b:317009620
Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85098
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will
enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the
FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is
larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge
RW_MRC_CACHE from 8K to 16K.
TEST=Build pass
BUG=b:317009620
Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85094
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
The basic flash parameter table described in JESB216F can be up to 23
DWORDs (92 bytes) long which is larger than the 47 byte SPI data buffer
in the AMD SoCs which also contains the data from the command buffer
except the command byte.
TEST=Calling 'read_sfdp_data' with a data length of 256 bytes which is
larger than the buffer of the AMD SPI host controller now works and
returns the SFDP data expected from the W74M12JW SPI flash:
0x00: 53 46 44 50 06 01 02 ff 00 06 01 10 80 00 00 ff SFDP............
0x10: 84 00 01 02 d0 00 00 ff 03 00 01 02 f0 00 00 ff ................
0x20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
...
0x80: e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb . ......D..k.;B.
0x90: fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 ..........@.. .R
0xa0: 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 ....6........cv3
0xb0: 7a 75 7a 75 f7 bd d5 5c 19 f7 4d ff e9 30 f8 80 zuzu...\..M..0..
0xc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
0xd0: 00 00 f0 ff ff ff ff ff ff ff ff ff ff ff ff ff ................
0xe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
0xf0: 38 9b 96 f0 a5 ad a5 ff ff ff ff ff ff ff ff ff 8...............
Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info
from the SFDP table.
TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct
has the expected entries (RPMC available, OP2 extended status as polling
method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
JESD216F.02 and JESD260 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85008
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add basic support for the Serial Flash Discoverable Parameters (SFDP)
standard which can be used to discover the parameters to interact with
any SPI flash chip that supports this mechanism. This commit adds
functionality to find specific SFDP parameter headers and print all SFDP
parameter headers, but not to parse any SFDP parameter table. This is a
preparation for a follow-up patch that adds support to parse the RPMC
SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in
the next patch, it's marked as static inline in this commit so that the
code still build; the 'inline' keyword will be removed again in that
follow-up patch.
For now, only the legacy access protocol using single bit SPI transfers
is supported, but this should cover most of the SPI NOR flash chips. In
any other case, the code will error out. It's also assumed that the SFDP
data blocks read from the SPI flash chip are small enough to fit into
the SPI host controller buffer and don't need to be broken up into
multiple transfers. This limitation will be addressed in a follow-up
patch.
JESD216F.02 was used as a reference.
TEST=On a board with a W74M12JW SPI flash chip, calling
'spi_flash_print_sfdp_headers' prints this on the console output:
Manufacturer: ef
SF: Detected ef 6018 with sector size 0x1000, total 0x1000000
SF: Exiting 4-byte addressing mode
SFDP header found in SPI flash.
major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3
SFPD header with index 0:
table ID 0xff00, major rev 0x1, minor rev 0x6
table pointer 0x80, table length DWORDS 0x10
SFPD header with index 1:
table ID 0xff84, major rev 0x1, minor rev 0x0
table pointer 0xd0, table length DWORDS 0x2
SFPD header with index 2:
table ID 0xff03, major rev 0x1, minor rev 0x0
table pointer 0xf0, table length DWORDS 0x2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
Fix the checkpatch error:
Macros with complex values should be enclosed in parentheses
Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Due to the hardware limitation on francka, reduce the memory speed to
7467 MT/s.
BUG=b:373394046
TEST=emerge-fatcat coreboot
Change-Id: I9c45c90952e20fc96943df03f591075338624e88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85102
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch adds a new config option to limit the maximum DRAM
frequency for Pantherlake platforms.
The mainboard code should try to set `max_dram_speed_mts` from
override device tree if required.
BUG=b:373394046
TEST=Able to build and boot google/fatcat.
Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Brox mainboard does not reliably support S3 entry/exit. Hence do not
select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board
reset if the system resumes from S3.
BUG=b:337274309
TEST=Build Brox BIOS image and boot to OS. Ensure that the _S3 name
variable is not advertised in the DSDT. Trigger a S3 entry and ensure
that on S3 exit, the board reset is triggered.
Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch optimizes the reset handling in the Alder Lake romstage while
disabling the UFS controller in an uni-boot scenario (a unified AP
firmware image can boot both UFS and non-UFS systems).
It introduces a check in `mainboard_expects_another_reset()` to skip
unnecessary resets when a CSE slot switch is due, meaning CSE is not
booting from the RW slot. This saves one reset for non-UFS SKUs when
a CSE slot switch is pending.
The patch also relocates the `cse_fw_sync()` call after disabling the
UFS controllers to ensure the system reset flow can be better optimized
and combined with any expected resets due to CSE synchronization.
TEST=Able to build google/trulo eMMC sku and able to save one reset.
Without this patch:
1. Warm reset after disabling UFS (1st reset)
2. Global reset after CSE sync (2nd reset)
3. Warm reset after disabling UFS (3rd reset)
4. Boot to OS
With this patch:
1. Skip disabling UFS if CSE sync is due, aka no reset.
2. Global reset after CSE sync (1st reset)
3. CSE is booting from slot RW meaning CSE sync is done, perform UFS
disabling and issue a warm reset after disabling UFS (2nd reset)
4. Boot to OS
Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
|
|
Before entering FSP-M, AP firmware must ensure the PM1_CNT register
reflects the correct sleep state if a global reset occurred.
This is crucial when Intel CSE has reset the system, as indicated by
the global reset bit and wake status register.
If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP
firmware must enforce an S5 exit path before handing control to FSP-M
for CSE initialization. This ensures proper system initialization and
avoids potential issues caused by an inconsistent sleep state.
Additionally, clears the PM1 status register (PM1_STS) after retrieving
the power state. This prevents stale status information from persisting
across power cycles, which could lead to confusion during subsequent
boots.
BUG=b:265939425
TEST=Verified that `prev_sleep_state` holds the correct value
(5 for S5) after CSE performs a global reset.
Fixes: Inconsistent sleep state after CSE reset.
Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs
(ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type
for the RAMTOP range.
Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was
crucial to ensure data consistency, as WB caches both reads and writes.
However, since the RAMTOP range now relies on WC MTRR, the role of
CLFLUSH becomes less critical.
Removing CLFLUSH in this scenario can improve performance, as it avoids
unnecessary cache invalidations.
BUG=b:373290479
TEST=Able to build and boot google/trulo.
Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Configuring the Early Caching Ramtop range as Write-Back (WB) before
memory initialization is NOT RECOMMENDED. Speculative execution within
this WB range can lead to issues. WB configuration should be applied
to this range ONLY AFTER memory initialization is complete.
To enable Ramtop caching before memory initialization, use
Write-Combining (WC) instead of Write-Back (WB).
This change applies the recommendation by always configuring the early
ramtop caching range as WC.
BUG=b:373290479
TEST=Able to build and boot google/trulo.
Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85027
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
This patch adds a new field, `size`, to the `ramtop_table` structure to
store the size of the RAMTOP region.
The RAMTOP size is calculated as the difference between the cbmem top
and the FSP reserved memory base address, aligned up to the nearest 4MB
boundary.
This change allows for more accurate tracking of the RAMTOP region and
improves compatibility with different memory configurations.
Previously, the RAMTOP size was always assumed to be 16MB. This could
lead to boot hangs on systems with different memory configurations,
where the actual RAMTOP size exceeded 16MB.
By dynamically calculating and storing the RAMTOP size, this patch
ensures that the correct memory range is used for intermediate
caching, preventing boot hangs and improving boot speed.
The `update_ramtop()` function is updated to write the calculated
RAMTOP size to CMOS along with the RAMTOP address.
The `early_ramtop_enable_cache_range()` function is also updated to
use the RAMTOP size from CMOS to set the correct MTRR range.
BUG=b:373290479
TEST=Built and booted successfully on various platforms. Verified that
the RAMTOP size is correctly calculated and stored in CMOS
Change-Id: I16d610c5791895b59da57d543c54da6621617912
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85003
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
Change-Id: Ibd7a7b8c9e1461fa665bb72082489b9a48da63c3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82767
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The overall procedure is taken from the original code that was removed
in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the
start and end was updated (expect timestamp and BIST result in `xmm*'
registers), stack is aligned to 16B, and linker symbols are now used
for the CAR and cached XIP ranges.
Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82766
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The first steps to bring C7 and CX700 support back mainline. Most is
skeleton copied from the `min86' example.
The romstage entry is placed in the northbridge code, as that's where
we'll perform raminit. Support to read the FSB frequency is added right
away, same for a reset function (using CF9 reset), as both are required
for a minimal build test.
A mainboard VIA EPIA-EX is also introduced for build testing, and in
later stages boot testing as well.
Links:
DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf
PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221
Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Elan touchscreen override devicetree for rull based on the latest
schematic NB7559_MB_SCH_V1_2024_1010.pdf.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. touchpanel function is normal and 'evtest' command displays the
touch point
Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85015
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Map a proper DRAM range for memory test during calibration.
TEST=memory test passed on Rauru
BUG=b:317009620
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85035
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Reduce stop delay for touchscreen based on the latest spec (EKTH6915
Product Spec_V1.0). This will optimize the touch response time to keep
the S0ix resume time under 500ms.
BUG=b:378012214
TEST=Verify improvement in resume time on Riven.
Change-Id: Id7dcbc393bfae9bb62b5700bb9042a543152e968
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85039
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Increase the bootblock size to support TPM.
TEST=Build pass
BUG=b:317009620
Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
