summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2022-12-21mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaksJan Samek
Contrary to mc_ehl2, which this variant is based on, this board doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the attempts to modify the bridge's registers unnecessary. Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Use runtime detection for touchscreens/digitizersMatt DeVillier
Switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens and digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. Test: build/boot Windows/Linux on various octopus variants, verify touchscreens/digitizers functional, dump ACPI tables and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Implement touchscreen/digitizer power sequencingMatt DeVillier
For octopus variants with a touchscreen/digitizer, drive the enable and reset GPIOs high in romstage, then disable the reset GPIOs in ramstage. Where available, only set the GPIOs for SKUs which have a touchscreen. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). TEST=tested with rest of patch train Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/amd/common/psp_verstage: Report previous boot statusKarthikeyan Ramasubramanian
Add support to report previous PSP boot failure to verified boot. This is required specifically on mainboards where the signed AMDFW blobs are excluded from vboot verification. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the appropriate FW slot is chosen. Cq-Depend: chromium:4064425 Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/intel/mtlrvp: Enable ChromeOS build for mtlrvpHarsha B R
This patch enables building ChromeOS for mtlrvp. Patch includes, 1. Add cros_gpios for mtlrvp 2. Add chrome OS configuration in Kconfig 3. Add Chromeos.c BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train (CB: 69886) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/intel/meteorlake/romstage: Rewrite the if conditionSridhar Siricilla
The patch rewrites `if` condition by connecting two different conditions using the logical and(&&) operator without changing the semantics to improve the code readability. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-21mb/google/skyrim: Fix Bluetooth configurationKarthikeyan Ramasubramanian
Power resource for Bluetooth device is not configured correctly in the device tree. Fix Bluetooth devicetree configuration. BUG=b:262785310 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able to connect to a Bluetooth headset. Change-Id: Id980424349537be35860dec04cc823d419cefe2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20mb/google/skyrim/var/frostflow: Config I2C frequency for touchpad.Rex Chou
1.Config setting for touchpad I2C BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: 1.I2C0 (Touchpad): 385.7kHz Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20soc/intel/xeon_sp: Set IA32_SMRR_PHYSMASK lock bitJohnny Lin
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the same MSR that has been locked by another thread. Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock bit. Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-20mb/starlabs/starbook/adl: Set thermal trip based on power profileSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07be0aa2144b7718e28f1f675978b4b4b92752ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69492 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADLKapil Porwal
Add missing CNVI IDs for ADL - ADL-P: 0x51f2, 0x51f3 ADL-S: 0x7af1, 0x7af2, 0x7af3 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-20soc/intel/*/crashlog.[ch]: Remove unused includesElyes Haouas
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Add files required for ramstage and SMMHarsha B R
This patch adds files required for ramstage and SMM. 1. Add file required for ramstage (mainboard.c) 2. Add smihandler.c for SMM BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Enable EC for mtlrvpJamie Ryu
This patch will initialize EC for mtlrvp which includes, 1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC) 2. Add respective ACPI configuration 3. Add ec.c required for ramstage 4. Program EC ranges as part of devicetree.cb 5. Enable VBOOT in Kconfig BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with CHROME_EC using subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-19tree: Replace Or(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b)` with `a | b`. Change-Id: I73842cd4843ebb0b48440059ae9dcf6c82235a76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70845 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19tree: Replace LAnd(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I6b7b958e2d2a43926663a8dc8755613abb07e949 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70844 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19tree: Replace XOr(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where possible. Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19soc/intel/meteorlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. This patch is backported from commit 8409f156d588e74932924ae8aac69478a4b6388e (soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module) Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-19soc/intel/meteorlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Meteor Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). This patch is backported from commit b6c3a0325b9b0462cca81ea4134efb6b73756577 (soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callback). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-19drivers/intel/fsp2_0: Implement `mps2_noop_get_number_of_processors()`Subrata Banik
This patch implements mps2_noop_get_number_of_processors() API with minimal information required for Intel MTL FSP to utilise the `MP_SERVICES_PPI_V2_NOOP` config. The major difference between Intel ADL and MTL FSP in terms of doing CPU feature programming aka utilizing MP PPI wrapper code is that, starting with MTL, FSP has dropped the `SkipMpInit` UPD. It means now, coreboot doesn't have any way to skip FSP doing MP Init operation. But during ADL, coreboot had introduced the MP_SERVICES_PPI_V2_NOOP config that is used to skip FSP about actually running any CPU feature programming on APs. The idea is to use the same config even in MTL to provide only the must have information (to bypass any assert in FSP during debug image) to FSP. Passing `FSP_UNSUPPORTED` from mps2_noop_get_number_of_processors() results in `assert` while compiling FSP in debug mode hence, implementing the function to pass only the information about BSP being the active processor along with passing `FSP_SUCCESS` (eventually it makes FSP happy and doesn't run into any issue in debug and/or release mode). TEST=Able to build and boot Google/Rex and Google/Kano while coreboot skip calling into FSP for doing MP init. Change-Id: I75d7e151699782210e86be564b0055d572cacc3f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70555 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-19ec/starlabs/merlin: Add EC related files for Cezanne laptopsSean Rhodes
Add EC memory layout and Q events for AMD Cezanne based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Change-Id: I87806b830b3d58a6ce3b89f45b5a07f4502a87f3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68333 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-19mb/google/octopus: Add NHLT endpoints for Cirrus Logic codecMatt DeVillier
Add NHLT endpoints for octopus boards using CS42L42 codec. Reuse method to add da7219 endpoint as the routing is identical. TEST=boot Windows, verify audio working with coolstar's audio drivers. Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/octopus: update variant VBTsMatt DeVillier
Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP display init to use native panel resolution instead. TEST=build/boot multiple google/octopus variants with edk2 payload, verify boot logo not distorted/stretched. Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/hatch/kohaku: set VBT boot resolution to 1080pMatt DeVillier
Boot menus are too small at native 4K res on some panels, so set fixed display resolution to 1920x1090p TEST=build/boot KOHAKU with 4K display, verify boot menu text legible. Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/brya/var/marasov: Configure I2C high and low timeFrank Chu
Adjust I2C speed for codec, TPM, touchpad, touchscreen. BUG=b:260565911 TEST=Built and verified adjusted I2C speed Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2022-12-17lib: Hook up libhwbase in romstageJeremy Compostella
It's hidden behind the configuration option `CONFIG_ROMSTAGE_LIBHWBASE'. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. Running Ada code in romstage and more particular libhwbase brings a few challenges as global initialized variables are not supported in Cache-As-Ram mode. 1. The libhwbase dynamic mmio driver implementation makes the Gnat compiler generate some global initialized variables. For this reason, when compiled for romstage or for romstage and ramstage the static mmio driver is enforced (`HWBASE_STATIC_MMIO'). 2. The Gnat compiler generates elaboration functions to initialize program data at runtime. These elaboration functions are called by the romstage_adainit() function. The data references symbols suffixed by `_E'. Even though these symbols, at compilation time, do not contain any data and are filled with zeros, the Gnat compiler installs them in the .data section. Since these symbols are actually filled with zeros, it is safe to install them in the .bss section. cf. https://docs.adacore.com/gnat_ugn-docs/html/gnat_ugn/gnat_ugn/elaboration_order_handling_in_gnat.html#elaboration-code This patch requires the libhwbase https://review.coreboot.org/c/libhwbase/+/69854 CL. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libhwbae compiles for romstage and loads successfully Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70275 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17Add option to use Ada code in romstageJeremy Compostella
If selected, libgnat is linked into romstage. In addition, a call to romstage_adainit() is added to support Ada program data initialization. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Ada code compiles for romstage and loads successfully Change-Id: I74f0460f6b14fde2b4bd6391e1782b2e5b217707 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70274 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17soc/intel/cmn: Clear interrupt status after HECI-1 has been receivedJohnny Lin
According to Intel doc#630774, BIOS should clear Host Interrupt Status if it has read all the slots of the message from the ME circular buffer. Since this is not found in client ME document, add a Kconfig SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server ME SKU. On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the change can avoid seeing below Linux warning during boot with Linux v5.12: [ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option) [ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0 [ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1 [ 17.922327] Call Trace: [ 17.927780] <IRQ> [ 17.932253] dump_stack+0x64/0x7c [ 17.939640] __report_bad_irq+0x37/0xb1 [ 17.948206] note_interrupt.cold.11+0xa/0x63 [ 17.957713] handle_irq_event_percpu+0x6a/0x80 [ 17.967626] handle_irq_event+0x2a/0x50 [ 17.976163] handle_fasteoi_irq+0x9e/0x140 [ 17.985305] __common_interrupt+0x38/0x90 [ 17.994255] common_interrupt+0x7a/0xa0 [ 18.002821] </IRQ> [ 18.007514] asm_common_interrupt+0x1e/0x40 Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17lib: Introduce fw_config_get_fieldEric Lai
In some cases, fw_config is used for ids like sar_id, sku_id etc. To avoid calling fw_config_probe over and over, hence provide the method to return the value then caller can use the switch case instead of if else statement. TEST=get fw_config field value on nivviks. [INFO ] fw_config get field name=DB_USB, mask=0x3, shift=0, value =0x1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iae89668e8fe7322d5a4dcbf88a97d7ed36619af5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settingsJan Samek
Based upon hardware differences from mc_ehl2, disable RP7 and enable RP3 and RP5. Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17mb/siemens/mc_ehl3: Add board variant based on mc_ehl2Jan Samek
Add a new mc_ehl variant, which is based on mc_ehl2 implementation. This patch uses a copy of mc_ehl2 with changes only in naming as a starting point for the new mc_ehl3 variant. Follow-up patches will introduce the functional changes against mc_ehl3. Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-17soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-NReka Norman
On nissa, sending EOP late improves boot time by about 57ms. Before (SOC_INTEL_CSE_SEND_EOP_EARLY): 943:after sending EOP to ME 931,206 (58,431) 943:after sending EOP to ME 932,911 (58,427) 943:after sending EOP to ME 930,908 (58,429) 943:after sending EOP to ME 941,357 (61,748) 943:after sending EOP to ME 933,289 (62,050) 943:after sending EOP to ME 939,578 (62,453) 943:after sending EOP to ME 932,491 (62,050) 943:after sending EOP to ME 929,693 (62,655) 943:after sending EOP to ME 942,247 (62,654) 943:after sending EOP to ME 936,984 (61,751) After (SOC_INTEL_CSE_SEND_EOP_LATE): 943:after sending EOP to ME 1,107,816 (3,498) 943:after sending EOP to ME 1,053,286 (25,212) 943:after sending EOP to ME 1,124,095 (3,511) 943:after sending EOP to ME 1,098,591 (3,498) 943:after sending EOP to ME 1,107,772 (3,499) 943:after sending EOP to ME 1,080,008 (45,969) 943:after sending EOP to ME 1,081,754 (8,024) 943:after sending EOP to ME 1,109,193 (4,102) 943:after sending EOP to ME 1,088,866 (4,201) 943:after sending EOP to ME 1,081,684 (4,203) BUG=b:247902068 TEST=EOP time is improved on nissa (measurements above). Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17drivers/generic/nau8315: Change method for HID assignmentDavid Lin
This patch is to change method of HID assignment with compatible id style in nau8315_config and allow mainboards to set it. Signed-off-by: David Lin <CTLIN0@nuvoton.com> Change-Id: Ia6f02e495eeb06290947edc9e44fa25a4ce18956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69965 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-17mb/google/nissa/var/yaviks: Enable wifi SARWisley Chen
Enable wifi sar function for yaviks. Use the fw_config to separate SAR setting for different wifi card. BUG=259199095 TEST=build, enabled iwlwifi debug, and check dmesg Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17mb/google/nissa/var/pujjo: Tunning RegProxCtrl0 register for SX9324Stanley Wu
Update SX9324 RegProxCtrl0 register settings based on tunning value from P-sensor vendor. BUG=b:242662878 TEST=i2cdump -y -f 13 0x28 on Pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17soc/intel/common: Remove read-only from chip_get_common_soc_structureSean Rhodes
Remove the `const` property from chip_get_common_soc_structure so that the returned values can be overwritten as required. Cc: th3fanbus@gmail.com Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-17device/Kconfig: bump desktop framebuffer max height/width to support 4KMatt DeVillier
Increase the default linear framebuffer max height/width for desktops so that native display resolution works properly on 2160p and 1440p ultrawide displays. TEST=build/boot google/fizz, verify libgfxinit display init works properly on 3440x1440p and 3840x2160p displays. Change-Id: I95a1f1275a4faea195b73997c648023119807958 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-17device/oprom/yabel/io: use __fallthrough instead of commentFelix Held
Unlike gcc, a clang build will fail when only a comment is used to indicate that the fallthough is intended. To fix the clang build, use __fallthrough instead. This will fix the build errors introduced by commit f45c7671d9ed ("Set x86_64 as supported architecture for clang") that enabled clang builds for a case that uses yabel to run the VBIOS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ed337025adeb833f352d198fc0f13b5e1c209c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70889 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-17soc/intel/skylake/irq.c: Fix undefined `memcpy()`Angel Pons
The original value of the `DevIntConfigPtr` is unknown, and there's no way to be absolutely certain that it actually points to usable memory. Instead of copying the data, update the pointer's address to reference the global variable directly. It is assumed that FSP does not write to the memory pointed by `DevIntConfigPtr`. Confirming this assumption is pointless; one might as well reimplement FSP instead. Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-12-17mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variantBen-StarLabs
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_202209`: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Ben-StarLabs <ben@starlabs.systems> Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17mb/google/skyrim: Configure RO and RW SPL filesKarthikeyan Ramasubramanian
This will help to integrate RO SPL table in RO partitions such that it is used before PSP verstage is loaded. After PSP verstage, SPL table in RW partition gets used. BUG=b:243470283 TEST=Build Skyrim BIOS image and boot to OS. Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16mb/google/brya/var/lisbon: Use RPL FSP headersKevin Chiu
To support an RPL SKU on lisbon, lisbon must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL FSP headers for lisbon. BUG=b:246657849 BRANCH=firmware-brya-14505.B TEST=FW_NAME=lisbon emerge-brask intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage flash and boot lisbon to kernel. Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-16drivers/i2c/designware: translate return type in dw_i2c_dev_transferFelix Held
dw_i2c_transfer returns an enum cb_err type, but dw_i2c_dev_transfer returns an int, so explicitly translate between the types. Since dw_i2c_transfer only returns either CB_SUCCESS or CB_ERR which are defined as 0 and -1, this won't change behavior of dw_i2c_dev_transfer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf2cbcf6564035d5c0fc13f5d5e7ac0d0425e85d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16Set x86_64 as supported architecture for clangArthur Heymans
This boots on both qemu and real hardware now. Change-Id: Ibd320059cff575847bbf1844b5bb100312f77916 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans
Clang generates R_X86_64_32S symbols that get truncated. TESTED: - prodrive/hermes boots with GCC and clang - MTRR are properly cleared (tested by filling in both MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing) Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16nb/intel/haswell: Add native raminit scaffoldingAngel Pons
Implement some scaffolding for Haswell native raminit, like bootmode selection, handling of MRC cache and CPU detection. Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16sb/intel/lynxpoint: Add native PCH initAngel Pons
Implement native PCH initialisation for Lynx Point. This is only needed when MRC.bin is not used. Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16sb/intel/lynxpoint: Add native thermal initAngel Pons
Implement native thermal initialisation for Lynx Point. This is only needed when MRC.bin is not used. Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64180 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16sb/intel/lynxpoint: Add native USB initAngel Pons
Implement native USB initialisation for Lynx Point. This is only needed when MRC.bin is not used. TO DO: Figure out how to deal with the FIXME's and TODO's lying around. Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16haswell/lynxpoint: Add native early ME initAngel Pons
Implement native early ME init for Lynx Point. This is only needed when MRC.bin is not used. Change-Id: If416e2078f139f26b4742c564b70e018725bf003 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16haswell/lynxpoint: Add native DMI initAngel Pons
Implement native DMI init for Haswell and Lynx Point. This is only needed on non-ULT platforms, and only when MRC.bin is not used. TEST=Verify DMI initialises correctly on Asrock B85M Pro4. Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16soc/intel/common: Drop unreferenced DP related macrosSridhar Siricilla
The patch drops the unreferenced DP related timeout macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16mb/google/brya/var/marasov: Update gpio table for EVTFrank Chu
BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-16mb/google/brya/var/marasov: Disable unused PCIE8 for s0ixFrank Chu
Disable unused PCIE8 for fix system can not enter S0ix completely. BUG=b:261915226 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-16mb/google/geralt: Revise the naming of MIPI PWM control GPIOLiju-Clr Chen
Rename the MIPI PWM control GPIO to be consistent with the schematic. BUG=b:244208960 TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-16mb/google/geralt: Pass GPIOs to allow backlight control in payloadsBo-Chen Chen
There are two ways to control backlight in geralt: 1. MIPI/eDP panel => control backlight via the GPIOs. (`backlight chip enable` and `PWM dimming control`) 2. eDP OLED panel => enable backlight via `backlight chip enable` and control dimming over AUX. For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs will be passed from coreboot. For eDP OLED panel(#2), only the "backlight enable" GPIO will be passed. If depthcharge successfully gets the GPIOs, it will use them to control backlight. BUG=b:244208960 TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16mb/google/brya/var/marasov: Enable ELAN touchscreenFrank Chu
Correct touchscreen setting to make touchscreen function workable. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=Built and verified touchscreen function Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16drivers/i2c/designware/dw_i2c: handle bus < 0 in dw_i2c_dev_transferFelix Held
dw_i2c_soc_dev_to_bus will return -1 if it failed to find an I2C bus number for a device. In this case return -1 instead of implicitly casting the -1 to an unsigned int and passing that as bus number to dw_i2c_transfer. The dw_i2c_base_address call inside _dw_i2c_transfer already ended up handling this error case correctly, but better handle the error more directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06b6005cee0c5c43855cb5b388a9911fc286c984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16soc/amd/common/block/i2c: don't call die() when MMIO address is NULLFelix Held
There's no need to call die() in the case that the MMIO address of the I2C controller is NULL, so handle this case by returning a failure instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12c143916ad551c56cc4ff75ae23754018817505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16soc/intel/apollolake/acpi/northbridge.asl: Fix commentElyes Haouas
This fixes the following error: In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21: src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment] PXEN, 1, /* Enable */ ^ Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-16security/vboot: Update vbnv_init signatureKarthikeyan Ramasubramanian
If the temporary nvdata storage inside the vboot context is already initialized then return immediately without reinitializing from the backup NV storage. This allows vbnv_init to be called more than once. Also the check to enable USB Device Controller (UDC) happens after NVdata is initialized. Hence the nvdata in vboot context can be used instead of reading from the backup storage again. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Change-Id: Id72709e2fc3fe6a12ee96df8df25e55cf11e50a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-16ec/kontron/it8516e/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I16890206d517f0455d29c1642cbbe642a3312481 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70679 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16cpu/x86/mtrr: rename local cpu_idx variable and make it constFelix Held
After the previous patch this local variable is no longer the mpinit CPU index, but the LAPIC ID, so rename it. Since it will only be set once, it can also be marked as const. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4fad4e1095478213727bee8586852f9d5a7d18e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70798 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-12-15mb/google/rex: Add support for WWAN over USB3Subrata Banik
This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1 schematics dated 12/14/2022. TEST=Able to build Google/Rex. Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/rex: Modify the PIN name as per schematicsSubrata Banik
This patch updates the GPIO PIN name as per Proto 1 schematics dated 12/14/2022. TEST=Not code change, just updated the comment section. Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15soc/intel/{adl, common}: provide a list of D-states to enter LPMEran Mitrani
This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/skyrim/var/frostflow: Update SPD file for H9JCNNNFA5MLYR-N6EFrank Wu
Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex instead of spd-9.hex. Reserve RAM ID 3 for it, so the RAM ID table remains the same. BUG=b:261530632 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage Then boot devices successfully Change-Id: I1b683168310f74a07d246af8618b977cce32287a Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-15mb/google/nissa/var/pujjo: Modify WWAN warm reset sequenceStanley Wu
pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff minimum 500ms requirement. BUG=b:260380268 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-15soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitionsSubrata Banik
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM Configuration +-----------------------+-------------------------------+ | Field Description | ASPM Support | +-----------------------+-------------------------------+ | 00b | No ASPM support | +-----------------------+-------------------------------+ | 01b | L0s Supported | +-----------------------+-------------------------------+ | 10b | L1 Supported | +-----------------------+-------------------------------+ | 11b | L0s and L1 Supported | +-----------------------+-------------------------------+ 100b aka 0x4 is added by FSP to allow auto configuration (to avoid conflicting with the PCI specification defined values). Additionally, changed enum definition which is now meeting the FSP expectations better. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15mb/google/rex: Add RTD3 support for discrete wifi moduleKapil Porwal
BUG=none TEST=Build and boot to the OS on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15nb/intel/sandybridge/sandybridge.h: Remove unnecessary guardElyes Haouas
__ACPI__ is covered through __ASSEMBLER__. Change-Id: I6a637e63c6bbe4af7cd52be1893e47d6b5967886 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70697 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15mb/google/brya/var/zydron: Enable Fast VMode for zydronDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:252966799 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15soc/intel/alderlake: Disable L1 substates for PCIe compliance test modeBora Guvendik
Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. BUG=b:235863379 TEST=Boot in compliance mode, check FSP settings Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-15cpu/x86/mtrr: use lapicid instead of cpu_index callsFelix Held
The cpu_index function can't be used before mpinit, so use lapicid calls instead. This fixes the regression introduced by commit 4c3749884d71 ("cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs") and also reverts also commit b3261661c703 ("cpu/x86/mtrr/mtrr: fix printk format strings"), since lapicid returns an unsigned int while cpu_index returns an unsigned long. TEST=Mandolin boots again and doesn't fail when it first tries to print the MTRR configuration Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0d226704051ab171891775a618ce7897b74fde16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70797 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-15mem_chip_info: Fix potential overflowJulius Werner
The calculation for mem_chip_info_total_density_bytes() may already overflow in the intermediate 32-bit calculations before being assigned to the 64-bit result variable. Fix that. Fixes Coverity issue: CID 1501510 BRANCH=corsola Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I73da014c953381974c6ede2b17586b68675bde2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-14mb/google/skyrim: Enable PCIe RTD3 supportJasonNien
Add PCIe RTD3 support for Skyrim BUG=b:245550573 TEST=Boot/Reboot cycles and Suspend_stress_test 10 times Signed-off-by: JasonNien <finaljason@gmail.com> Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove more TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/amd/common/block/espi_util: drop unneeded check in espi_get_configFelix Held
Since soc_get_common_config will either return a valid pointer or cause a linking error, this function will also return a valid pointer or cause a linking error, so no need for additional runtime checks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/*/config: drop invalid commentFelix Held
Since commit 28e61f16341f ("device: Use __pci_0_00_0_config in config_of_soc()") config_of_soc() was changed form being an actual function to a macro for the __pci_0_00_0_config struct pointer generated by util/sconfig. This change didn't only improve linker optimizations, but also turned runtime errors into link-time errors, so it's guaranteed that __pci_0_00_0_config won't be NULL and config_of_soc() won't "return" NULL. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/espi_util: make espi_set_initial_config non-fatalFelix Held
Improve the espi_set_initial_config implementation so that a failure in there due to an invalid configuration won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatalFelix Held
Improve the eSPI pin configuration setup so that a failure in there won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. This will prevent an early boot failure if the EC is missing or the eSPI interface is in a non-functional state. Also slightly shorten the function names so that the code still fits into 96 chars. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-12-14device/cpu_device.c: Zero initialize structArthur Heymans
Don't rely on this being 0. Change-Id: I7c0d16b6a265bf9c7abcfdf2f18a43706ee03ea1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69752 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14cpu/x86/mp_init.c: Improve AP entry pointArthur Heymans
Make sure that a pointer exists before dereferencing it. Change-Id: I1a9833bb9686451224249efe599346f64dc37874 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14soc/intel/common: Add helper function to get DP modeSridhar Siricilla
The patch adds helper function to get the DP mode. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14cpu/intel/206ax: Fix generating C state entriesArthur Heymans
The struct device passed to this function is the cpu cluster and not individual lapic. This fixes a regression introduced by cdb26fd (cpu/intel/model_206ax: Remove fake lapic device) Change-Id: I586e13a723303b8d639d526a175bd6828465a607 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-14soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macroSubrata Banik
This patch drops the redundant macro to define CPU BCLK and instead uses `CPU_BCLK_MHZ` config to calculate the `smbios_cpu_get_max_speed_mhz`. TEST=Able to see max cpu speed is correct in smbios table while trying on Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop NEM supportSubrata Banik
This patch drops NEM support from MTL and enables eNEM support. BUG=b:217130861 TEST=Able to build and boot Google/Rex in eNEM mode. Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Add required configs to enable eNEMSubrata Banik
This patch combines all required configs under one umbrella config named `METEORLAKE_CAR_ENHANCED_NEM`. MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not selected. BUG=b:217130861 TEST=Able to build and boot Google/Rex. Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Reorg TCSS related configsSubrata Banik
This patch moves all required TCSS related configs under one umbrella config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will help in future to deselect the TCSS support for MTL SoC SKUs. TEST=Able to build and boot Google/Rex. Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14drivers/wwan/fm: Fix typoSubrata Banik
This patch fixes a typo by adding `Arg0 = 0` to define warm reset. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I92b81697a254c9dab127b200174d32554db1b5cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70721 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80Subrata Banik
Update header files for FSP for Meteor Lake platform to version 2431_80, previous version being 2404_00. FSPM: 1. Address offset changes FSPS: 1. Address offset changes Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. This patch is backported from commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable). Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Remove `FIXME` as SkipMpInit UPD has deprecatedSubrata Banik
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP doesn't like to allow an option for boot firmware to perform CPU feature programming being independent of FSP. Change-Id: I6447937838ab91551d172936cbb4201ea86a614b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>