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2015-05-21Kill ENABLE_TPM.Vladimir Serbinenko
It's used only in P470 and lynxpoint machines. Remove it from other southbridges. New machines should use src/drivers/pc80/tpm. Change-Id: I4741e76df4c6204d65562f016abac9ed60558432 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21lenovo: Remerge smbios_mainboard_bios_version.Vladimir Serbinenko
Change-Id: I8df5b7f6707957b925f7bb4dc06a717252c70868 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10275 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2015-05-21Remove unused functionsPatrick Georgi
acpi_fill_slit and acpi_fill_srat were removed in commit 5e597572e. Take care of the boards that were added in the mean time. Change-Id: I907e51de5d4ce9acfcce82e6bb30eefff312d35d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-20acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20Remove noop smihandler.c in several mainboards.Vladimir Serbinenko
Change-Id: I14e381e1f1c825699063ca3df20e450f7510b040 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20bd82x6x: Merge common apmc finalize procedure.Vladimir Serbinenko
Change-Id: I9c938b8a69479fae6b0eb99d1135f1caaf26d0e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10227 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20build system: use archives, not linker action to shorten command linesPatrick Georgi
Intermediate linking may distort linker behavior (in particular related to weak symbols). The idea is that archives are closer to 'just a list of object files', and ideally makes the linker more predictable. Using --whole-archive, the linker doesn't optimize out object files just because their symbols were already provided by weak versions. However it shouldn't be used for libgcc, because that one has some unexpected side-effects. Change-Id: Ie226c198a93bcdca2d82c02431c72108a1c6ea60 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10139 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-05-19superio/nuvoton: Add support for Nuvoton NCT6779DMatt DeVillier
Add support for Nuvoton NCT6779D, using NCT6776 as a baseline Change-Id: I020a21267f7e30bdea4bb5f83d67bd94082fdf05 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10232 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-05-19intel/haswell: Drop MONOTONIC_TIMER_MSRPatrick Georgi
The variable was set on all haswell boards, so we can do it like on broadwell where the MSR based timer is assumed to be around, too. Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10256 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
DYNAMIC_CBMEM is only selected a couple of times but never declared or read. Remove it. Change-Id: I5016dac2c935d3f261001e9f388a8989540e93ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
MAINBOARD_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere (with no overlap), and never read. Remove it. Change-Id: Ica1f16182b556dbf4a3b747237af74bcc4c0608c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
CPU_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere (with no overlap), and never read. Remove it. Change-Id: I3f294b0724a87876a7e2f274e6933fe10321a69d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19arm64: Make SPSR exception masking on EL2 transition explicitJulius Werner
The configuration of SPSR bits that mask processor exceptions is kinda oddly hidden as an implict part of the transition() function right now. It would be odd but not impossible for programs to want to be entered with enabled exceptions, so let's move these bits to be explicitly set by the caller like the rest of SPSR instead. Also clear up some macro names. The SPSR[I] bit is currently defined as SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit actually *disables* (masks) interrupts. The fact that there is an additional SPSR_IRQ_MASK definition with the same value but a different purpose doesn't really help. There's rarely a point to have all three of xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so simplify this to a single definition per bit. (Other macros in lib_helpers.h should probably also be overhauled to conform, but I want to wait and see how many of them really stay relevant after upcoming changes first.) BRANCH=None BUG=None TEST=None Change-Id: Id126f70d365467e43b7f493c341542247e5026d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297 Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270785 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10250 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Add support for using ARM Trusted Firmware as secure monitorJulius Werner
This patch adds support for integrating the runtime-resident component of ARM Trusted Firmware (github.com/ARM-software/arm-trusted-firmware) called BL31. It expects the ARM TF source tree to be checked out under $(top)/3rdparty/arm-trusted-firmware, which will be set up in a later patch. Also include optional support for VBOOT2 verification (pretty hacky for now, since CBFSv1 is just around the corner and will make all this so much better). BRANCH=None BUG=None TEST=Booted Oak with ARM TF and working PSCI (with additional platform patches). Change-Id: I8c923226135bdf88a9a30a7f5ff163510c35608d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a1b3b2d56b25bfc1f3b2d19bf7876205075a987a Original-Change-Id: I0714cc10b5b10779af53ecbe711ceeb89fb30da2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270784 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10249 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make more obvious that there's no code execution here after payload_entry. [pg: taken from patch linked below] Change-Id: Ia341e5d290b10ad5ba3edb349b8a7f619022d99f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10247 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: we need to sync the i-cache in both code paths, so do it in a single location. [pg: taken from patch linked below] Change-Id: Iab173acfc6d66e4dccb6f6ab916aea2007632bfd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10246 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make spintable handling optional through a kconfig flag. [pg: taken from patch linked below] Change-Id: I64610640835473fcc3d9eff01feb5f861b753eb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10245 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable. Improve locality of code. [pg: taken from patch linked below] Change-Id: Ie9ea6a10b9d5e5c33bf020369afcae4f10ef068e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10244 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: the secure monitor entry is now guarded by an explicit if statement for its Kconfig rather than hiding than in the corresponding header file. This makes it clear that there are two (soon three) separate code paths here. Change-Id: I44993da7a982b08f485b93ffc522d193bb3fa118 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10243 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Rename Kconfig options for secmon and spintable to be prefixed with ARM64_ instead of ARCH_, which seems to be the standard throughout the rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this provides a clearer separation between generic options that are selected by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to some of the MAINBOARD_HAS_... we have) and options that only make sense in the context of a single architecture. Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10242 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
The secure monitor entry is now guarded by an explicit if statement for its Kconfig rather than hiding than in the corresponding header file. This makes it clear that there are two (soon three) separate code paths here. Similar change for the optional spintable feature in the "legacy" payload entry path. [pg: split out from the patch linked below] Change-Id: Ia1554959b3268b718a9606e2f79d8f22f336c94d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10248 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Remove the secmon Kconfig guard from Makefiles that add to the secmon class since they are redundant (the class is simply not used when compiling without secmon) to improve readability/ease-of-use. [pg: taken out of the patch linked below] Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10241 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Reorganize Kconfig (split out from the original patch linked below) Change-Id: I84ec8e453dd7a3980de95a455ad21494c601a98c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10240 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19nehalem native gfx init: Adjust state to be compatible with OPROM.Vladimir Serbinenko
My main payload is GRUB and I load SeaBIOS as secondary payload when for some reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom (SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either completely uninited gfx or some special state in gmbus and software scratch registers. Provide this state. The only alternative without this patch for such usecase is to use oprom and I'd like to avoid doing so when going my main boot path to GNU/Linux. Change-Id: Ic157a6a580d7a5048ac28155e0d6b3433bbd1f2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19ivybridge native gfx init: Adjust state to be compatible with OPROM.Vladimir Serbinenko
My main payload is GRUB and I load SeaBIOS as secondary payload when for some reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom (SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either completely uninited gfx or some special state in gmbus and software scratch registers. Provide this state. The only alternative without this patch for such usecase is to use oprom and I'd like to avoid doing so when going my main boot path to GNU/Linux. Change-Id: I38e78fb845e43b81df084cd4d65f4618bfb2506d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19gma/edid: Fix gma register access.Vladimir Serbinenko
0x20 was incorrectly represented as 4 * 5 while in fact it's 4 * 8 Change-Id: I6053a3baa6de0da9f1d648009353bc1fe542f81f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19Move smi trap sample to documentation, don't keep it in every mobo.Vladimir Serbinenko
Sample code belongs to documentation, not copied 100x over prodcution code. Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19Remove useless extern gnvs declaration in smi handlers.Vladimir Serbinenko
Change-Id: I3047badea8d4f61155f4e4f7d3d078426948162a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10228 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19vboot: remove vboot_context.hAaron Durbin
The vboot_context.h file hasn't been used since commit 6d65f796db. Remove it. Change-Id: I57a6c619c6e1f57be6963da2954329bc9c007dd8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10223 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19pcengines/apu1: Add switch between UART and GPIO modesKyösti Mälkki
These are alternative customer options connected to J19 header. We need to avoid modifying devicetree.cb, so we fix devicetree for the super-io device-enables at runtime instead. Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19x86: garbage collect SMM programsAaron Durbin
The non-module SMM programs were not being garbage collected during linking. Do this so that one doesn't have to add dependencies for unused functions in SMM. TEST=Interrogated readelf -e smm.elf on both builds as well as diffed the symbol table. Runtime testing was not done. Change-Id: I31991496d92191e540df6340c587eec09c7022b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10219 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19regions: add more helpersAaron Durbin
Fill out functions to get the offset and size for both regions and region_devices. Additionally add a helper for memory mapping an entire region_device. Change-Id: I8896eaf5b29e4a67470f4adc6f5b541566cb93b5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10215 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-18drivers/gic: reprogram the GIC CPU interface to bypass IRQJoseph Lo
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. So the CPU can exit from WFI when an asserted IRQ is coming. This is critical for power gating a CPU. BRANCH=none BUG=chrome-os-partner:39620 TEST=testing with CPU idle with power down state support and CPU can wake up normally Change-Id: I71ac642e28024a562db898665b74a5791fce325a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a3f098cbf3fbfdab8150ebd4fd688fdb472b529 Original-Change-Id: I20569a18f34a4b11b8c8c67ea255b3d0f021839f Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269116 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10172 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-18arm64: psci: add cpu_suspend supportJoseph Lo
Implement the cpu_suspend for the PSCI service in secmon. BRANCH=none BUG=chrome-os-partner:39620 TEST=test with CPU idle driver that invoke the cpu_suspend of PSCI Change-Id: I4cdfab88bf36bf432fb33c56c1ea114b384528f8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 90b3ea3fcb21cb393e30a8359f0328054961f6d5 Original-Change-Id: Ieb76abc017b9c3e074cc018903cef72020306a8f Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269115 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10171 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-17x230/smihandler: Kill non-functional brightness code.Vladimir Serbinenko
Just a copypaste, never worked. Change-Id: I84b46a5a0ada2e472894c63a17170e0979ad9160 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10218 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-05-17nuvoton/nct6776: there is no IRQ for LDN8Felix Held
Change-Id: Ib4ee3633d210a05e06ed95fc13830cc692095501 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/10235 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-17lenovo/x200: Enable wacom digitizer support for x200tAlex David
This patch is based on commit f2b3cd63 (lenovo/x60: Support digitizer on X60t and X201t) Tested on Thinkpad X200 Tablet (7450): all pen functionallity works (i.e. movements, presure sensitivity and buttons) Change-Id: I9bd18642a6ea4211dc3be065456a507fc0b72561 Signed-off-by: Alex David <opdecirkel@gmail.com> Reviewed-on: http://review.coreboot.org/10208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-16i945: Disable check for 2-dimm support.Vladimir Serbinenko
The check is wrong. On Acer Aspire One it returns 0 despite 2 DIMMs working fine on the same channel if this check is disabled (tested by memtest). On boards that have only 1 DIMM per channel, the code will simply find no SPD and skip empty slot. Change-Id: I5f2fdcd1d948ebf3eabebaea4441af4c19e47f8f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7568 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-05-16Remove defines APMC_FINALIZE.Vladimir Serbinenko
We already have APM_CNT_FINALIZE defined to the same value. Just use it thoughout. Change-Id: Ife94ec7a34da27d3a720bda7337c02e41f18ac72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10226 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-15rk3288: remove unused structs and declarationsAaron Durbin
The struct rockchip_spi_media type is no longer used; nor is initialize_rockchip_spi_cbfs_media(). Remove them. Change-Id: I2c24be249e0cd89e2dd328e05cdd24a178fe37e8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10214 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-15gigabyte/ga-b75m-d3: Fix SMBios version entryKyösti Mälkki
These boards are not ThinkPads. Furthermore, autogenerated build.h might not be generated yet to be included. Change-Id: I084f632d45477abf5e3cb1b734e8048f554423ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10213 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-15x230: Fix ricoh driver.Vladimir Serbinenko
Inclusion of ricoh driver was lost in 1d7b9de3504e90f0886fccec3a1f8a783fd4cc58. So the relevant code wasn't even compiled. Fix copy-paste mistakes without significance while on it as well. Change-Id: Ie548cb43f986f147658fc9c67963f8a055250598 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10211 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-15ibexpeak: Merge common NVS initVladimir Serbinenko
Change-Id: Ia5e26110928fa011305c13362f20fbe78ca9cf30 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7134 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-15spi_flash: document expected return valuesAaron Durbin
The spi_flash API did not have any of its callbacks documented. Do that so that people don't have to go into the guts of an implementation to figure out the proper expectations. Change-Id: I55a0515445cab3697813d88373ee413f30b557b5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10206 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-15console: Bring back newline translationKyösti Mälkki
Change-Id: Ib42f4a9eeb48dfb1a04e332aeb8f83dc4c4eef91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-14superio: Replace the indexed I/O functionsDave Frodin
Replace the multiple indexed I/O read and write functions with common functions. Change-Id: Idfe7a8784c28d51b3fbcb2f4e26beaa0b91741a8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10145 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-14bd82x6x, ibexpeak: Support fully locking ROM on S3 resume.Vladimir Serbinenko
Currently only RO-lock is supported. Make full lock available as an option. Change-Id: Ib68a1e82733a51053a9adc80ac501b6205c6b8a7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10191 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14regions: add mmap helper deviceAaron Durbin
In order to facilitate platforms which need a buffer cache for performing boot device operations provide infrastructure to share the logic in managing the buffer and operations. Change-Id: I45dd9f213029706ff92a3e5a2c9edd5e8b541e27 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-14regions: add memory region device supportAaron Durbin
Provide common code for using memory-backed region devices. This allows in-memory buffers to act as a region device. Change-Id: I266cd07bbfa16a427c2b31c512e7c87b77f47718 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-14coreboot: add memory pool infrastructureAaron Durbin
The memory pool infrastructure provides an allocator with very simple free()ing semantics: only the most recent allocation can be freed from the pool. However, it can be reset and when not used any longer providing the entire region for future allocations. Change-Id: I5ae9ab35bb769d78bbc2866c5ae3b5ce2cdce5fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9129 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-14coreboot: add region infrastructureAaron Durbin
The region infrastructure provides a means of abstracting access to different types of storage such as SPI flash, MMC, or just plain memory. The regions are represented by region devices which can be chained together forming subregions of the larger region. This allows the call sites to be agnostic about the implementations behind the regions. Additionally, this prepares for a cleaner API for CBFS accesses. Change-Id: I803f97567ef0505691a69975c282fde1215ea6da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-14superio/nct5104d: Handle shared GPIO/UART pinsKyösti Mälkki
Routing is decided based on enabled logical/virtual devices. For a valid devicetree, one should have only one of SP3 and GPIO0, and only one of SP4 and GPIO1, enabled at a time in configuration. Change-Id: I02017786aba9dd22d12403aaa71d7641f5bbf997 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14superio/nct5104d: Refactor IRQ trigger configKyösti Mälkki
That function was getting too long. Change-Id: Ic50f210391c2467b65215aa556269b0ba601c2ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10176 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-14lenovo: Disable radio when suspending or turning off.Vladimir Serbinenko
Without this some radios may remain operational. They may consume power but the immediate demonstrable effect is wireless LED still being on. Coreboot will reenable radios on resume or poweron. Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10190 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14x230: Fix VGA PCIIDs.Vladimir Serbinenko
x230 is ivy, not sandy. Fix copy-paste error. Change-Id: Ic462bab39ddac0e1e6fef1e043970957e45fb6ed Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10189 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-13vboot: fix die() hang for recovery pathAaron Durbin
When we are taking the recovery path there is no slot or components to fill out. Change-Id: Ic97a247629365ef54a340c4398cb7491935edc11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10198 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-13amd/pi: Move AGESA cbfs access into the wrapperMarc Jones
The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10058 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13secmon: allow for serial consoleAaron Durbin
Add necessary checks and objects for secmon serial console. Change-Id: Ibafa19061255ef6847a424922565a866328ff34c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10197 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13verstage: provide support for serial consoleAaron Durbin
verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13vboot: indicate verstage loading on consoleAaron Durbin
There was no indication of verstage being loaded. Provide this output so that one can follow the flow from console messages. Change-Id: I67ae6bb334608fe10a4a12fe690498afaf6b8366 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10195 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13console: enumerate all known stagesAaron Durbin
There are more stages than currently handled in the initial message from console_init(). Add support for those including an UNKNOWN catchall. Change-Id: I2374db590072bdca8ff35116e2ecb2ad6459b697 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10194 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13Include back the 306ax microcode again.Vladimir Serbinenko
In ee89435798022021026f511deddf0e3b401ad031 microcode for 306ax was forgotten in migration. Without microcode update my machine experiences random hangs and various misbehaviour. Change-Id: I61c704d88a8a0ed74a16fb3f80cce08e8515e6e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10180 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-05-13cbmem: Add initial allocation supportLee Leahy
Add support to allocate a region just below CBMEM root. This region is reserved for FSP 1.1 to use for its stack and variables. BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: I1d4b36ab366e6f8e036335c56c1756f2dfaab3f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10148 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13x86: expose tsc's timer_monotonic_get() in SMMAaron Durbin
The implementation of timer_monotonic_get() for the tsc module was being guarded from SMM. Allow this to be linked into SMM as the generic spi flash driver now needs this support which can be included in SMM. Change-Id: I3909edecac8de117922c4ea6c53e6e561f6f435b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10187 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13baytrail: broadwell: correct refcode loadingAaron Durbin
I messed up the conditionals on loading the reference code. The bug used || instead of && causing 2 reference codes to be loaded. Change-Id: I29a046bf0e8dc29a9efdb636ebfd04e11eb73f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10185 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13vboot: handle RELOCATABLE_RAMSTAGEAaron Durbin
The support for RELOCATABLE_RAMSTAGE was accidentally omitted in the vboot loader. Add said support. Change-Id: I569918823253c33f698acefd6a619133543c7aef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10184 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-12FSP 1.1 Comparison BaseLee Leahy
Add FSP 1.0 source for comparison with FSP 1.1. BRANCH=none BUG=None TEST=None Change-Id: I8df349f97acfa74f4de3607d49633da3d4884546 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-12usbdebug: Add FTDI FT232H supportKyösti Mälkki
Tested with gizmosphere/gizmo1 Explorer add-on board, which exposes the following device: 0x0403 Future Technology Devices International, Ltd 0x6014 FT232H Single HS USB-UART/FIFO IC For now UART is hard-coded to 115200, 8n1, no flow-control. Change-Id: I4081f84f7700751ccbf079e7fcbb1467aa71d872 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10063 Tested-by: build bot (Jenkins)
2015-05-11vboot: allow for dynamic work buffersAaron Durbin
The vboot library currently relies on link-time known address and sizes of the work buffer. Not all platforms can provide such semantics. Therefore, add an option to use cbmem for the work buffer. This implies such platforms can only do verification of the firmware after main memory has been initialized. Change-Id: If0b0f6b2a187b5c1fb56af08b6cb384a935be096 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: add vb2_working_data_size()Aaron Durbin
Instead of using the symbols directly provide a size function to provide symmetry between getting the work data and size. It also allows for an abstraction where the linker symbols may not be the only source of this information. Change-Id: I4568064a0050d118c3544ab1ea59a08eb0bad8e4 Signed-off-by: Aaron Durbi <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11chromeos: remove vboot_verify_firmware()Aaron Durbin
vboot_verify_firmware() was only defined to ease upstreaming. It was only an empty inline as it is so remove it. Additionally, vboot2 does not require romstage_handoff so there's no need in adding it for the nyan boards. Change-Id: I4d84ac9fb60c756cf10742f26503f7f11af5f57b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: inject vboot loader for stage loadingAaron Durbin
As previously done the vboot loader can be optionally inserted in the stage loading logic in order to decide the source of each stage. This current patch allows for verstage to be loaded and interrogated for the source of all subsequent stages. Additionally, it's also possible to build this logic directly into one of the additional stages. Note that this patch does not allow x86 to work. Change-Id: Iece018f01b220720c2803dc73c60b2c080d637d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10154 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-11imd: don't recover on limit == 0Aaron Durbin
If the limit of the large starting region was set with a NULL pointer then the limit field will be 0. If the limit is zero then no attempt to recover is necessary as there is no region to recover. This prevented an early call cbmem_find() from hanging a rambi device. The config was with vboot enabled and was way before memory init in the sequence. Change-Id: I7163d93c31ecef2c108a6dde0206dc0b6f158b5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10175 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-11vboot2: Use the right set of compiler flags for building vboot librariesPatrick Georgi
This make it pass through -fno-stack-protector, and also uses libverstage fields consistently. verstage is for 'stage' stuff, libverstage for all the vboot logic. Change-Id: I3032e072414bed52effd2dc5057896781ad562c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10174 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-11vboot: allow options to be selected from .configAaron Durbin
In order to allow easier setting of variables without changing mainboards and/or chipset Kconfig files allow the vboot options to be selected by the user. Change-Id: I6e995eb209b4cd63c73ef679d0c5699759d129f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10153 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: fix vboot_reference compilationAaron Durbin
The VB_FIRMWARE_ARCH variable was not being set correctly, and the VBOOT_STARTS_IN_BOOTBLOCK Kconfig option was not properly prefixed with CONFIG_. Correct both of these oversights. Change-Id: Id27974c285d2629bd47b90b6a93aca1ec8a76512 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11chromeos: add missing vboot functionsAaron Durbin
Somewhere along the development path the following vboot functions were dropped: int vboot_enable_developer(void) int vboot_enable_recovery(void) Add them back, but also refactor the flag extraction so as not duplicate all that same logic. Change-Id: Id58f3b99f29caeff98b2d3111cfa28241d15b54f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11arm64: update verstage linkingAaron Durbin
The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Change-Id: Ib8427fe015b72e2282219f116a39949739a0af48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10150 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11arm: update verstage linkingAaron Durbin
The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Lastly, VERSTAGE_LIB has no value so remove it. Change-Id: Ie53b42c4995a96006463ec5b358aa43a731cb1b8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10149 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11cache: Add arch_program_segment_loaded call to arm and arm64Furquan Shaikh
arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. Use this function in rmodules as well instead of cache_sync_instructions which guarantees sync upto PoC. BUG=chrome-os-partner:37546 BRANCH=None TEST=Boots into depthcharge on foster Change-Id: I64c2dd5e40ea59fa31f300174ca0d0aebcf8041d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35ba0b882b86ff2c29ac766e1d65f403c8346247 Original-Change-Id: I964aa09f0cafdaab170606cd4b8f2e027698aee7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260908 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10173 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-11secmon: Add some missing filesPatrick Georgi
secmon is referring to uart's default_baudrate() and various coreboot version strings. Change-Id: I40a8d1979146058409a814d94ea24de83ee4d634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-11nvidia/tegra132: we write tables in ramstagePatrick Georgi
So that's more precise than "anything non-pre-ram". Change-Id: I21db536a5ea704c4b087f57d0b761dd3fdf43e3e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-10AGESA: Drop unused AGESA_MEM_TABLEKyösti Mälkki
These tables are not referenced anywhere, thus all comments about adjustments are void. Also drop stub AgesaReadSpd that is all commented out. Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-08cpu/amd/model_10xxx: Add missing ACPI _PSD objectTimothy Pearson
The ACPI power state generator for AMD 10xxx CPUs did not generate the _PSD object required for reliable PowerNow! operation. Without a correct _PSD object PowerNow! does not know the required core clock relationships, potentially causing unstable system operation. Generate the _PSD object in accordance with the BKDG Rev. 3.62. Change-Id: I255a4837ab29ff1b0874daf189ffb61798645795 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10142 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-08northbridge/intel/gm45/gma: Minor cleanupTimothy Pearson
1.) Removed invalid set of TRANS_STATE_MASK bit 2.) Used i915 register defines to clarify code Change-Id: I08d016e9d66b5eeea8f2174abaa35a98e2b4eca3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08southbridge/i82801gx: Add x_EN defines for LPC_ENDamien Zammit
A few hardcoded values could be fixed after this commit Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-08northbridge/intel/gm45/gma: Add backlight control register fieldTimothy Pearson
This allows the backlight control register to be set via devicetree.cb Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9330 Tested-by: build bot (Jenkins)
2015-05-08fmaptool: Introduce the fmd ("flashmap descriptor") language and compilerSol Boucher
This adds a compiler for a language whose textual representation of flashmap regions will be used to describe the layout of flash chips that contain more than just a single CBFS. Direct integration with cbfstool (via a new command-line switch for the create action) is forthcoming but will be added separately. BUG=chromium:461875 TEST=Use Chromium OS's cros_bundle_firmware script on the fmap.dts file for panther. Using the latter file as a reference, write a corresponding fmap.fmd file and feed it through fmaptool. Run both binary output files though the flashmap project's own flashmap_decode utility. Observe only the expected differences. BRANCH=None Change-Id: I06b32d138dbef0a4e5ed43c81bd31c796fd5d669 Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 005ab67eb594e21489cf31036aedaea87e0c7142 Original-Change-Id: Ia08f28688efdbbfc70c255916b8eb7eb0eb07fb2 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255031 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9942 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-07timestamp: fix incremental linking error for !HAVE_MONOTONIC_TIMERAaron Durbin
In linking ramstage a single object file is created before linking with the linker script. Though there is a weak timestamp_get() symbol in timestamp.c any of its dependent symbols need to be available during the incremental link. As not all platforms have HAVE_MONOTONIC_TIMER enabled this will create a linking error. Fix this by providing a hint to the compiler to remove dead code and thus the dependent symbols causing linking errors in the presence of !HAVE_MONOTONIC_TIMER. Change-Id: Ib8a5dca2c12c2edac7605f403ed91b793823c8a3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10138 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-07kbuild: Use wildcard for driver subdirectoriesStefan Reinauer
Change-Id: Id1685c0b28ec8e3ab972a671af6f2de6f321c645 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-07vboot2: Replace hard coded 'fallback' prefix with Kconfig variablePatrick Georgi
Change-Id: I9cbdf06f4d0956b5374915f8af7501c6f75b4687 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-07imgtec/pistachio: Add comment on the unusual memory layoutPatrick Georgi
To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld. Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-053rdparty/vboot: Add vbootPatrick Georgi
This allows providing a verified boot mechanism in the default distribution, as well as reusing vboot code like its crypto primitives for reasonably secure checksums over CBFS files. Change-Id: I729b249776b2bf7aa4b2f69bb18ec655b9b08d90 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05sandy/ivy boards: Rename defines from onboard.h for ACPIKyösti Mälkki
Adopted style from later Chromebooks. Change-Id: I4993b8f40489b6bf5d08e00089f36f293853629e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/9992 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-05arch/arm64: provide boot_cpu()Aaron Durbin
Change-Id: I708041133dfafdc97e052952ad9d8f2e4164209c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10105 Tested-by: build bot (Jenkins)
2015-05-05timestamp: provide weak default implementation of timestamp_getAaron Durbin
Change-Id: I2e7f17a686f6af3426c9d68cd9394e9a88dbf358 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-05vboot: add cbfs_coreAaron Durbin
And we don't support lzma compressed data in verstage. Change-Id: I3d8d3290f147871c49e9440e9b54bbf2742aaa9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10103 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 18:15:35 +0000