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2023-07-12cpu/intel/microcode: Drop unnecessary alignment for split microcodeSubrata Banik
This patch drops the unnecessary alignment of 64 bytes that was introduced when implementing the split Intel microcode packing logic into CBFS. - The 16-byte alignment that is already used for Intel microcode is sufficient. - Removes unnecessary alignment check of 64 bytes against an AMD platform specific config. TEST=Able to build and boot google/rex without any functional impact. Change-Id: Icc44e9511e321592de7ab8d1346103d0a9951c9b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76397 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-11soc/intel/xeon_sp: Clear reserved field in SRATNaresh Solanki
During the ACPI dump of the System Resource Affinity Table (SRAT), it was noticed that the reserved field within the Memory Affinity structure contained a non-zero value. This commit addresses the issue by performing a memset to zero on the reserved field, ensuring the avoidance of any potential problems arising from garbage values. TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries reserved fields read zeroes Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-11mb/google/rex: LZ4 compress ramstage instead of LZMAWonkyu Kim
for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB. For detail, refer below. Existing: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact (73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/rex/var/ovis: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi to function properly with the connected bluetooth devices and wake up from low power state. BUG=None TEST=None Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
2023-07-11mb/google/rex/var/rex0: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=None TEST=Make rex platform suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex/var/rex0: Reduce camera NVM size to 8KBJamie Ryu
The actual NVM size of camera module is 64KB; however, only 8KB is in use to store data. This reduces the size of both NVM0 and NVM1 to 8KB to minimize the time taken to read NVM and launch Camera preview. BUG=NONE TEST=Launch Chrome camera application and check the time taken to read eeprom from camera service log and show camera preview. It takes 2 to 3 seconds to show camera preview while it takes 4 to 5 seconds without the changes. Before the changes: 06:21:04.204944Z OpenDevice(): camera_id = 1 06:21:07.297584Z Read camera eeprom from eeprom 06:21:08.763491Z Read camera eeprom from nvmem After the changes: 21:37:23.923676Z OpenDevice(): camera_id = 1 21:37:24.386020Z Read camera eeprom from eeprom 21:37:24.574515Z Read camera eeprom from nvmem Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189 Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/nissa/var/gothrax: Update eMMC DLL tuning valuesSimon Yang
Update eMMC DLL tuning values for improved initialization reliability BUG=b:289763421 TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston eMMC Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10nb/amd/pi/00730F01: Specify supported memory typeElyes Haouas
Change-Id: Iccaeb685ba66112b9e05ed72b57eb840543d7c6a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-10mb/google/rex/var/ovis: Enable both Memory Channels (MC0 and MC1)Subrata Banik
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine the memory channel configuration. The signal behavior is not proper, hence limiting the DIMM capacity to half (only MC0 is enabled). This patch always reports the full memory capacity as in dual channel (both MC0 and MC1 enabled). This change is necessary to ensure that the system reports the correct memory capacity, even if the MEM_CH_SEL GPIO is not working properly. BUG=b:290174538 TEST=Able to detect 32GB memory capacity while booting google/ovis. Without this patch: localhost ~ # cat /proc/meminfo MemTotal: 16183080 kB With this patch: localhost ~ # cat /proc/meminfo   MemTotal: 32673664 kB Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/brya/var/redrix: Use just single GFX entryWon Chung
Since multiple GFX entry causes an ACPI error when trying to write _DOD method multiple times, combine the GFX entry into one so that _DOD method is written just once. BUG=b:289854155 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-10mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edgeEran Mitrani
This CL corrects the trigger for HID over SPI from Level to Edge. BUG:None TEST:Tested with I2C and SPI Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/corsola: Add support for AW37503 Power ICRuihai Zhou
The AW37503 is designed to supply positive/negative supply for driving the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we need to program the registers at boot. We program the target positive/negative output voltage via I2C and enable the power rails by pulling up ENP and ENN pins. On Starmie, we need +/-6V power supply for the MIPI panel. We program the AW37503 registers in coreboot so that kernel can control AW37503 via fixed regulators without additional settings(what we did for TPS65132). Since we distinguish AW37503 and TPS65132 by reading the vendor ID, we need to initialize I2C bus as early as possible. Therefore, we move mtk_i2c_bus_init() to mainboard_init(). BUG=b:289482828 TEST=emerge-staryu coreboot chromeos-bootimage TEST=Test the sequence the voltage Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/corsola: Add new board 'ponyta'cengjianeng
Add a new kingler follower 'ponyta'. BUG=b:290259648 TEST=make # select ponyta Signed-off-by: cengjianeng <cengjianeng@huaqin.corp-partner.google.com> Change-Id: I74759441957e9901bd7e5a709a2ae7d97a7cd040 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76331 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2023-07-10mb/google/brya/var/brya: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74407 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/brya/var/skolas: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-10mb/google/brya: put Bluetooth VPGIOs overridableMac Chiang
The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here. Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten. The fix included crota and omnigul BT offload work successfully. BUG=b:264834572 TEST=test Bluetooth offload playback/capture in SCO profile. Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69 Signed-off-by: Mac Chiang <mac.chiang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-10vboot: Fix S3 resume with stage_cacheKyösti Mälkki
In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not get called when postcar was loaded from TSEG stage cache on ACPI S3 resume path. Resume failed as MP init attempts to access microcode update from unverified FW_MAIN_A/B section. In a similar fashion, for POSTCAR=n, loading ramstage from TSEG stage cache would bypass the call to vboot_run_logic(). TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able to complete S3 resume. Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-10mb/google/brya/var/kuldax: Add fw_config and configurate AUX pinDavid Wu
Add fw_config and configurate AUX pin for MB USB Type-C. MB USB3 doesn't have re-timer, thus have to configurate the AUX pin. BUG=b:275335023 TEST=build pass Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2023-07-08allocator_v4: Disable top-down allocation for EDK2Nico Huber
EDK2 seems to have problems at least with the resource allocation for Intel's IGD. While the investigation is ongoing, disable top-down allocation by default if the payload is known to be EDK2. Change-Id: I771d8a3b74b54a043624843a00498225d1f509ad Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76373 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-08cpu/x86/lapic: Fix regression with X2APIC_LATE_WORKAROUNDKyösti Mälkki
This patch fixes the boot hang due to commit 053a45bcdb3ccf8 ("cpu/x86/lapic: Fix X2APIC_ONLY regression") on platform which selects X2APIC_LATE_WORKAROUND config. [EMERG] Switching from X2APIC to XAPIC mode is not implemented. Without this patch: Boot gets stuck inside at BS_WRITE_TABLES when enable_lapic() gets called after X2APIC mode has been enabled. The fix is to change enable_lapic() to track when late enablement for X2APIC mode happens with X2APIC_LATE_WORKAROUND. TEST=Able to build and boot google/rex to chromeos. Change-Id: I41e72380e9cfb59721d0df607ad875d7b6546974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76384 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-08cpu: Enable per-CPUID microcode loading in CBFSSubrata Banik
The current design of the `ucode-<variant>.bin` file combines all possible microcode per cpuid into a unified blob. This model increases the microcode loading time from RW CBFS due to higher CBFS verification time (the bigger the CBFS binary the longer the verification takes). This patch creates a provision to pack individual microcodes (per CPUID) into the CBFS (RO and RWs). Implementation logic introduces CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config which relies on converting Intel CPU microcode INC file into the binary file as per format specified as in `cpu_microcode_$(CPUID).bin`. For example: Intel CPU microcode `m506e3.inc` to convert into `cpu_microcode_506e3.bin` binary file for coreboot to integrate if CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled. Another config named CPU_INTEL_UCODE_SPLIT_BINARIES is used to specify the directory name (including path) that holds the split microcode binary files per CPUID for each coreboot variants. For example: if google/kunimitsu had built with Intel SkyLake processor with CPUID `506e3` and `506e4` then CPU_INTEL_UCODE_SPLIT_BINARIES refers to the directory path that holds the split microcode binary files aka cpu_microcode_506e3.bin and cpu_microcode_506e4.bin. Refer to the file representation below: |---3rdparty | |--- blobs | | |--- mainboard | | | |--- google | | | | |--- kunimitsu | | | | | |--- microcode_inputs | | | | | | |--- kunimitsu | | | | | | | |--- cpu_microcode_506e3.bin | | | | | | | |--- cpu_microcode_506e4.bin Users of this config option requires to manually place the microcode binary files per CPUIDs as per the given format (`cpu_microcode_$(CPUID).bin`) in a directory. Finally specify the microcode binary directory path using CPU_UCODE_SPLIT_BINARIES config. Additionally, modified the `find_cbfs_microcode()` logic to search microcode from CBFS by CPUID. This change will improve the microcode verification time from the CBFS, and will make it easier to update individual microcodes. BUG=b:242473942 TEST=emerge-rex sys-firmware/mtl-ucode-firmware-private coreboot-private-files-baseboard-rex coreboot Able to optimize ~10ms of boot time while loading microcode using below configuration. CONFIG_CPU_MICROCODE_CBFS_SPLIT_BINS=y CONFIG_CPU_UCODE_SPLIT_BINARIES="3rdparty/blobs/mainboard/ $(CONFIG_MAINBOARD_DIR)/microcode_inputs" Without this patch: 10:start of ramstage 1,005,139 (44) 971:loading FSP-S 1,026,619 (21,479) > RO/RW-A/RW-B CBFS contains unified cpu_microcode_blob.bin Name Offset Type Size Comp ... cpu_microcode_blob.bin 0x1f740 microcode 273408 none intel_fit 0x623c0 intel_fit 80 none ... ... bootblock 0x3ee200 bootblock 32192 none With this patch: 10:start of ramstage 997,495 (43) 971:loading FSP-S 1,010,148 (12,653) > RO/RW-A/B CBFS that stores split microcode files per CPUID FMAP REGION: FW_MAIN_A Name Offset Type Size Comp fallback/romstage 0x0 stage 127632 none cpu_microcode_a06a1.bin 0x1f340 microcode 137216 none cpu_microcode_a06a2.bin 0x40bc0 microcode 136192 none ... ... ecrw 0x181280 raw 327680 none fallback/payload 0x1d1300 simple elf 127443 none At reset, able to load the correct microcode using FIT table (RO CBFS) [NOTE ] coreboot-coreboot-unknown.9999.3ad3153 Sat May 20 12:29:19 UTC 2023 x86_32 bootblock starting (log level: 8)... [DEBUG] CPU: Genuine Intel(R) 0000 [DEBUG] CPU: ID a06a1, MeteorLake A0, ucode: 00000016 Able to find `cpu_microcode_a06a1.bin` on google/rex with ES1 CPU stepping (w/ CPUID 0xA06A1) (from RW CBFS) localhost ~ # cbmem -c -1 | grep microcode [DEBUG] microcode: sig=0xa06a1 pf=0x80 revision=0x16 [INFO ] CBFS: Found 'cpu_microcode_a06a1.bin' @0x407c0 size 0x21800 in mcache @0x75c0d0e0 [INFO ] microcode: Update skipped, already up-to-date Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-08cpu/intel/microcode: Avoid Pre-RAM microcode update if FIT enableSubrata Banik
This patch changes the default behaviour of the MICROCODE_UPDATE_PRE_RAM config for the platform with FIT (CPU_INTEL_FIRMWARE_INTERFACE_TABLE) enabled. If FIT is enabled then microcode update will be taken care of by FIT at pre-cpu reset hence, microcode update at pre-ram phase can be skipped. BUG=b:242473942 TEST=Able to build and boot google/rex with MICROCODE_UPDATE_PRE_RAM remains disabled. No functional impact. Without this patch: CONFIG_MICROCODE_UPDATE_PRE_RAM=y With this patch: CONFIG_MICROCODE_UPDATE_PRE_RAM is not set Change-Id: I603e064115869aba2bffa5589ffe47a44a90b848 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-07-07mb/google/skyrim/var/crystaldrift: Override SPI flash bus speedYunlong Jia
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:270500631 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0915d9b10dbfae7fff4e8874011951d1690de870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-07-07soc/amd/*/globalnvs,nvs: remove deprecated & unused CBMC field from GNVSFelix Held
Commit cde4f3b2790d ("acpi/gnvs.c: Drop unused pointer to the cbmem console") removed writing the coreboot memory console pointer to the GNVS and kept the CBMC field as reserved. Since those fields aren't needed any more and there are no dependencies on the absolute position of the different fields in GNVS as long as both GNVS definitions on the C and the ASL side match, remove the deprecated and unused CBMC field from the GNVS structs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iadfaf5a4ec1401b027dbfb6a7c6ce74a1dcecdfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/76351 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-07lib: Adjust the log levels in ux_locales.cHsuan Ting Chen
The function ux_locales_get_text() should expect to have a correct preram_locales region to read, hence we need to adjust the log levels inside lib/ux_locales.c:ux_locales_get_text(): * If the region does not exist or is not in a correct format, we should print in BIOS_ERR * If the arguments are not correct but we have a good workaround (e.g. the lang_id from vboot API seems weird), we should print in BIOS_WARNING. Also change some minor syntax issues. BUG=b:264666392, b:289995591 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic8a8856c883f6ca78fed69542a7d388f57c5c508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76316 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-07soc/intel/xeon_sp/spr: Fix upd_display.c build errorJohnny Lin
Fix below build error after DISPLAY_UPD_DATA is selected: src/soc/intel/xeon_sp/spr/upd_display.c:131:29: error: variable 'old' set but not used [-Werror=unused-but-set-variable] 131 | const FSP_S_CONFIG *old; | ^~~ src/soc/intel/xeon_sp/spr/upd_display.c:130:29: error: variable 'new' set but not used [-Werror=unused-but-set-variable] 130 | const FSP_S_CONFIG *new; Change-Id: I43ed5fadab58e0d4dc824457c7a1bdf48511198e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76342 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-07drivers/intel/fsp2_0: Remove BUILD_TIME_STAMP_SIZE macroRonak Kanabar
Remove BUILD_TIME_STAMP_SIZE macro from coreboot because FSP 3223 version have BUILD_TIME_STAMP_SIZE macro defined as part of `FspProducerDataHeader.h`. Ref change: 9c28ab1d1a vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80 BUG=b:285110116 TEST=Able to build google/rex. Change-Id: I52707adf1aa6dadca8dcf82102f76916a0cfe346 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-07soc/amd/*/Makefile.inc: Use _tohex instead of printfFred Reitberger
Use the _tohex function to convert values to hex instead of 'shell printf' TEST=timeless builds identical for grunt,dalboz,guybrush,chausie,birman Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic7f7d1b764479088cc0980b208d8d603bc712832 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76314 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-07mb/google/brya/var/constitution: Update overridetreeMorris Hsu
constitution only has one TBT port, remove tcss_dma1. BUG=None TEST=emerge-constitution coreboot Change-Id: Ia4eb4371eb20e75a0f464e2b087fd2fe59569537 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com>
2023-07-06util/apcb: Add apcb edit tool for phoenixRob Barnes
Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into an APCB for phoenix platform. The tool makes several assumptions: * Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero. * Each block is 64 bytes. * Dimm and socket are always 0 * Unused SPD entries are zero'd BUG=b:281983434 BRANCH=None TEST=build, flash, boot myst Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-06acpi/acpi.c: Fix regression with DSDTKyösti Mälkki
Fix regression introduced with commit 01af0f8ac803 ("acpi/acpi.c: Reduce boilerplate"). DSDT table is not to be listed within RSDT/XSDT, ACPICA and/or OSPM may try load it twice raising conflicts in the namespace and effectively ignoring all or most of the AML. Change-Id: I0e6d07b35522f2bf9a51cef0a7e3181b15087d88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-06mb/amd/birman/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODEFred Reitberger
Always exit 4-byte addressing mode to prevent errors when the spi flash is not left in 4-byte addressing mode. TEST=boot with PSP releases that leave the flash in both 4-byte and 3-byte mode and verify flash writes Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9884b85bc3b0a9b654a2cb91fb314b0869abd622 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76094 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06mb/siemens/mc_ehl4: Make DRAM population depending on GPIO GPP_B5Mario Scheithauer
GPIO GPP_B5 is used as input on this mainboard. For a full-populated DRAM configuration, the input signal is connected to ground and for a half-populated configuration it is connected to 3.3 V. BUG=none TEST=Use different HW configurations and check coreboot log GPP_B5 = 0: [DEBUG] 2 DIMMs found GPP_B5 = 1: [INFO ] meminit_channels: DRAM half-populated [DEBUG] 1 DIMMs found Change-Id: I48b4a3bea7f1ff804b78b7c648a7ea1925627b8a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76245 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mb/siemens/mc_ehl: Make DRAM population configurableMario Scheithauer
There can be mainboard variants, which are only equipped with half-populated DRAM. For this reason, the meminit parameter for populatation should be adjustable. The default setting remains at full-populated DRAM. At mainboard variant level a different selection via individual input paths can be made. Change-Id: I390bbfa680b5505bb2230fa0740720bd9dd1fafb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76244 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06emulation/qemu-q35: Enable ECAM earlierKyösti Mälkki
Align implementation with real hardwares, such that ECAM (PCI configuration via MMIO) is available for use when console is initialised. Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-07-06cpu/x86: Add some notes about XAPIC/X2APICKyösti Mälkki
At the time of writing SMM runtime does not make register accesses to LAPIC registers, but such breakage has been reported. S3 resume failure, where OS switched back from X2APIC to XAPIC mode, can be reproduced with a sandybridge SKU that has VT-d disabled. Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-06cpu/x86/lapic: Fix X2APIC_ONLY regressionKyösti Mälkki
Some ancient CPUs may have had LAPIC disabled at power-up, so semantically enable_lapic() should always come before attempting to access the register banks. With X2APIC_ONLY option it is necessary to ensure enable_lapic() is called prior to any other lapic register space accesses, since the XAPIC mode MMIO accessors are optimised away build-time and CPU's do not yet initialise for X2APIC mode at reset. Change-Id: I96eaa5c43108c802375e184e0c68b5091ca0198f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76195 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-06emulation/{i440fx,q35}: Don't use PCI driver to set root PCI dev opsArthur Heymans
This devices is always present so hooking up the ops in devicetree makes more sense. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I369129e365ce8596cad25b97d12168bb08e3ed0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76241 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mainboard/starlabs/*: Remove the power_on_after_fail optionSean Rhodes
None of these boards have an RTC battery, so this option has no effect. Remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mainboard/starlabs/starbook: Unselect RESIZABLE_BARSSean Rhodes
It is not needed, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-06vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75916 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mb/google/brya/var/mithrax: Generate SPD ID for supported partsJohn Su
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL (Samsung) 2. K4UBE3D4AB-MGCL (Samsung) BUG=b:289873670 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7a262ac62c24cfb43c0283c9730c177a242342e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76240 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05soc/amd/phoenix/Makefile.inc: Refactor repeated lines to a variableFred Reitberger
Rather than repeat the same line multiple times, save it in a variable once and use that variable in the rest of the file. TEST=timeless birman build identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4eb262adb3bbda04add79b2e2b8bee9a609a1e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76197 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offsetFred Reitberger
Pass the APOB NV address as a flash offset instead of x86 address. TEST=boot birman and verify APOB_NV is working Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76162 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05arch/x86: Ensure LAPIC mode for exception handlerKyösti Mälkki
Attempting to use X2APIC MSRs before the call to enable_lapic() is made raises exception and double-faults. Change-Id: Ib97889466af0fbe639bec2be730784acc015b525 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-05soc/intel/alderlake: Increase default CBFS size to 4MBFelix Singer
Updating some submodule pointers to their latest commit causes some builds with default configuration to fail since all required components don't fit into 2MB anymore. Specifically, this has been experienced with the microcode and FSP submodules. So, increase the default CBFS size to 4MB to make sure builds succeed with updated submodules. Change-Id: I2fc16240bef36c057608acadf3cb7c65e7f0d244 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-05mb/protectli/vault_ehl: Set DIMM_MAX to 1Michał Żygowski
VP2420 (vault_ehl) has only 1 DIMM slot present. Set the DIMM_MAX to 1 to optimize the common libraries to not attempt to read and parse more SPD than needed. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory properly and fastboot is working. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I29a99f387ffe2df1060547e0818c5c5b66a27061 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05soc/intel/meteorlake: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05mb/google/rex/var/screebo: Update touchpad I2C timingZhongtian Wu
Change i2c[3] parameter to meet below timing: t-HIGH > 600ns; 900ns > Thd:dat > 300ns. BUG=b:286030723 BRANCH=none TEST=Test success by EE. Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05mb/google/rex/var/ovis: Set TCC to 100°CSubrata Banik
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for ovis. BUG=b:270664854 TEST=Build and boot google/ovis. Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05soc/intel/meteorlake: add power limits for 28W SKUSumeet Pawnikar
Add power limit values for Meteor Lake 28W SKU. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I0b4741185278913d11d902d53345ae8ccebb18f8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76239 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05soc/intel/meteoerlake: add support for 28W SKUSumeet Pawnikar
Add power limits support for 28W SKU. BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I83deb1e574990cb70f9aac5d5eb46fbb710a6170 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76238 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05mb/google/rex/var/ovis: Add Power Limit for 28WSubrata Banik
This patch adds a power limit for Ovis with 28W Intel Meteor Lake silicon. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BUG=b:289854108 TEST=Able to boot google/ovis with power limit being overridden as appropriate to 28W. Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-05mb/google/rex: Temporarily disable the crashlogKapil Porwal
Currently, boards with ES2 silicon are unable to boot with crashlog enabled because crashlog driver is unable to handle invalid data. Temporarily disable the crashlog to unblock development until the issue is fixed. BUG=b:289749310 TEST=Able to boot to the OS on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-07-05mb/google/rex/var/screebo: Update touchscreen I2C timingZhongtian Wu
Change i2c[0] parameter to meet touchscreen timing. Thd:dat > 100ns. BUG=b:287898252 BRANCH=none TEST=Test success by EE. Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-04soc/amd/common/block/acpi/ivrs: use IOMMU PCI register definitionsFelix Held
Use IOMMU_CAP_BASE_[LO,HI] instead of magic values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7032d9f032a22649951ef1535f39b918eb8bd539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-04soc/amd/common/block/iommu: factor out PCI register definitionsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie155cab1f659e9f7b64cd87ba8a77260056656d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76222 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04util/cbmem: add parsing of TPM logs per specsSergii Dmytruk
CBMEM can contain log in different forms (at most one is present): - coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as LB_TAG_TPM_CB_LOG) - TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG) - TPM2 format (CBMEM_ID_TPM2_TCG_LOG) The last two follow specifications by Trusted Computing Group, but until now cbmem couldn't print them. These formats were added not so long ago in: - commit 4191dbf0c9a5 ("security/tpm: add TPM log format as per 1.2 spec") - commit 53db677586e3 ("security/tpm: add TPM log format as per 2.0 spec") These changes make cbmem utility check for existence of TPM1.2/TPM2 logs in CBMEM and add code necessary for parsing and printing of their entries. TEST=`cbmem -L` for CONFIG_TPM1=y case TCPA log: Specification: 1.21 Platform class: PC Client TCPA log entry 1: PCR: 2 Event type: Action Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e Event data: FMAP: FMAP TEST=`cbmem -L` for CONFIG_TPM2=y case TPM2 log: Specification: 2.00 Platform class: PC Client TPM2 log entry 1: PCR: 2 Event type: Action Digests: SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c Event data: FMAP: FMAP Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c Ticket: https://ticket.coreboot.org/issues/425 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04arch/arm64/Makefile.inc: Fix Kconfig name in commentYu-Ping Wu
Change-Id: I93860a20a425c833b41e16347722e9a879f83ab1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-04mb/google/rex: Enable Bluetooth offload for soundwire audioUday M Bhat
This patch enables BT offload feature for soundwire audio over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=build and verify BT offload on rex soundwire audio Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-04mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offsetDtrain Hsu
Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to modify DPTF parameters and tcc_offset. - Set tcc_offset to 3. - Update Critical Policy trip point. - Update Power Limits PL1 minimum step size to control limits (in mW). BUG=b:282598257 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and pass thermal test. Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-04mb/google/nissa/var/joxer: Disable external fivrMark Hsieh
In next phase, joxer will remove external fivr. BUG=b:285477026 TEST=emerge-nissa coreboot and boot to OS, suspend/resume work normally. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I7fd7ad90e1544966170df402243604379f5790db Reviewed-on: https://review.coreboot.org/c/coreboot/+/76187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-04soc/amd/common/block/uart: remove DRIVERS_UART_8250MEMEric Lai
Select DRIVERS_UART_8250MEM_32 will select DRIVERS_UART_8250MEM too. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I87a47e2d76ab7a0717edf725bf94d87f9f2357f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76184 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-07-03acpi/acpi.c: Move ACPI header creation to a functionArthur Heymans
This reduces boilerplate. One functional difference is that SSDT no longer has oem_revision set to 42. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-03acpi/acpi.c: Reduce boilerplateArthur Heymans
Adding tables to R/XSDT, aligning current pointer, computing checksum is a lot of boilerplate that needs to be done for each table. TESTED on foxconn/g41. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-03soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATIONFred Reitberger
Phoenix is an x86 soc that supports sha256 instructions. TEST=boot birman to chromeos Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id228399ba02708b97110d524ce12c2626588762d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76166 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-03soc/amd/phoenix: Remove TODO after reviewFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ifd2b53ff24776238190eb946db7b12827fcfc804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-03drivers/spi_flash: Always exit 4-byte address mode when memory-mappedFred Reitberger
Always send the Exit 4-Byte Address Mode (E9h) command before the first access to the SPI flash in all stages when the SPI flash is memory-mapped. This is useful for x86 mainboards that do not access SPI flash in bootblock yet still need to exit 4-byte addressing mode in romstage or ramstage. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-03cpu/x86: Reduce scope of MTRR functions used locallyKyösti Mälkki
Change-Id: Ic00358ee5b05d011a95d85ec355adef71c39a529 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76193 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/{adl,tgl}: Add FMD filesTim Crawford
Replace `CBFS_SIZE` with FMD files to declare regions and sizes. This will be used to lock BIOS region (except SMMSTORE) on boot. `CBFS_SIZE` was incorrectly set to 10 MiB, so this also corrects the BIOS region size to match the FIT values. Change-Id: I0f068f4d9b376f12b46faa5bb0c6a08e6cb744d8 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76155 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Add space for ramtop in CMOS layoutTim Crawford
Fixes building when `USE_OPTION_TABLE` is selected. Change-Id: I4fb017aa549b24eda6b9e0356bc1776d4044c95d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Select CBFS SMBIOS hooksTim Crawford
Multiple users have requested to have the DMI values for product UUID and serial number be populated. Enable the drivers so that we may set them when flashing or updating firmware. Change-Id: I710363d9df626d51756a265f0099f26ef28411c2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Select TPM read delay on all boardsTim Crawford
The Infineon chip occasionally fails Startup or Resume. Adding the delay makes it work more reliably. Change-Id: I4a8f98633154888e2167a3d55192b86e13ffcb62 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76095 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/adl: Remove PL4 valuesTim Crawford
System76 EC since system76/ec@99dfbeaec3b8 sets PL4 values through PECI based on AC state for all boards. Remove the static PL4 values from coreboot since they won't be used. Ref: https://github.com/system76/ec/pull/353 Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03ec/system76/ec: Do not call reset on wakeTim Crawford
Resetting the device will cause the keyboard backlight and airplane LED to lose their state. Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/rpl: Add Oryx Pro 11 as a variantJeremy Soller
The Oryx Pro 11 (oryp11) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots - Both M.2 NVMe SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Change-Id: I0d29e03cdde523a95ae6d174a9948f4c119cca6e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/tgl-u: Enable reporting CPU C10 state over eSPIJeremy Soller
This allows the EC to detect C10 using eSPI instead of a dedicated pin. Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/adl: Add Gazelle 17 as a variantJeremy Soller
The gaze17 comes in 2 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet Controller - NVIDIA RTX 3060, using onboard I219-V Ethernet Controller Tested with a custom TianoCore UefiPayloadPkg payload. Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - MicroSD card reader - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting to Pop!_OS Linux 22.04 with kernel 6.2.6 - Internal flashing with flashrom v1.2-703-g76118a7c10ed Not working: - Discrete/Hybrid graphics: Requires NVIDIA driver - mDP/HDMI displays on 3060 variant: Requires NVIDIA driver - Detection of devices in TBT slot on boot - S3 suspend: MP init eventually fails Not tested: - Thunderbolt devices Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76/tgl-h: Disable D3coldTim Crawford
Disable D3cold to prevent issues with Thunderbolt not working after S3 suspend. Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03soc/amd/*: Utilize get_fmap_value() Makefile function where possibleMatt DeVillier
Replace: $(shell awk '$$2 == "xyz" {print $$3}' $(obj)/fmap_config.h) with: $(call get_fmap_value,xyz) to improve code readability/maintainability. Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76168 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-03Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cseMatt DeVillier
Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5Leo Chou
Update SX9324 register settings based on tuning value from SEMTECH. BUG=b:279510275 TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0Jan Samek
It's been decided not to use any of the USB 3.0 ports on this board. This patch disables the remaining USB 3.0 port 0, after the port 1 has already been disabled in commit d0627c7595fe ("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1"). BUG=none TEST=None of the USB 3.0 ports functional anymore after boot, the USB 2.0 ports continue working. Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/siemens/mc_apl1: Fix wrong register maskingMario Scheithauer
With the previous instruction the complete register was set to '0'. Correctly, only the bits 23:16 must be masked. Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-07-03mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0Mario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. The appropriate value of 0.7 V was determined by using an oscilloscope. Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-03mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'Mario Scheithauer
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3 refers to SATA port 1 only. To make this clear, change the name of the define from 'TX_DWORD3' to 'TX_DWORD3_P1'. Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-07-03mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macroMario Scheithauer
A correction of Tx signal from SATA interface is not necessary on these boards currently. Therefore remove the define and the corresponding code on mc_apl5. Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-03mb/google/nissa/var/joxer: support for different WiFi SAR tablesMark Hsieh
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table. BUG=b:285477026 TEST=emerge-nissa coreboot and check the SAR value Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/nissa/yaviks: Tune eMMC DLL value for boot issueChia-Ling Hou
Resolve boot issue by tuning RX HS50 and HS200. BUG=b:265611305 TEST=Reboot test 2500 times pass Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62 Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75812 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
2023-07-03mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:283245785 BRANCH=firmware-grunt-11031.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-03mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the kb8010 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The kb8010 retimer does not support this feature, so let the SoC do the flip. BUG=b:267589112 TEST=verified DP-ALT mode works in both cable orientations on rex with reworked kb8010 DB by flykt@ Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-03mb/google/kahlee: Enable Secure OSJon Murphy
Secure OS was disabled on Grunt devices since it isn't used. This reduces the attack surface and is meant to mitigate potential security risks. However, this prevents users from using an alternate OS. Enable Secure OS upstream to allows users to use Windows, and ensure that it is still disabled in the chromium repo. BUG=b:287630343 TEST=Builds with Secure OS included. Cq-Depend: chromium:4620881 Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-03mb/hp: Add new port for compaq_8300_elite_usdtRiku Viitanen
New port based on autoport. Autoport worked with minor tweaks, but fan speeds went almost immediately to the maximum. They are controlled by the NPCD379 Super I/O which isn't supported by coreboot. But coreboot already has code for NPCD378, which HP Compaq 8200 SFF makes use of. So SuperIO configuration was copied from the 8200 SFF port. It seems to work without any issues in "normal" use. Most importantly, fan speed control seems to work correctly. However this means that some of the SuperIO LDNs may be configured incorrectly. See the comments on Gerrit for more information. The following is tested and is working: * Native raminit with both DIMMs * Libgfxinit textmode and framebuffer on both DisplayPorts and VGA * External USB2 and USB3 ports: they all work * USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports) * Ethernet * Mini-PCIe WLAN * SATA: 2.5" SSD and optical drive bay * Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1 * GRUB (with Libreboot config) * PS/2 keyboard and mouse * S3 suspend and resume, wake using USB keyboard * Headphone output, line out, internal speaker * Wake on LAN * Rebooting * CMOS options & nvramcui Untested: * mSATA slot. The SATA port needs to be enabled on devicetree too, but I'm unable to test due to lack of hardware * Line in, mic input * MXM graphics card * EHCI debug Not working: * Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so maybe it just isn't present * PS/2 keyboard wake from S3 Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/dedede/var/taranza: Add more USB configurationSheng-Liang Pan
- remove usb2_ports[5] since taranza doesn't have PL2303. - add usb2_ports[6] and usb3_ports[1] for Type-A Port A4. BUG=b:288094807, b:278167978 TEST=emerge-dedede coreboot chromeos-bootimage verified all the USB port works Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7b411c21271497ba386143140aa8cfbb17a1a111 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76186 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Enable LAN0Subrata Banik
This patch performs below operations to enable LAN0. - Complete the LAN PEREST power sequencing - Program the SRC_CLKREQ (GPP_D20) with correctly. - Add overridetree.cb entry to configure the LAN0 device. BUG=b:289395519 TEST=Able to boot google/ovis with LAN0 being enabled. Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Enable LAN1Subrata Banik
This patch performs below operations to enable LAN1. - Add overridetree.cb entry to configure the LAN device. - Complete the LAN1/SD PEREST power sequencing BUG=b:289395519 TEST=Able to boot google/ovis with LAN1 being enabled. Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_V12 PADSubrata Banik
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the Ovis schematics dated June'23 to ensure LAN port is not in sleep. BUG=b:289395519 TEST=Able to measure SLP_LAN PIN and confirm it's deasserted. Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_C10 PADSubrata Banik
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis schematics dated June'23 to ensure LAN ports having power. BUG=b:289395519 TEST=Able to measure LAN port power is enabled with this CL. Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 03:00:34 +0000