summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2022-03-14mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytesWerner Zeh
DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14soc/intel/common: Use generic enum type valuesSridhar Siricilla
The patch uses generic enum type values for EOP command handler. So, it renames cse_eop_result enum type to cse_cmd_result and also renames the enum values to have generic name. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14soc/intel/common: Use heci_reset() in the CSE TX and RX flowsSridhar Siricilla
The patch implements error handling as per the ME BWG guide. The BWG recommends HECI interface reset if there is a timeout or malformed response is received from the CSE. Also, the patch triggers HECI interface reset if the CSE link state is not ready in the heci_send() API. TEST=Verify HECI Interface reset in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14soc/intel/common: Implement error codes for for heci_send_receive()Sridhar Siricilla
The patch implements below changes: 1. Implements different error codes and use them in appropriate failure scenarios of below functions: a. heci_send() b. recv_one_message() c. heci_receive() 2. As heci_send_receive() is updated to return appropriate error codes in different error scenarios of sending and receiving the HECI commands. As the function is updated to return 0 when success, and non-zero values in the failure scenarios, so all caller function have been updated. BUG=b:220652101 TEST=Verified CSE RX and TX APIs return error codes appropriately in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/brya/var/kinox: update overridetreeDtrain Hsu
1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. BUG=b:218786363, b:214025396, b:212183045 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCKRaul E Rangel
The verstage.c file contains PSP verstage specific code. We don't need it when using x86 verstage. BUG=b:193050286 TEST=Build and boot guybrush with x86 verstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/google/brya: Set EPP to 45% for all Brya variantsCliff Huang
This sets EPP value to be 45% for all Brya variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. BUG=b:219785001 BRANCH=firmware-brya-14505.B TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14soc/intel/alderlake: Add EPP override supportCliff Huang
This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/dedede: Update DPTF settingTeddy Shih
Update PL1, PL2, and temperature sensor values from thermal team, as well as, we remove unused temperature sensors according to baseboard/devicetree.cb and mainboard schematic. After we check DTT setting, the thermal and performance test pass. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, run following commands: localhost /tmp # cat /sys/class/thermal/thermal_zone*/type x86_pkg_temp INT3400 Thermal TSR0 TSR1 TCPU localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp 45000 20000 32800 32800 39000 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2Felix Held
The one USB2 port on the XHCI2 controller should have the port ID 2.0, since it's the first USB2 port on that XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devicesFelix Held
GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/google/nissa/var/nivviks: Hook up SD host controller GL9750Eric Lai
Select GL9750 driver and add power sequence according to datasheet: GL9750S-OIY04 rev1.22. BUG=b:223304292 TEST=check GL9750 can get enumerated by kernel 5.15. 01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01) Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-14mb/google/nissa/var/nivviks: Enable pen garageEric Lai
Enable pen garage. Pen detect is active low. And wake system when eject. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-10drivers/pcie/generic: Add support to generate code under companion device ↵Cliff Huang
instead Only one ACPI device should be added to a PCIe root port. For the root ports which already have device created, the generated code from this driver needs to be merged with the existing device. By default, this driver will create new device named DEV0. This change allows to generate code under an existing device. ex: (generate code under PXSX): Scope (\_SB.PCI0.RP01.PXSX) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } BUG=b:221250331 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10soc/intel/alderlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table after normalizing to the zero-point value. Although consumer CSE sku also supports this feature, it was validated on CSE Lite sku only. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset on Brya/Redrix 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 88,000 945:CSE started to handle ICC configuration 88,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000) 0:1st timestamp 330,857 (48,857) 11:start of bootblock 341,811 (10,953) 12:end of bootblock 349,299 (7,487) Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10mb/google/skyrim: Configure WLANJon Murphy
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mappping derived from Skyrim schematic. BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10mb/google/skyrim:Update GPIO 32Jon Murphy
GPIO 32 was not allocated correctly, updating to reflect the native function use of the pin BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/herobrine: Add trackpad initializationRavi Kumar Bokka
Initialize trackpad on Qualcomm reference boards BUG=b:182963902,b:223826899 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I93e866d92cf37887a98de88b4b2d768562515670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/guybrush: Enable DEBUG_SMI for non-serial firmwareRaul E Rangel
In order to copy the PSP verstage logs into x86 cbmem, we need to enable DEBUG_SMI. This will include the CBMEM console code in SMM. I only enable DEBUG_SMI when UART is disabled because SMM doesn't currently save/restore the UART registers. This will result in clearing the interrupt enable bits and makes it so you can no longer use the TTY. BUG=b:221231786, b:217968734 BRANCH=guybrush TEST=Build serial and non serial firmware and verify DEBUG_SMI is set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmemRaul E Rangel
Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10cpu/x86/smm: Add weak SoC init and exit methodsRaul E Rangel
This change provides hooks for the SoC so it can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10mb/google/guybrush/var/nipperkin: turn off WWAN DPRKevin Chiu
Sets GPIO 42 to high to turn off WWAN DPR BUG=b:216735313 BRANCH=guybrush TEST=emerge-guybrush coreboot make sure GPIO42 is high Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10soc/mediatek/mt8195: Enable PCIe supportJianjun Wang
Enable PCIe support for mt8195. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10soc/mediatek/mt8195: Add driver to configure PCIeJianjun Wang
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10soc/amd/cezanne/psp_verstage: Log the platform boot mode reportKarthikeyan Ramasubramanian
Log the platform boot mode reported by PSP verstage to PSP stage 1 bootloader. This helps to improve the debuggability. BUG=b:193050286 TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot mode is logged in the verstage logs. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I752ee56f2af48215a770d799432d02f0609757cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-10mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRMKarthikeyan Ramasubramanian
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2. But it is programmed incorrectly in the concerned ACPI device. Pass the correct GPIO. BUG=b:204401306 TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object contains the right GPIO. Ensure that the screen visibility gets updated by pressing the privacy screen button. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10soc/intel/adl: Send EOP early in the boot sequenceMAULIK V VAGHELA
As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-10intel/common/block/cse: Add option to send EOP early via SoCMAULIK V VAGHELA
Earlier while trying to optimize boot time End Of Post (EOP) time kept increasing (~80 ms) when boot time decreased to around 1 second. This was because CSE was busy with own firmware loading. When EOP was moved later in boot stage it again created issue since CSE got busy with other payload loading for OS boot, so response to EOP got delayed by ~70-80 ms. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board. Since this setting might vary for each SoC, SoCs can decide when to send EOP in the boot sequence. This patch adds Kconfig option to send EOP via SoC BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Code compilation is fine for Brya board. Boot time test is done using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms. Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-10Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"Ronak Kanabar
This reverts commit 6af980a2aeca9b8cedfb3d7734389e6e36099c88. BUG=b:199246420 Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-10mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleavezoey wu
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4. BUG=b:219831754 Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10mb/google/brask/variants/moli: Reduce PSysMax to 11 ARaihow Shi
Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W BUG=b:215258941 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10soc/apollolake: Hook up VTD to CMOSSean Rhodes
Hook up vtd_enable to CMOS value of "vtd". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10mb/starlabs/labtop: Remove unnecessary return value from MWAKSean Rhodes
Don't return 0x00 when running MWAK as it is not needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10ec/starlabs/merlin: Use ECWR functionSean Rhodes
Use ECWR function, instead of writing raw values to emem, to avoid a lack of syncronisation as it uses a mutex. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10ec/starlabs: Write the correct value for KLBE when suspendingSean Rhodes
The current code will write the raw value from the CMOS, which doesn't match the respective setting in EC. Switch argument will write the correct value, and prevent the setting being reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10ec/starlabs: Write the correct value for KLSE when suspendingSean Rhodes
The current code will write the raw value from the CMOS, which doesn't match the respective setting in EC. Switch argument will write the correct value, and prevent the setting being reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I93444cdb96eaf729630b48551d0853511b584634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10ec/starlabs: Write the correct value for TPLE when suspendingSean Rhodes
The current code will write the raw value from the CMOS, which doesn't match the respective setting in EC. Switch argument will write the correct value, and prevent the setting being reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10ec/starlabs: Store the correct value for KLBE when suspendingSean Rhodes
The current code will read the raw value from the EC, which doesn't match the respective setting in CMOS. Switch argument will store the correct value. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic2a83df9a270de6d7bab295e732a6c13accbe17c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62606 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10ec/starlabs: Store the correct value for KLSE when suspendingSean Rhodes
The current code will read the raw value from the EC, which doesn't match the respective setting in CMOS. Switch argument will store the correct value. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I62e0fc3b6fcae72f2d8eacf37a390b4e4b1f0783 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62605 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10ec/starlabs: Store the correct value for TPLE when suspendingSean Rhodes
The current code will read the raw value from the EC, which doesn't match the respective setting in CMOS. Switch argument will store the correct value. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62604 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/starlabs/labtop: Always run PTSSean Rhodes
Remove the dependency on Arg0 so PTS always runs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I96c44397d62848231039330a32de781f75bb56bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2022-03-10ec/starlabs/merlin: Change RPTS method to SerializedSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id64d321846dc042d4092d39ce9598d028ab15ed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-10soc/apollolake: Correct SMBus interruptSean Rhodes
This solved the error: i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A i801_smbus 0000:00:1f.1: PCI INT A: not connected i801_smbus 0000:00:1f.1: SPD Write Disable is set i801_smbus 0000:00:1f.1: SMBus using polling Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10soc/mediatek/mt8186: Modify internal capid to 0xE0Rex-BC Chen
The mainboard may not be able to disable the internal cap, so we want to set 0xe0 for all boards to minimize the internal cap. And a mainboard implementation may choose XTAL with higher cload if the frequency requirement is met, and the total capacitance can be tuned externally for different boards. BUG=b:218439447 TEST=set capid to 0xe0. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09cpu/intel/common: Add support for energy performance preference (EPP)Cliff Huang
This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09soc/intel/common: Include Meteor Lake device IDsWonkyu Kim
Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTERFelix Held
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-09drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to driversTim Wawrzynczak
Some non-SoC code might want to know whether or not the CNVi DDR RFIM feature is enabled. Also note that future SoCs may also support this feature. To make the CnviDdrRfim property generic, move it from soc/intel/alderlake to drivers/wifi/generic instead. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2022-03-09prog_loader: Change legacy_romstage_select_and_load() to return cb_errJulius Werner
This is passing through a cb_err from cbfs_prog_stage_load(), so it should be declared to return that as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/62656 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09vc/google/chromeos/Kconfig: Fix typoAngel Pons
heirarchy ---> hierarchy Change-Id: I5cbd77a156852e6f8ad6eafc316ee33f153635b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-03-09soc/mediatek/mt8186: set pin drive strength to 8mA for NORRex-BC Chen
Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=SPI SI tests for AP to NOR pass for both kingler and krabby. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-09soc/mediatek/mt8186: Add GPIO driving functionsGuodong Liu
Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUsDavid Wu
Based on testing results from the thermal team, they have decided to update PL1, PL2 and PL4 for U28 SKUs. BUG=b:221338290 TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-03-09mb/google/brya/variants/felwinter: Fix stylus UI behavior bugJohn Su
Fix stylus UI behavior bug. 1) it appears the kernel's gpio_key driver is not expecting an IRQ descriptor for the `gpio` property, therefore change to an active-low input. 2) The wakeup event was configured backwards. Change list - Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW". - Change wakeup_event_action from ASSERTED to DEASSERTED. BUG=b:220992812 TEST=emerge-brya coreboot chromeos-bootimage and verify pass Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/skyrim: Add FW_CONFIG DefinitionJon Murphy
BUG=b:214415048 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-09cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMIRaul E Rangel
This change will allow the SMI handler to write to the cbmem console buffer. Normally SMIs can only be debugged using some kind of serial port (UART). By storing the SMI logs into cbmem we can debug SMIs using `cbmem -1`. Now that these logs are available to the OS we could also verify there were no errors in the SMI handler. Since SMM can write to all of DRAM, we can't trust any pointers provided by cbmem after the OS has booted. For this reason we store the cbmem console pointer as part of the SMM runtime parameters. The cbmem console is implemented as a circular buffer so it will never write outside of this area. BUG=b:221231786 TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are visible when running `cbmem -1`. Perform a suspend/resume cycle and verify new SMI events are written to the cbmem console log. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-09mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8Wisley Chen
Config VR_DOMAIN_GT's slew rate to 1/8 as well. BUG=b:204009588 TEST=build and verified by Power team. Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/bry/anahera{4es}: Disable TCSS port1Wisley Chen
Disable unused TCSS Port1. BUG=b:223082190 TEST=Build Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/brya/var/anahera{4es}: Configure Acoustic noise mitigationWisley Chen
Enable Acoustic noise mitigation and set slew rate to 1/8 BUG=b:223082189 TEST=build and verified by power team Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/nissa: Add fmd file for nissaKrishna Prasad Bhat
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash layout for brya is of 32MB size, and nissa is expected to have 16MB SPI NOR flash. The current composition of AP firmware exceeds 16MB. To get an estimate of the unutilized region in the current flash layout for nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware size to under 16MB and to remove the RW_UNUSED regions from the final fmd file. Below table gives the size reduction from brya fmd to nissa fmd: +----------------+-------------------+---------------+ | Region | Earlier size (KB) | New size (KB) | +================+===================+===============+ | SI_ME | 5116 | 3772 | +----------------+-------------------+---------------+ | RW_SECTION_A/B | 8192 | 4344 | +----------------+-------------------+---------------+ | VBLOCK_A/B | 64 | 8 | +----------------+-------------------+---------------+ | ME_RW_A/B* | 3008 | 1434 | +----------------+-------------------+---------------+ | RW_LEGACY | 2048 | 1024 | +----------------+-------------------+---------------+ | RW_ELOG | 16 | 4 | +----------------+-------------------+---------------+ | SHARED_DATA | 8 | 4 | +----------------+-------------------+---------------+ | VBLOCK_DEV | 8 | 0 | +----------------+-------------------+---------------+ | RW_SPD_CACHE | 4 | 0 | +----------------+-------------------+---------------+ | RW_NVRAM | 24 | 8 | +----------------+-------------------+---------------+ | WP_RO | 8192 | 4096 | +----------------+-------------------+---------------+ | GBB | 448 | 12 | +----------------+-------------------+---------------+ *Based on LZMA compression on ME_RW_A/B regions. With LZMA compression, this region can be 1434K. Without this, ~665K will be more in each of these regions. Patch: https://review.coreboot.org/c/coreboot/+/62358/ BUG=b:202783191 BRANCH=None TEST=Build and boot Nivviks. Cq-Depend: chrome-internal:4584911 Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-09mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW KconfigKrishna Prasad Bhat
Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09soc/intel/common: Add Kconfig to enable compression on ME_RW blobsKrishna Prasad Bhat
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B regions. On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B regions. FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none FMAP REGION: ME_RW_B Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09coreboot_tables.c: Expose the ACPI RSDPArthur Heymans
The ACPI RSDP can only be found in: - legacy BIOS region - via UEFI service On some systems like ARM that legacy BIOS region is not an option, so to avoid needing UEFI it makes sense to expose the RSDP via a coreboot table entry. This also adds the respective unit test. Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09soc/apollolake: Hook up CnviMode to devicetreeSean Rhodes
Hook PCH_DEVFN_CNVI (0c.0) to CnviMode. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09ec/starlabs: Correct Keyboard Backlight offsets for GLKSean Rhodes
Correct the offsets used for the keyboard backlight control: ECRAM_KBL_STATE 0x19 ECRAM_KBL_BRIGHTNESS 0x18 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I23bac43301635e6b18f1cbd28311e7210b049c70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09mb/starlabs/labtop: Remove duplicate value from KconfigSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0324747f936be27ee39e586124005530d5c424b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-09mb/dell/optiplex_9010: Fix chassis typesMichał Żygowski
Discovered this chassis identification number on Dell Precision T1650 which is much OptiPlex 9010 alike. Precision T1650 is a Mid Tower (MT) chassis. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I2266fe39606b947a3d30a9462377fd56c39c2fa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-09mb/dell/optiplex_9010/mainboard.c: Add missing spaceMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3487b0ab94e565862ed727e9a91bd1efb364d43d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-09{drivers/security}: Replace `cb_err_t` with `enum cb_err`Subrata Banik
This patch replaces remaining `cb_err_t` with `enum cb_err` after commit hash 69cc557c (commonlib/bsd: Remove cb_err_t) removes majority of `cb_err_t` instances. TEST=Able to build the brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-09commonlib/bsd: Remove cb_err_tJulius Werner
cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09soc/mediatek: Add PCIe supportJianjun Wang
Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-08soc/intel/tgl: chipset devicetree: correct TraceHub device aliasMichael Niewöhner
Device 1f.7 is TraceHub, not the PCH Thermal device, which doesn't exist anymore on TGL. Correct the device´s alias. Reference: Intel doc# 631119-007 Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08soc/intel/tgl: drop orphaned VR domains enumMichael Niewöhner
Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08ec/starlabs: Guard Max Charge in KconfigSean Rhodes
Guard Max Charge EC write in Kconfig so it's only used on platforms that support it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-08mb/starlabs/labtop: Add LabTop Mk IVSean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iv-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08sb/intel/common/firmware: Hook up adding 10GbE LAN firmwareJeff Daly
Add ability to use ifdtool to add LAN firmware to image using Kconfig Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08util/ifdtool: Add support for Denverton SoCJeff Daly
Denverton is a special version of IFD2 flash layout. It defines 10GbE firmware regions (11/12) and the IE (10) region which other IFD2 platforms do not have. Denverton does not include the legacy GbE region (3) or the EC region (8) which other IFD2 platforms do have. TEST='ifdtool -p dnv coreboot.rom' and verify correct output Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08mb/google/brask/variants/moli: set up gpioRaihow Shi
Set the GPIO configuration of moli BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-08ec/starlabs/merlin: Disable ACPI support last when suspendingSean Rhodes
When entering suspend, ACPI support is disabled by setting OSFG to 0x00. This has been moved to be the final action, so it is after saving the current EC settings. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08ec/starlabs/merlin: Use ECRD functionSean Rhodes
Use ECRD function, instead of getting raw values from emem, to avoid a lack of syncronisation as it uses a mutex. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I31113ef9af3a1e171e3e1f226e7adcfa0fbce61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC addressWerner Zeh
Set the log level to BIOS_NOTICE for the case where the mainboard can not provide a MAC address since this can be a valid case. Showing this message with log level BIOS_ERR is not appropriate. In addition, rephrase the message to make clear that if the mainboard does not provide a MAC address the one stored in the MAC will be used. Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-03-08mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10Reka Norman
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nivviks overridetree to enable port 10 instead of port 8, which is the external port used for bluetooth with PCIe WLAN. BUG=b:222595137 TEST=Bluetooth works on nivviks Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-03-08device/mmio.h: Move readXp/writeXp helpers to device/mmio.hJianjun Wang
These helpers are not architecture dependent and it might be used for different platform. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08mb/google/brya/var/primus{4es}: add enable pin to rtd3-coldCasper Chang
Currently the BayHub eMMC controller is only going into its reset state when the RTD3 sequence is initiated. This causes it to still consume too much power in suspend states. This CL adds the power enable GPIO into the RTD3 sequence as well, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage test suspend stress 100 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00Ronak Kanabar
The headers added are generated as per FSP v3091_00 Previous FSP version was v2511_04 Changes include: - Update MemInfoHob.h BUG=b:222415800 BRANCH=None Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-07mb/google/brya: Enable GPIO PM dynamically based on cr50 FW versionTim Wawrzynczak
cr50 firmware revisions starting at 0.5.5 and later are able to extend their IRQ pulses to be a minimum of 100us long. This change will enable cr50 long interrupt pulses when it detects the feature is supported by the detected firmware version. If the capability was detected, then GPIO PM will be enabled for the device, otherwise it will be disabled. BUG=b:202246591 TEST=boot brya0, check console logs for the correct message, and verify the GPIO PM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07drivers/tpm/cr50: Add I2C bus support to cr50 driverTim Wawrzynczak
This allows mainboards using an I2C bus to communicate with the cr50 to reuse the functionality related to firmware version and BOARD_CFG. BUG=b:202246591 TEST=boot on brya0, see cr50 FW version in logs Change-Id: Ide1a7299936193da3cd3d15fdfd1a80994d70da0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-07drivers/tpm/spi: Refactor out some cr50-specific logicTim Wawrzynczak
Mainboards accessing the cr50 over an I2C bus may want to reuse some of the same firmware version and BOARD_CFG logic, therefore refactor this logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses the new tis_vendor_read/write() functions in order to access the cr50 regardless of the bus which is physically used. In order to leave SPI devices intact, the tis_vendor_* functions are added to the SPI driver. BUG=b:202246591 TEST=boot to OS on google/dratini, see the same FW version and board_cfg console prints as before the change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-07mb/google/brya/var/taniks: Add GL9750 SD card reader supportJoey Peng
Add GL9750 SD card reader support. BUG=b:222402409 TEST=Build FW and check device function normally. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/var/redrix{4es}: Disable TCSS PCIe port1Wisley Chen
Disable unused TCSS PCIe port1 BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07soc/intel/tigerlake: Hide PMC and IOM devicesMichał Kopeć
Windows complains on missing drivers for these ACPI devices. Hide them from OS as it doesn't influence the hardware operation. Linux can still probe the drivers correctly. TEST=Boot Windows 11 and see there are no devices with missing drivers. Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are still probed. Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/vell: Enable USB2 port for KBD MCUDaisuke Nojiri
Vell has a keyboard MCU connected to USB2 port 7. This patch enables the port. localhost# usb_updater2 -f Found device. found interface 0 endpoint 1, chunk_len 64 READY ------- start target running protocol version 6 (type 1) maximum PDU size: 4096 Flash protection status: 0000 version: prism_v2.0.12137+c4ae1432f5 key_version: 1 min_rollback: 0 offset: writable at 0xc000 Current versions: Writable prism_v2.0.12137+c4ae1432f5 BUG=b:203664745,b:211496726 TEST=Run 'usb_updater2 -f' on Vell. Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/var/{brya*,redrix*}: Add DmaProperty for WWANTim Wawrzynczak
ChromeOS considers the WWAN devices to be untrusted, therefore enable the new DmaProperty in the WWAN's _DSD to indicate to the OS that these devices should have IOMMU restrictions applied to them. BUG=b:215424986 BRANCH=brya TEST=dump SSDT Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-07drivers/wwan/fm: Include option to add ACPI _DSD for DmaPropertyTim Wawrzynczak
Similar to commit 09c047c, the WWAN device might be considered an untrusted device by some platforms, therefore add an option to add the same `DmaProperty` to the WWAN _DSD. BUG=b:215424986 BRANCH=brya TEST=dump SSDT, see new property Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If485ac5314fae6e6faefac43fcfcea4f4cdd02c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-07mb/google/hatch/var/jinlon: Fix EPS detection and disablementMatt DeVillier
Commit ebf14826 [mb/google/hatch/var/jinlon: Switch to using device pointers] broke jinlon boards without an electronic privacy screen (EPS) by disabling the parent device (iGPU) instead of the EPS when determined to be not present via SKU ID. Commit c5a3a4a6 [mb/google/hatch (baseboard): add ACPI backlight support] broke EPS detection by adding a duplicate iGPU device to the devicetree, resulting in the EPS entry being skipped. Fix both of these issues by assigning the device alias to the EPS child device, not the parent (iGPU). Rename the alias for clarity, and combine the duplicate device definitions for the iGPU. Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional in both firmware boot screens and Linux OS. Change-Id: I0615ce361497abe6872085b0dec83292607e53dd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07mb/google/glados: Restore ChromeEC tablet mode switch for caroline, caveMatt DeVillier
Commit 017b5c453a72f57ec785da1764939e24651ac5eb [ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config] broke tablet mode on google/caroline and cave in mainline Linux kernels by changing the inclusion of the ChromeEC tablet mode ACPI handler. Fix this by addding it back (using the updated name guarding the inclusion of the tmbc ACPI). Test: build/boot google/cave under Linux 5.16, observe tablet mode handled correctly. Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07soc/intel/alderlake: Use Kconfigs for Descriptor RegionSridhar Siricilla
The patch uses Kconfigs for Descriptor Region and Descriptor Region size instead of locally defined macros TEST=Build and boot Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-03-07soc/intel/alderlake: Define Kconfigs for Descriptor RegionSridhar Siricilla
The patch defines Kconfigs for FMAP Descriptor Region and Descriptor Region size. The Kconfigs will be used by follow-up patches. TEST=Build Brya code Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/var/redrix{4es}: Re-enable USB2 port for BluetoothWisley Chen
BT didn't work due to commit 03c0853f4d58c73. Commit 03c0853f4d58c73 accidentally set the Bluetooth USB2 port to "empty", therefore re-enable USB2 port 9. BUG=b:217238553, b:222238381 TEST=build and verfied BT work/suspend successfully Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 14:25:21 +0000