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This EC code is for the Byte, a Cezanne Mini PC. The EC is different
to the Cezanne StarBook Mk VI. Rename it to `-desktop`, so the laptop
variant becomes the primary.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I25f812cb1c6cefca1ebbe3bee5d20cf521dd60af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the characters per line limit was increased from 80 to 96, some
line breaks can be removed to improve code readability.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92aa3fec8c8caba143e418efc999ec4a7c5d93c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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When no HOB list is found, not only adding the resources reported by the
FSP were skipped, but also adding the GNB IOAPIC resource was skipped.
Fix this bug by moving the reporting of the GNB IOAPIC resource before
the resources reported in the FSP HOBs to not skip the IOAPIC resource
when there's no HOB list.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
gladios variant.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The WCH CH347 presents a USB CDC serial port on interface 4 while in
operating modes 0, 1, and 3. Mode 0 also presents a UART on interface
2 but this is ignored for compatibility with the other modes. Mode 2
uses vendor defined HID usages for communication and is not currently
supported. Like the FT232H the data format is hard coded to 8n1.
Tested using a CH347 breakout board and a Dell Latitude E6400.
Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68264
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Required for 2nd COM port to work.
Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The FSPM and FSPS UPD signatures hadn't been updated from their cezanne
origins. Change them to MNDCNO_M/S.
BUG=b:240573135
TEST=Build & boot, see new signature in boot log.
Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Without a cast the aritmetics of
tat = einj + sizeof(acpi_einj_smi_t)
is the same as
tat = (uintptr_t)einj + size(acpi_einj_smi_t) * size(acpi_einj_smi_t)
So it overshoots the intended offset by a lot.
This issue only came apparent because now einj is in the small IMD
region which is close to TSEG. With the wrong aritmetics the tat
pointer ended up inside TSEG which is not accessible from the OS
causing exceptions.
TEST: observe that tat pointer is inside the small IMD below
TSEG (0x78000000 on our setup).
"acpi_create_einj trigger_action_table = 0x77ffe89c"
Change-Id: I3ab64b95c33eef01b2048816a21e17855bcb2f54
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.
Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I6ff18e5ede0feda65f81c064394febd3eebc5247
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55316
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Commentary about mixing LAPIC IDs and IOAPIC IDs was wrong,
remove it. The only platform affected is aopen/dxplplusu with
i82801dx southbridge.
Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Using this I/O APIC IDs will be assigned incrementally
in the order of calling. I/O APIC ID #0 is reserved for
the I/O APIC delivering GSI #0.
Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Read I/O APIC ID and vector counts from hardware.
Change-Id: Ia173582eaad305000f958c5d207e9efaa06d8750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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to soc
Move SMBIOS type 4 override functions from mainboard to soc so that all
xeon family cpus share same functions without implementing again.
Tested=On OCP Deltalake, dmidecode -t 4 shows expected info.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Add definition for smbios type 4 and type 9
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Skyrim platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.
BUG=b:241878652
BRANCH=none
TEST=Build kernel and firmware. Run on skyrim and verify TPM
functionality.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Updated comment as per guidelines.
BUG=b:232302324
TEST=none
Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable WLAN power and deassert the various radio disables.
TEST=boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Change the EC FW CBFS filename prefix to a more accurate "ec/"
TEST=build and boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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To support an RPL SKU on marasov, marasov must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL
FSP headers for marasov.
BUG=b:254365935
BRANCH=None
TEST=FW_NAME=marasov emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
MT62F1G32D4DR-031 WT:B 4 (0100)
H9JCNNNCP3MLYR-N6E 5 (0101)
BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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update devicetree setting per the schematic
BUG=b:254365935
BRANCH=None
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This kind of allocation without '=' is not working with clang.
Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It looks like this code was not finished so it's left commented out
for now.
Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The EC_CMD_USB_PD_PORTS host command returns a
struct ec_response_usb_pd_ports, not a
struct ec_response_charge_port_count.
Luckily, both structs have the same memory layout, so this is simply a
name change.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Simplify the implementation of setting the keyboard backlight PWM
value. Host command stubs typcially don't need to examine the host
command's return value as stored in cmd_code because that level of
detail is not very interesting. Higher value error codes are returned in
actual result structures.
This host command can return EC_RES_ERROR for out of range PWM values
which is already a generic error and unlikely to happen since we already
limit the range to 0..100 here. Finally, none of the callers in coreboot
check the return value.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT command does not return data, so
don't specify a result buffer.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I5b9a0d228e187a9337498246a3b9ed8db07b95c7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events.
EC panic is not covered by the standard (0-F) ACPI notify values.
Arbitrarily choosing B0 notify, which is in the 84-BF device specific
ACPI notify range.
This will be a no-op until the kernel driver is also updated to handle
this event.
BUG=b:258195448
BRANCH=None
TEST=Observe event with modified cros_ec_lpc driver
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:257879909
Test:Boot to OS on craask and check stylus GPIO pins
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Request by thermal team, make below changes:
1) tdp_pl2_override: 12 --> 25
2) pl1.min_power: 3000 --> 5500
3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC
4) pl2.min_power: 12000 --> 25000
5) pl2.max_power: 12000 --> 25000
6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1
7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1
BUG=b:239495499
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
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Update SX9324 related settings based on tunned values from the ODM.
This patch supports both legacy and upstream Linux's SX9324 driver.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28
(Verified register values on Pujjo)
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie3a08799294729beec83faf819fb1f249c6461cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I2b611773e596bea4788b05a3f58485fb3e002402
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69362
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when
the cpu is in x2apic mode.
TESTED: Fixes SMI generation on xeon_sp hardware with
CONFIG_X2APIC_RUNTIME.
Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.
BUG=b:186792595
TEST=Builds for volteer
Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This commit factors out some code for XHCI port status values.
BUG=b:186792595
TEST=Built coreboot for volteer device
Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e
and applies minor fixes to make it build again.
PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.
Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These symbols and codepaths are unused now so drop them.
Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.
TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with clang on prodrive/hermes: Boots to payload
Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69234
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clang warns on both the declaration and the definction.
Change-Id: I94d979fcdbe41349c59248656066615bffd215b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Expression after a case statement are not allowed.
This fixes building with clang.
Change-Id: Ie369454f10b515aa5601a5e78330e12f4b7a5e4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code was never tested with SSE enabled. Now qemu enables it and
FX_SAVE encroaches on the save states. Without SSE enabled the handler
just happened to be aligned downwards enough to have the save states
fit. With SSE enabled that's not the case. The proper fix is to give the
code setting up stubs the right base address, which is the same as for
the TSEG codepath.
Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Provide timing parameter for SSDT generation to achieve the requested
100 kHz speed with a high accuracy.
Test: Measure I2C bus clock, high and low times during I2C access from
Linux and confirm they match the specification.
Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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In Linux, the I2C speed defaults to 400 kHz if there is no device
registered in ACPI which requests a different speed. Due to board
limitations (layout, bus load), 400 kHz are too fast which results in a
timing violation. Therefore, add a dummy I2C device to both used I2C
buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus
speed in Linux accordingly.
Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).
This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.
Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as
the base clock for I2C controllers. To support them properly add a
frequency setting for 100 MHz to the designware I2C controller driver.
Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Add wifi sar table for craask/craaskbowl.
Use fw_config to separate different project settings.
BUG=b:247652032,b:251287099,b:251287101
Test=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.
BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
11:start of bootblock 688,046
14:finished loading romstage 30,865
16:FSP-M finished LZMA decompress (ignore for x86) 91,049
Total Time: 1,972,625
After:
11:start of bootblock 667,642
14:finished loading romstage 29,798
16:FSP-M finished LZMA decompress (ignore for x86) 87,743
Total Time: 1,943,924
Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E.
DRAM Part Name ID to assign
H9JCNNNCP3MLYR-N6E 0 (0000)
BUG=b:257867226
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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SX9324 driver is updated per Linux's documentation found at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
Supporting logic for the deprecated SX932x driver is hence guarded by
DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
This patch by itself does not introduce functional changes to any board.
The legacy SX932x Linux driver never reached upstream Linux and is only
available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted
a different implementation named SX9324 and has been available since
5.4. Ideally all variants should adopt the new driver; however, during
the transition phase, coreboot must support both drivers. It is better
to have a single firmware build that can work with both Linux kernel
drivers by specifying both sets of properties. Legacy driver support
should be deleted once all variants finish migration.
BUG=b:242662878
TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
SX932x driver are identical w/ and w/o this patch
(Tested on Craask and Nivviks)
Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of
FPMCU on startup")
TEST=Tested on Rex - setup and logged in using fingerprint
Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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These functions are added for ramstage:
* add IPMI OEM command to get board configuration.
* add function to get blade index in the sled.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68779
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Kconfig SOC_RAS_BMS_SEL and corresponding support for
generating PCIe error SEL records and sending them to BMC.
Add PCIe error definitions.
This is needed for SMM, so build the ipmi kcs driver in SMM.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68758
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.
This patch also adapts mainboards and SoCs to new vboot reset
requirements.
TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.
Re-define in the common code.
Update coreboot code to use FSP_X_CONFIG consistently.
Tested=On OCP Delta Lake, boot up OS successfully.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the
coreboot tree other than in arch/x86/tables.c. Add macros to
standardize these postcodes.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This patch groups vboot context, recovery reason and subcode saving, and
reboot calls into two handy functions:
- vboot_save_and_reboot() - save context and reboot
- vboot_fail_and_reboot() - store recovery reason and call function
above
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change-Id: I16aa756039973e164c887ff5237bda69d042a235
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use "* MiB" instead of "<< 20".
Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Also sort includes.
Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Disable Pch PM Energy Report WA was added to enhance boot time
with HFPGA only. SoC needs reporting enabled.
BUG=None
TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression..
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for moli board. Please refer Intel doc#723158 for
more information.
BUG=b:257415959
TEST=Verify the build for brask board
Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4
Signed-off-by: Ricky Chang <rickytlchang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).
TEST=Able to build and boot Google, Rex to OS.
Without this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0
With this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
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BUG=b:239495499
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69197
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
|
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This patch supports multiple camera modules based on FW_CONFIG.
BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ricardo Ribalda <ribalda@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kinox board. Please refer Intel doc#723158 for more
information.
BUG=b:257373738
TEST=Verify the build for kinox board
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Lisbon doesn't support thunderbolt.
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This enables ACPI configuration and add ACPI table.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The headers added are generated as per FSP v3361.07
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:254054169
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.
BUG=b:218406702
TEST=reboot from AP console (on CRD3)
prior to fix (from cbmem dump):
1000:depthcharge start 1,139,809 (152,679)
after fix (from cbmem dump):
1000:depthcharge start 1,041,109 (46,353)
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.
Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently build rules allow using x86 SHA extensions for all coreboot
stages when enabled. On some SoCs where verstage can run in non-x86
environment, x86 SHA extension cannot be used. Update build rules
accordingly such that x86 SHA extensions can be used in AMD SoCs. This
is particularly useful when CBFS verificiation is enabled which verifies
the hash of the CBFS file being loaded.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration
is used when a CBFS file is loaded and observe an overall improvement of
10 ms.
Change-Id: I4f388e963eb82990cda41d3880e66ad937334908
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68953
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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No need to call a function that just instantly returns.
It greatly enhances readability to just check before calling a funtion
and it also removes an extra argument.
Change-Id: I4d57c45ede520160ef615725c023b7e92289a995
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This adds an initial mainboard code for mtlrvp, Intel Meteorlake
reference platform.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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RTD3,_ON method sometimes can create delays during system boot.
Even when the power is already up, kernel still tries to call _ON
method to power up device, but it's unnecessary.
RTD3._STA returns device power, so _ON method can check _STA and see
if the power on process can be skipped
BUG=b:249931687
TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on
Crota. Suspend stress test passes 100 cycles
Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Switch cases expect a statement so move the default label.
TEST: With BUILD_TIMELESS=1 binary remains identical.
Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66266
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:253210291
TEST=Able to build and boot rex to OS. Also needed for S0ix, tested
with Sandbox OS + Firmware combination for S0ix entry/exit.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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const void is a meaningless return type and clang complains about
incompatible function pointer signatures.
Change-Id: Ia00706b9cd718e590819621986dbd20555f6c226
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable the mirror flag for CML and TGL.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I51678bdb8d876d238076e12c6315a53c5da59628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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When enabled, the EC will mirror the firmware contained inside the
coreboot ROM. This allows it to be updated at the same time as
coreboot.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ief088e012b65be32648f581fc3190e1000bca241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.
BUG=b:121309055
TEST=build/boot ChromeOS and Linux on guybrush, ensure touchscreen is
functional, and ACPI device entry generated for correct touchscreen
model.
This mirrors the changes made for skyrim in CB:67779.
Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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As all variants have a touchscreen option, in baseboard table set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.
Variants/SKUs which do not have a touchscreen (if any) can use the
romstage/ramstage GPIO override tables to set the associated enable/
reset GPIOs to NC.
This mirrors the change to skyrim in CB:67778.
BUG=b:121309055
TEST=build/boot guybrush with rest of patch series
Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell
system demonstrated better power improvement without sacrificing the
performance.
PLT Results(Perf) with EPP@40% and EPP@50%:
EPP@40%: Device1-656 mins, Device2-664 mins.
EPP@50%: Device1-678 mins, Device2-677 mins.
In short, with EPP@50%, PLT KPI ran for more than 13 to 22mins compared
to EPP@40%.
Branch=firmware-brya-14505.B
BUG=b:215526166
TEST=Verified code build for Vell board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Only a subset of variants has proximity sensors.
This patch by itself does not introduce functional changes to any board.
It is mainly to ease migrating SX9324 from the legacy driver to the
linux one - allowing gradual migration variant by variant.
BUG=b:242662878
TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch
Change-Id: Ic00e0d9eafcef2c9eaf32571fecf6190777cec36
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69191
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No platform uses this anymore.
Change-Id: Ifccb59ae45daa8fec41a9a2d46c628ff24a0c998
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69140
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that all platforms use parallel_mp this is the only codepath used
for cpu_info() local thread storage.
Change-Id: I119214e703aea8a4fe93f83b784159cf86d859d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69122
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This codepath is deprecated after the 4.18 release.
Change-Id: I7e90f457f3979781d06323ef1350d5fb05a6be43
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69121
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is deprecated after the 4.18 release.
Change-Id: I17327c31f8ade51716578e45c2d90a327efcd4ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69128
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is now unused by any platform.
Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This code is now unused by any platform.
Change-Id: I5464daa8cfb8231e2b19447c343fc80ab1d68ce8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69119
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Now that all agesa CPUs are removed this code is unused.
Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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