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2024-04-03drivers/intel/fsp2_0: Use coreboot uint8_t type for consistencySubrata Banik
This patch replaces UINT8 with uint8_t to align with coreboot's standard data type conventions. This promotes consistency within the codebase. BUG=b:242829490 TEST=Verified firmware splash screen functionality on google/rex0. Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81571 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-02mb/google/brox: Enable PMC pins to work with PDAshish Kumar Mishra
Enable SMLINK1 interface for PMC-PD communication to configure Type-C muxes. Refer RPL EDS vol 1: 765585. BUG=b:327622474 BRANCH=None TEST=Boot image on SKU2 and check PMC-PD working. Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
2024-04-02mb/google/brya: Make get_soc_power_limit_config() a public functionSeunghwan Kim
Make get_soc_power_limit_config() a public function to use on brya variants. Add prefix 'variant_' for it. BUG=None BRANCH=brya TEST=emerge-brya coreboot Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-02mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory partsLeo Chou
Add sundance supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE BUG=b:332201349 TEST=Use part_id_gen to generate related settings Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-02mb/google/rex/var/deku: Swap LAN device indices for correct MAC addressTony Huang
Deku has two Ethernet ports. Currently both get assigned the wrong MAC address due to the LAN devices indices being swapped and vpd ethernet_mac0() affects device eth1 and vpd ethernet_mac1() affects device eth0. Correct the device indices for LAN devices so ethernet_mac[0-1] in vpd can apply to the correct ethernet ports. BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=vpd -s ethernet_mac0=<mac address0> vpd -s ethernet_mac1=<mac address1> reboot the system and check ifconfig eth0 and eth1 MAC addresses are fetched correctly Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81564 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-04-02include/device/pci_ids.h: Add DIDs for MTL Touch controllerCliff Huang
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for THC0, and 0x7e4b for THC1. 0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0 and THC1 respectively. Refer MTL EDS vol 1: 640228. BUG=b:307775082 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81330 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
2024-04-02drivers/mipi: Add support for KD_KD101NE3_40TI panelYang Wu
Add K&D panel KD_KD101NE3_40TI serializable data to CBFS. Datasheet: KD101NE3-40TI-A003 _Pre SPEC_20231218.pdf BUG=b:331870701 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81583 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01Kconfig: Make GBD_STUB and long mode mutually exclusiveArthur Heymans
GDB debugging is not implemented with x86 long mode. Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81379 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01soc/intel/xeon_sp: Remove PAM unlock operationsShuo Liu
unlock_pam_regions routes Programmable Attribute Map (PAM) access to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the step to SoC specific codes. TEST=intel/archercity CRB Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-01acpi: Add acpigen_write_OSC_pci_domainShuo Liu
Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Dynamic SSDT generation is used to generate a list of ASL device objects based on FSP outputs (e.g. the SoC/SKU configurations) and _OSC is a method inside these objects (hence it would be straightforward to be generated altogether, plus some C codes managed boot configs could be referenced as well). This usage is optional. It is helpful for cases where the same code set supports multiple SKUs/SoCs (difficult to be handled by one set of static SSDT), and the CPU performance is good enough to run SSDT generation logics with minimal costs. TEST=intel/archercity CRB Tested with https://review.coreboot.org/c/coreboot/+/81377. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-01intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASEShuo Liu
IBL (Integrated Boot Logic) provides a subset of server PCH logics for no-PCH solution. IBL is with limited features and registers exposed, PCIe root ports/USB/SATA/LAN support are removed. Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01soc/intel/xeon_sp: Redefine data types for GNRShuo Liu
Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/ UDS_SOCKET_RES and retires the usages of STACK_RES/ IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both 6th Gen before and later. Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81040 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01mb/google/{brya,hades}: use soc index for variant_update_power_limits()Seunghwan Kim
The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01mb/google/brya/var/xol: Update GPIO settings for speaker and DMICSeunghwan Kim
Update GPIO configuration according to the schematic changes. The locations of speaker and DMIC are swapped. - Speaker: I2S2 -> I2S1 - DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5 BUG=b:318584606 TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81444 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-01mb/google/brox: Configure ISH device based on FW_CONFIGKarthikeyan Ramasubramanian
ISH Firmware name needs to be configured only when full sensing capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA property needs to be added only when UFS is enabled through STORAGE_UFS FW_CONFIG. Hence configure the ISH device at run-time based on FW_CONFIG. BUG=b:319164720 TEST=Build Brox BIOS image and boot to OS. Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01mb/google/nissa/var/glassway: Add 2nd Synaptics touchpadFrank Chu
Add Synaptics touchpad via HID-I2C interface in I2C5 bus for glassway. BUG=b:331677400 BRANCH=firmware-nissa-15217.B TEST=emerge-brya coreboot and check touchpad function work. [INFO ] input: PNP0C50:00 06CB:CE9B Touchpad as /devices/pci0000:00/0000:00:19.1/i2c_designware.5/i2c-17/i2c-PNP0C50:00/0018:06CB:CE9B.0001/input/input4 [INFO ] hid-multitouch 0018:06CB:CE9B.0001: input,hidraw0: I2C HID v1.00 Device [PNP0C50:00 06CB:CE9B] on i2c-PNP0C50:00 Change-Id: Ifbb2cb750a80bc6e8f96609257dcd1e695ad1fa4 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-01mb/google/nissa: Create sundance variantLeo Chou
Create the sundance variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:328505938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_SUNDANCE Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2024-04-01arch/ppc64: Add arch as supported by the clang compilerArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1aacff869663e1db74cd485787d7103b9ec5602e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78448 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-01arch/ppc64: Fix inline assembly for clangArthur Heymans
Use macros from the Linux kernel 6.5 to make the inline assembly also compile on clang. TEST: See that the generated code is identical on GCC and compiles on clang. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-01mb/google/corsola: Add new board variant 'Kyogre'Kei Hiroyoshi
Add a new Kingler follower device 'Kyogre' BUG=b:318614302 TEST=emerge-corsola coreboot Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Signed-off-by: Kei Hiroyoshi <hiroyoshi.kei@fujitsu.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81218 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-01soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPLKilari Raasi
The RPL FSP currently uses HECI commands to retrieve the chipset initialization version because the MBP HOB creation is disabled (SkipMbpHob=1). This has resulted in an approximate 150ms increase in boot time. Investigations are ongoing to determine the cause of the delay when using HECI commands. As an interim solution, this patch sets SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset initialization version, which is expected to reduce the boot time. BUG=b:328430167 TEST= Able to build,boot and collect boot time data of brya. With this patch: 963:returning from FspMultiPhaseSiInit 1,337,481 (249,046) Without this patch: 963:returning from FspMultiPhaseSiInit 1,496,268 (408,194) Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-03-30vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headersJincheng Li
GNR N-1 FSP headers are a set of stub headers used to fulfill build sanity check for GNR SoC and CRB codes before the formal FSP headers are published. The N-1 headers are forward compatible with the later formal headers. Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-30soc/intel/xeon_sp: Unshare Xeon-SP chip common codesShuo Liu
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack descriptors impacting the way of coreboot's creation of domains. Separates the codes as preparation for 6th Gen and later platforms. Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-30superio/ite: Add full-speed config optionJoel Linn
Add Kconfig option for full-speed setting. Some variants do not support the full-speed at limit configuration (IT8772F). Keep it enabled for all current variants that use the common EC code as it was previously enabled unconditionally - datasheets weren't revisited individually. Change-Id: Icf24ea1c4f41771a18803957456f0aeba0e51b13 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81525 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30superio/ite: Fix incorrect warningsJoel Linn
Fix warning for disabled thermal inputs. Fix warning for PECI thermal inputs if one was set up previously. Depending on the mb, the superio will not go through power-on reset and retain its registers. Do not trigger a warning if the current register value aligns with the desired value. Don't return early if some input is already configured for PECI, simply overwrite the configuration. Both warnings were observed while porting the "HP Pro 3500 Series" mb. Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-30drivers/tpm: Make it compile againPatrick Rudolph
Fix regression introduced in 47e9e8cde1810ee9f249027b14ee9f82a7a52d84 "security/tpm: replace CONFIG(TPMx) checks with runtime check": Replace BIOS_WARN with BIOS_WARNING. Change-Id: Id23cda2f5403effd2a4bda3852f0f300d0e62cdf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81590 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30soc/intel: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-30commonlib: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I57686e68b4b1bdb28a15b69e55b71c98b0b53a1f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30superio: Remove blank lines before and after code blocksElyes Haouas
Change-Id: I0d2ff9828e83ef927036c561d11f95b54b858cda Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/acer: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I335487ca1b17ab958c0d0238f425b92b430014ca Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/inventec: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I51dd9eb5a2fef5800670f981275139e932af2be0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81493 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30mb/google: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-03-30soc/cavium: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: Id604dc981d6ca0a8163b7477b7916210faa56a77 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/emulation: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/amd: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I2dae34441909f6135b95e7b017659ce4f4666b4e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30soc/qualcomm: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If2c2138ed3dc437b924297330805caa8c357853d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30soc/rockchip: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81459 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30soc/amd: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I0203e77dd23fa026cd252abbda50f1e9f6892721 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30acpi: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I9ba061fe0b1396ccc1597e26685a6b4e312e3549 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30arch/x86: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I1bb4a052a4e74850660944b687c21e817eb437b2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-28cpu/x86/Kconfig: Mark 64bit support as stableArthur Heymans
With SMM holding page tables itself, we can consider SMM support stable and safe enough for general use. Also update the respective documentation. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-28cpu/x86: Link page tables in stage if possibleArthur Heymans
When switching back and forth between 32 to 64 bit mode, for example to call a 32-bits FSP or to call the payload, new page tables in the respective stage will be linked. The advantages of this approach are: - No need to determine a good place for page tables in CBFS that does not overlap. - Works with non memory mapped flash (however all coreboot targets currently do support this) - If later stages can use their own page tables which fits better with the vboot RO/RW flow A disadvantage is that it increases the stage size. This could be improved upon by using 1G pages and generating the pages at runtime. Note: qemu cannot have the page tables in the RO boot medium and needs to relocate them at runtime. This is why keeping the existing code with page tables in CBFS is done for now. TEST: Booted to payload on google/vilbox and qemu/q35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28soc/amd/noncar: Increase bootblock size from 64K to 128KArthur Heymans
When linking in page tables more place is needed. Size the bootblock is top aligned, this has no impact the final size for existing setups. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I23f176d63d3c303b13331a77ad5ac6c7a19073d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-28soc/amd/non_car/memlayout_x86.ld: Top align the codeArthur Heymans
This does the following: - Top align the bootblock so that the only the memory needed gets used. This might slightly reduce the time the PSP needs to decompress the bootblock in memory - Use a memory directive to assert that the 16bit code is inside the top 64K segment - Use the program counter less. While the BDF linker is happy about running the program counter backwards, LLD is not. There is no downside to this. - Use a symbol rather that the program counter for sections. LLD gets confused when (.) is used along with '<': it places the section at the start of the memory region, rather than at the program counter. Using a variable name works around this. - Use a 'last_byte' section to make sure the first instruction is at 0xfff0. Both the BDF and the LLD linkers seems to work well with this code TEST: Both BFD and LLD are able to link the bootblock Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-28security/vboot: extract secdata_tpm{1,2}.cSergii Dmytruk
Most of the original secdata_tpm.c was TPM2-specific implementation. Just moving the code around, with trivial tweaks: - drop now unnecessary #ifdef directives from _factory_initialize_tpm() - drop leading underscore from _factory_initialize_tpm{1,2}() (external identifiers should not start with an underscore in C) - drop unused <security/vboot/tpm_common.h> include and sub-includes of tss.h which should be considered its part (so this isn't an indirect inclusion) - fixed formatting of RETURN_ON_FAILURE() which didn't have slashes aligned no matter what tab width was used Change-Id: I0090b748d7d3b2d76a941b87b5885682fd81c4fc Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81415 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28security/tpm: replace CONFIG(TPMx) checks with runtime checkSergii Dmytruk
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2 during compilation, in which case actual TPM family in use can be determined at runtime. In some places both compile-time and runtime checks are necessary. Yet in places like probe functions runtime state checks don't make sense as runtime state is defined by results of probing. Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28security/tpm: resolve conflicts in TSS implementationsSergii Dmytruk
No functional changes. Refactor code such that there won't be any compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled in. One might want to support both TPM families for example if TPM is pluggable, while currently one has to reflash firmware along with switching TPM device. Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-28security/tpm: make tis_probe() return tpm_familySergii Dmytruk
Via an out parameter. This is needed to be able to dynamically pick TSS implementation based on the information discovered on probing. Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69159 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28soc/mediatek: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-28lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_paramsAshish Kumar Mishra
For dram_type 21 the switch case in use_ddr4_params function falls to default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block for dram_type 21 in the function. With this patch below NOTE will not be observed in the log: [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params BUG=None BRANCH=None TEST=Boot brox SKU1/SKU2 and verify logs for default case Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-27arch/riscv: remove misaligned load/store/fetch handlingRonald G Minnich
Testing on the unmatched shows the code no longer works completely correctly; Linux has taken over the handling of misalignment anyway, because handling it in firmware, with the growing complexity of the ISA and the awkward way in which it has to be handled, is more trouble than its worth. Plus, we don't WANT misalignment handled, magically, in firmware: the cost of getting it wrong is high (as I've spent a month learning); the performance is terrible (350x slowdown; and most toolchains now know to avoid unaligned load/store on RISC-V anyway. But, mostly, if alignment problems exist, *we need to know*, and if they're handled invisibly in firmware, we don't. The problem with invisible handling was shown a while back in the Go toolchain: runtime had a small error, such that many misaligned load/store were happening, and it was not discovered for some time. Had a trap been directed to kernel or user on misalignment, the problem would have been known immediately, not after many months. (The error, btw, was masking the address with 3, not 7, to detect misalignment; an easy mistake!). But, the coreboot code does not work any more any way, and it's not worth fixing. Remove it. Tested by booting Linux to runlevel 1; before, it would hang on an alignment fault, as the alignment code was failing (somewhere). This takes the coreboot SBI code much closer to revival. Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81416 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-27mb/google/nissa/var/anraggar: Modify the GPP_F15 of pen to EDGE_BOTHQinghong Zeng
Currently, simply changing the wake event configuration to ANY does not completely resolve the issue of inserting a pen not waking the system. The pen actually needs to wake up the system both when plugged in and when pulled out. This is because in the pen's GPP_F15 configuration, the original attribute is EDGE_SINGLE, which should be changed to EDGE_BOTH. BUG=b:328351027 TEST=insert and remove pen can wakes system up. Change-Id: I1823afd0bcb86804227117d2d5def38788bc7387 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81441 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-27mb/google/brya: Create yavista varianthsueh.rasheed
Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA. Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Signed-off-by: Hsueh Rasheed <hsueh.rasheed@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80342 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-27soc/intel/xeon_sp/spr: Enable x86_64 supportArthur Heymans
Fix compilation errors when compiled for x86_64. Test: Booted on ibm/sbp1 to linux payload. Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81280 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-27mb/purism: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I2285d1bdaa2734658ca1a0cc58ef2294d90d333e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-03-27mb/google/brox: Fix GPE_EC_WAKE configurationKarthikeyan Ramasubramanian
Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration. BUG=b:329026602 TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up using EC generated events like AC connect/disconnect. Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2024-03-26mb/msi: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I4a678b433e3e1a492e2a8e679caf75f4741317cb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81485 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/google/butterfly: Fix compiling for 64bit modeArthur Heymans
Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-26mb/razer: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I2c8cc390bed3aef901d6ada19361c35928dfdb0c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81496 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/roda: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: Id039ad885d2f08bc3fe09aca740a72a5820f7fcc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-03-26mb/lenovo: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I6ece868184dd772fc2c3c472ae2172d1c34fb179 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81484 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26arch/x86/bootblock.ld: Align the base of bootblock downwardsArthur Heymans
Instead of using some aritmetics that sometimes works, use the largest alignment necessary (page tables) and align downwards in the linker script. This fixes linking failing when linking in page tables inside the bootblock. This can result in a slight increase in bootblock size of at most 4096 - 512 bytes. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80346 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/fb/fbg1701: Move VBOOT key locationArthur Heymans
Move it downwards allows for a larger bootblock, which comes in handy if romstage or page tables are linked inside the bootblock. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80347 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26util/xcompile: Add target architecture to CPPFLAGSArthur Heymans
In order to preprocess linker scripts the target architecture needs to be specified. With clang this needs to be set via a cli argument. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-26drivers/intel/fsp2_0: Avoid unnecessary extra CBFS accessJeremy Compostella
fsp_mrc_version() function does not need to perform a CBFS access to to get an address to the FSP-M blob as the caller, do_fsp_memory_init(), already has it loaded. In addition to make the code simpler, it avoids an unnecessary decompression of the FSP blob if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set. TEST=Verified on Meteor Lake rex Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81256 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-03-26soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4Li, Jincheng
FSP2.4 and previous FSP versions have different FSP-T UPD parameter settings. Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26soc/intel/xeon_sp: Share DDR codes across Xeon-SP platformsJincheng Li
DDR support codes across generations are similar. Share the codes to improve code reuse. TEST=intel/archercity CRB Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-25arch/riscv: add new SBI callsRonald G Minnich
This is just a start. We are playing catch up. 7 down, 70+ to go. Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-24mb/google/veyron_{mickey,rialto}: Remove return statement in void functionElyes Haouas
Return statement is not useful in void function. Change-Id: I8cf020de335e4da933b7bbdc27b7ac6f31afe885 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81430 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24soc/intel/common/block/cse: Remove return statement in void functionElyes Haouas
Return statement is not useful in void function. Change-Id: Idb8e07f48043452b329d255fe457f00317c017ae Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81429 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24soc/intel/alderlake: Attach timestamp around eSOL callSubrata Banik
This patch adds timestamp start/end entries around the eSOL implementation to track the panel initialization time while rendering the eSOL screen. TEST=Able to build and boot google/omnigul. 555: started early sign-off life (eSOL) notification 643,694 (40) 556: finished early sign-off life (eSOL) notification 1,072,143 (428,449) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-24commonlib: Add timestamp entries for eSOLSubrata Banik
This patch adds timestamp entries for eSOL (early Sign-Off Life). This is critical to tracking the panel initialization time while rendering the eSOL screen. TEST=Able to build and boot google/omnigul. 555: started early sign-off life (eSOL) notification 643,694 (40) 556: finished early sign-off life (eSOL) notification 1,072,143 (428,449) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81386 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23soc/amd/common/noncar/memmap: reduce visibility of memmap_early_dramFelix Held
The memmap_early_dram struct is now only used inside the non-CAR memmap.c, so move the struct definition there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id2bb3d3a9e01e9bae9463c582cb105b95c673a38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-23soc/amd/common/cpu/noncar/memmap: use VGA MMIO defines everywhereFelix Held
Only the VGA MMIO range used the VGA_MMIO_* defines, but instead of using constants for the end of the region before that and the beginning of the region after that, the VGA_MMIO_* defines can be used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45c3888efb942cdd15416b730e36a9fb1ddd9697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-03-23soc/amd/common/cpu/noncar/memmap: make local variables constFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If3424df80655a150f27c7296a5683b528873816b Reviewed-on: https://review.coreboot.org/c/coreboot/+/81390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-03-23soc/amd/*/memmap: factor out common read_lower_soc_memmap_resourcesFelix Held
Since the code for reporting the memory map below cbmem_top is basically identical for all non-CAR AMD SoCs, factor this out into a common read_lower_soc_memmap_resources implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81389 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-23drivers/i2c/tas5825m: Allow using I2C busTim Crawford
The latest Clevo boards connect the TAS5825M to one of the I2C connections instead of the SMBus connection. The I2C ops are compatible with SMBus, so always use them. Tested on system76/oryp6 (uses SMBus) and in-development system76/oryp12 (uses I2C3). TAS5825M init is successful and speaker output works. Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-23soc/intel/xeon_sp/spr: Move XHCI code into southbridge folderPatrick Rudolph
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs. TEST=intel/archercity CRB Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-23soc/intel/xeon_sp/spr: Drop unused definesPatrick Rudolph
Since there's no code using those defines drop them. TEST=intel/archercity CRB Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81369 Reviewed-by: Jincheng Li <jincheng.li@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-23soc/amd/genoa_poc/domain: refactor read_soc_memmap_resourcesFelix Held
To bring genoa_poc more in line with the other AMD SoCs, move the reporting of the memory map up to cbmem_top from the openSIL-specific add_opensil_memmap function to read_soc_memmap_resources. This is a preparation for making this code common for all newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23src: Add missing SPDX license headersNicholas Chin
Other files in the commits that added these files were licensed under GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that as the license. Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81421 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23drivers/intel/ish: Include stdbool.h to identify bool typeKarthikeyan Ramasubramanian
When the concerned chip.h file is included in a source file, it causes compilation error saying unknown type name bool. Fix it by including the stdbool.h file in the chip.h file. BUG=None TEST=Build Brox by including the chip.h file in one of the source files. Change-Id: I4159e2c281c3e89dc45555ce38ad8637a3bf8587 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-22arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFGRonald G Minnich
Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. The SiFive FU540 and FU740 do not support this register; set the variable to n for those parts. Add constants for this new CSR. Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: add debug output for unused chipFelix Held
Print that the MPIO chip of one of the MPIO-related PCI device functions is unused and is skipped, if the type is IFTYPE_UNUSED and the corresponding PCI device function isn't enabled. This allows to differentiate between this case and the case where the type isn't IFTYPE_UNUSED. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4fc28d39a229494b487b300b28f92bf3adad66f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22vc/amd/opensil/genoa_poc/mpio: fix unused MPIO chip warningFelix Held
When the chip of one of the MPIO-related PCI device functions has the type IFTYPE_UNUSED, there is no corresponding MPIO engine, so replace 'engine' with 'chip' in the warning. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f55a3f8e1d220d4eb7b0287d03b7af2e5d2889f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22vc/amd/opensil/genoa_poc/mpio: use device status for port_presentFelix Held
Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE macro parameter when the device is enabled; otherwise report the port as disabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81342 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: simplify per_device_config argumentsFelix Held
Since we're already passing a pointer to the corresponding device to per_device_config, we don't need to pass the chip_info as separate parameter. Before moving the PCIe port function device below the MPIO chip, the chip_info struct was from a different device, so that change allows this simplification. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chipFelix Held
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook: Correct alphabetisation of Kconfig optionsSean Rhodes
Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/starlabs/starbook/adl: Set RP9 detection timeout to 50msSean Rhodes
Certain SSDs are not detected in the default time window, so change this to 50ms to allow these SSDs to be detected. Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIOSean Rhodes
The CPU port is not used so disable it. Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO commentsSean Rhodes
Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"Sean Rhodes
This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881. This was originally assumed to be an FSP/Descriptor/PMC mismatch but it turns out that the problem was coreboot incorrectly detecting ASPM support on devices. Revert so that a proper fix can be applied. Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/adl: Correct the layoutSean Rhodes
Adjust the size of the ME partition to match the descriptor Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/{adl,rpl}: Disable CNViSean Rhodes
No variants were ever built with CNVi cards, so disable this device. Change-Id: I3725465eae0c7ade3dafa03add151353818ee761 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22soc/intel/xeon_sp: Include soc_util.h in Xeon-SP common codesShuo Liu
Different SoC generations might have different FSP header files. It is recommended to put these uncommon header files in soc_util.h so that Xeon-SP codes refer to soc_util.h to include them in a clean way. TEST=intel/archercity CRB Change-Id: Icfc20921efe00bc69b0c16c665f65f5baae4c309 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81229 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22vc/intel/fsp/twinlake: Add FspProducerDataHeader.h headerRonak Kanabar
This patch is to add FspProducerDataHeader.h header file to support MRC version Info in TWL. BUG=b:296433836 Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81037 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-22soc/intel/alderlake: select UDK_202111_BINDING for ADL-NRonak Kanabar
ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N SoC. BUG=b:296433836 TEST=Able to build and boot google/crassk. Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80274 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/lenovo/s230u: Fix compiling for 64bit modeArthur Heymans
This fixes the warning when an integer is cast to a pointer of a different size. Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-22vc/intel/edk2-stable202111: Resolve compilation error in EDK2 202111Ronak Kanabar
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used with UDK_202111_BINDING Kconfig. Compilation error: src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25: error: static assertion failed: "sizeof (L\'A\') does not meet UEFI Specification Data Type requirements" src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25: error: static assertion failed: "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements" BUG=b:296433836 TEST=Able to build google/crassk with UDK_202111_BINDING. Change-Id: Ib2716436a910b43a5e546afdedb9eec88c5da8c6 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81328 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 11:04:52 +0000