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2019-10-24acpi: Drop wrong _ADR objects for PCI host bridgesElyes HAOUAS
Found-by: ACPICA 20191018 Change-Id: I81286d89da933b503f605737f28772bfb08483a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36253 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Improve DRAM calibration logsYu-Ping Wu
- Add macro dramc_err. - Some log levels are changed. - Some messages are improved for readability. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Correct continuation line indentYu-Ping Wu
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I9d01d24d3494f2eb28cfb411e13adf3b6717d191 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36285 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/intel/fsp_baytrail: use designware I2C driverUwe Poeche
Refactor I2C driver for fsp_baytrail to match the coreboot supported I2C bus device structure. The internal I2C controllers are now handled by the generic PCI driver approach and generic I2C access is enabled. As orientation for the I2C code the actual solution from soc/intel/apollolake I2C was taken. All the I2C specific parts were removed from lpss.c and have been implemented in the I2C driver. Future merge to soc/intel/common/block/i2c/i2c.c would be possible. With this patch I2C chip devices can now be used in devicetree. TEST=Booted siemens/tcu3 and verified that access to PTN3460 worked. Change-Id: I3b87bd7c27e4c1afcce7cd4225cca02599f43c60 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-24soc/mediatek/mt8183: Force retraining memory if requestedHung-Te Lin
To allow retraining memory without hotkey (for example in manufacturing process), we want to enforce re-training when the recovery reason is set to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running "crossystem recovery_request=0xc4"). The special reason was created for X86 MRC cache, for ensuring RO calibration data is filled (the underlying implementation was in vboot, not coreboot); and on MT8183 we have only RW calibration, but it seems totally fine to extend that for RW. BRANCH=kukui BUG=None TEST=boots; crossystem recovery_reason=0xc4; reboot Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-24arch/acpi.h: Use of typedef for acpi_vfctHimanshu Sahdev
Use of typedef and modify the usage accordingly. Change-Id: I875ef2fa31e65750233fa8da2b76d8db5db44f2d Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-24arch/acpi.h: Use of typedef for acpi_vfct_image_hdrHimanshu Sahdev
Use of typedef and modify the usage accordingly. Change-Id: I65581702a60dbd286cb3910c6eeef5f9e1853cf1 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-24soc/intel/skylake: search for PME wake event on all root portsMichael Niewöhner
Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist. Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24mb/supermicro/x11-lga1151-series: enable SLP_S0 as vendor doesMichael Niewöhner
This enables SLP_S0 for x11 boards. Change-Id: I7240ed631bf72b1d3c9ea887da43772781c80b45 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24mb/lenovo/t410/board_info: Add release year fieldPeter Lemenkov
Change-Id: I24b92977ab1259159d2d21dfb355ea5d53bfb141 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36204 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24cpu/intel/common: Enable GetSec leaves for Intel TXTPatrick Rudolph
Similar to VMX and SMX also enable all GetSec leaves for Intel TXT. Change-Id: I89620c2a98cfceaa785b1a798fafbf35cc99a0b2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-24soc/intel/fsp_broadwell_de: Add function to set DPRPatrick Rudolph
Add code for FSP Broadwell DE to set the DPR. Used by the Intel TXT code. Tested on Intel Broadwell DE using Intel TXT. Change-Id: Ib5e1ba8731e5cea1be9319a1fb9658dba841dc7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-23soc/intel/skylake: lock AES-NI MSRMichael Niewöhner
Lock AES-NI register to prevent unintended disabling, as suggested by the MSR datasheet. Successfully tested by reading the MSR on X11SSM-F Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35188 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set_optionArthur Heymans
Avoid searching for cmos_layout.bin each time get/set_option is called on platforms with NO_CAR_GLOBAL_MIGRATION. Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-23mb/supermicro/x11-lga1151-series: add x11ssm-f boardMichael Niewöhner
This adds another x11 series board, the X11SSM-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and Ethernet interfaces. Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner
2019-10-23mb/{lenovo/x201,packardbell/ms2290}/acpi: Merge common platform ASL codeVladimir Serbinenko
This code in reality just describes the southbridge features, don't put a copy in every mainboard. This commit follows up on commit e288758b with Change-Id I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 ("bd82x6x: Merge common platform ASL code"). Change-Id: Ic5260461165b794a13efd2c6d968c953f60dd253 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36229 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23soc/mediatek/mt8183: Fix incorrect usage of sizeofYu-Ping Wu
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: Ic2f6bfaf42aed642e1d7d6aba5db373944eb8ef6 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-23soc/mediatek/mt8183: add dphy reset after setting lanes numberJitao Shi
Add dphy reset after setting lanes number to avoid dphy fifo error. BUG=b:139150763 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-23soc/mediatek/mt8183: fine tune the phy timingJitao Shi
To fix MIPI D-PHY test failure, the hs-prepare should be less than LimitMin from spec, and we have to enlarge TEOT margin. BUG=b:138344447 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-23mb/lenovo/t410/dock: Remove unused includesPeter Lemenkov
Change-Id: Ia1df27b6d946d8ef5252cc35bb4fcaaabedbe2c7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22mb/lenovo/t410/early_init: Remove unused include delay.hPeter Lemenkov
Change-Id: I22b78a976c6ea43caa326e990a3c3333fef99d61 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-22mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatchKane Chen
On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode. VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted. This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can program related setttings to save power. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: Ia02ff8823883489b36349457213409496f082f36 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-22soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBEKane Chen
The previous code actually set SlpS0WithGbeSupport even when GBE is disabled in device tree and could cause power consumption in s0ix. This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport, PchPmSlpS0Vm075VSupport by device tree. SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-22soc/nvidia/tegra124: Fix null pointer and logic bugJacob Garber
Commit 680027edf6 fixed a null dereference and logic bug in the tegra210 spi code: soc/nvidia/tegra210: Fix potential NULL pointer dereference Recent Coverity scan indicated potential NULL deference; if either spi->dma_in or spi->dma_out are NULL, the fifo_error() check could dereference a NULL pointer. Also fixed what appears to be a logic bug for the spi->dma_out case, where it was using the todo (count) from spi->dma_in. Coverity is warning about the same problem for tegra124, so apply the same fix there. Also, add braces around a while statement. Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 124183, 124185 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platformsArthur Heymans
This follows the ICH7 datasheets. Change-Id: Ic8f6db8556662b03efead8c1b9e3074ffe24cd8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36201 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22mb/lenovo/t410/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. This commit follows up on commit 6752b615 with Change-Id I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for const structures"). Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22mb/lenovo/t410/Makefile: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. This commit follows up on commit 9265f89f with Change-Id I10b4300ddd18b1673c404b45fd9642488ab3186c ("arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class"). Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-22mb/lenovo/*/acpi: Remove unused include smi.hPeter Lemenkov
Change-Id: I995ef40a04c7705def95c2d5950be940503ee5ab Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-22google/chell: Update ICC_MAX configurationMatt DeVillier
Correct ICC_MAX values per SKL-Y EDS spec. Adapted from chromium commit 1c4e89e8 [Chell: Update ICC_MAX configuration] Original-Change-Id: Ic660cc6a2d11e995a86a30ddde800d096d93e012 Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/593715 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ia31ce432cf979d574d84e9205a287f87de5de057 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2019-10-22mb/google/drallion: Change touch enable pin default valueEric Lai
Change GPP_B21 default to low. This can prevent power leakage of non-touch sku. BUG=b:142849034 BRANCH=N/A TEST=Measure the power of non-touch sku, check GPP_B21 is 0V. Boot up with touch sku and check touch functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
2019-10-22mb/mainboard/hatch: support Goodix touch panel for AkemiPeichao Wang
Configure enable pin GPP_D9 pull high when active BUG=b:143046441 TEST=build bios and verify touch screen works fine Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186 Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22mb/portwell/m107: Clean up unused Kconfig symbolsArthur Heymans
Change-Id: I9714b197ff0d1af834aa29f96b33809396f0b203 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36196 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22mb/google/octopus: Override VBT selection for BloogletTony Huang
Share the same vbt_blooguard.bin to disalbe DRRS support. BUG=b:143045247 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is blooglet. Change-Id: Ia180f265080f801a09f10ce8a8b520c47f218775 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-10-22AUTHORS: Move src/drivers/[l*-v*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22vc/amd/agesa/f16kb: Cast to UINT64 to avoid overflowJoe Moore
Evaluated using 32-bit arithmetic, then used in a context that expects an expression of type UINT64. Cast to UINT64 instead. Change-Id: I4f0aa26e116b47505633897c790ca8e86ea5dc4e Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22vc/amd/agesa/f16kb: Remove redundant value assignmentJoe Moore
Code sets `Status = TRUE` in section of code that can only be reached if `Status == TRUE`. Change-Id: Id9a49476d17a5ca141994b0d5dfc5e5c62a00f0e Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22sb/intel/common/smihandler: Fix compilation on x86_64Patrick Rudolph
Use uintptr_t instead of uint32_t to fix compilation on x86_64. Change-Id: I5584f849202c0a833c751a80bdd9a8f86c60169a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36172 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22mb/supermicro/x11-lga1151-series/x11ssh-tf: move usb to overridetreeMichael Niewöhner
Move USB ports from the common devicetree to the variants' overridetree as they differ at least for X11SSH-TF and X11SSM-F. Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21drivers/intel/fsp2_0: Add ENV_CACHE_AS_RAM check for consumed rangesMarshall Dawson
Rename the freeranges array to better match what they represent, i.e. ranges that are used by the current running program and CAR region that is not unallocated. Skip adding the CAR region if cache-as-RAM is not active. Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21soc/amd/picasso: Add audio processorMarshall Dawson
Add a driver that can properly configure the pads needed to run the correct audio mode. I2S requires the 48M oscillator enabled regardless of an external connection. Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-21mb/intel/kunimitsu: drop support for FSP 1.1Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - drop FSP-1.1-only romstage.c and spd.c TODO: - testing Change-Id: I9d312ac959a7dac4b018d5ca1d007b1347bcf1dd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21mb/google/glados: port to FSP 2.0Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - switch to using the FSP default VBT TODO: - testing Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21soc/skl/vr_config: Add VR config for SKL-S/H/U/YMaxim Polyakov
Icc/Loadline automatic detection is supported only for FSP2.0 These changes are in accordance with the documentation: [*] S-Platforms, Document Number: 332687-008EN [*] H-Platforms, Document Number: 332986-010EN [*] U/Y-Platforms, Document Number: 332990-008EN Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>'Elyes HAOUAS
Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21soc/mediatek/mt8183: Force DRAM retraining if hotkey pressedYu-Ping Wu
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21soc/mediatek/mt8183: Skip fast calibration in recovery modeYu-Ping Wu
SoC DRAM team suggested always running full calibration mode in recovery mode because it is possible to get unstable memory even if the complex memory test has been passed. Since the recovery mode runs from RO and we only have training data cache for RW, the trained calibration data can't be saved since RO and RW may be running different firmware. Also revised few message to make it more clear for what calibration mode (fast, full, or partial) has been executed. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21mb/google/hatch/var/dratini: Add ELAN touchscreen supportWisley Chen
Add ELAN EKTH6915 USI touchsreen support. BUG=b:139392144 TEST=check touchscreen work, and confirmed power sequence with vendor. Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21Revert "soc/intel/cannonlake: Remove DMA support for PTT"Jeremy Soller
This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c. Reason for revert: Breaks boot on Whiskey Lake-U boards Both System76 and Purism have had memory initialization failures when this patch is applied, with the following error message: Failed to accommodate FSP reserved memory request! An extra 4096 bytes needs to be reserved for the FSP on these systems, and reinstating the PTT reservation does this as expected. PTT is enabled for the System76 galp3-c in the ME configuration, which is why the behaviour is different. Signed-off-by: Jeremy Soller <jeremy@system76.com> CC: Matt DeVillier <matt.devillier@gmail.com> CC: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21sc7180: Provide initial SoC supportT Michael Turney
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-21google/poppy: add VBT for nautilus variantMatt DeVillier
Add data.vbt and modify Kconfig appropriately; allows use of FSP/GOP display init. VBT extracted from stock ChromeOS firmware. Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-21purism/librem_bdw: hook up libgfxinitMatt DeVillier
Test: build/boot Librem 13v1, 15v2 with libgfxinit Change-Id: Ia108314b6ab9a01e898e1a8b0022aa4a0d8788be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36108 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21sb/lynxpoint: Fix 'dead increment'Elyes HAOUAS
Dead increment spotted out using clang-tools. Change-Id: I631524b9346647048fe8ea30387553a5b4651f59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-21mb/google/hatch/akemi: disable unused devices for AkemiPeichao Wang
Akemi unused devices declare: - I2C #1 gpio_keys - close I2C #3 - close GSPO #1 BUG=b:142800988 TEST=Reboot stress test and suspend stress test, the DUT will be able to working properly Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086 Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21mb/facebook/fbg1701: rename mainboard.h to logo.hWim Vervoorn
Renamed mainboard.h to logo.h as it only contains logo related items. BUG=N/A TEST=tested on fbg1701 Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-20soc/amd/picasso: Increase max APCB images to 5Marshall Dawson
An important piece of information contained in the APCB is a copy of SPD-type data to use for soldered down memory. The amdfwtool has been updated with the ability to build five APCBs into the PSP's BIOS Directory Table. Modify Picasso's Kconfig and Makefile.inc to take advantage of the flexibility, and pass the correct instance ID to amdfwtool. Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20drivers/intel/fsp2_0: Make vbt_get() conditionalMarshall Dawson
Skip calling vbt_get() if FSP is not supposed to run GOP. Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiBV Sowmya
The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses the same stack provided by coreboot. This patch updates it to 129KiB since the default value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). BUG=b:140268415 TEST=Build and boot CML-Hatch. Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Correct a few GPIO namesMarshall Dawson
Fix a handful of errors that slipped through in 2e0f2788 "soc/amd/picasso: Update GPIO configuration". Change-Id: I5784ab3cd95abc28fdc80a3815d0a52d955cff26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36118 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src/soc/amd/common: Add Azalia support to HDAMarshall Dawson
Let the mainboard decide whether to let coreboot load the verb table. Change-Id: I8f05ac02f690a43ada470916f5292b83aeaa8a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35274 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20pci_ids: Add AMD Family 17h ACPMarshall Dawson
Add Picasso's Audio Coprocessor Change-Id: I3f49a61125f0a25db9f43bf2b27c9c68f21d1594 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36116 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Add cpuid for older deviceMarshall Dawson
Make the driver work with stepping=0. Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35273 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20vc/amd/fsp: Add UPD header files for picassoMarshall Dawson
Add files for Picasso's FSP UPD definitions. These are automatically generated from the FSP build. Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20cbmem: Add IDs for TSEG and BERT table dataMarshall Dawson
Prepare for products that can use any DRAM for TSEG. Include an ID for data pointed to by an ACPI BERT table. This region's only requirement is it is marked reserved. Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36115 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Adjust I2C ASLMarshall Dawson
Clarify names as I2C2, etc. Use iomap.h defines for base addresses. Update IRQs. Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update iomapMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33991 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Update UARTsMarshall Dawson
Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Add display identification and vbios nameMarshall Dawson
Add Picasso's Device ID and default filename. Only a single Device ID is documented for Picasso so remove the oprom remapper function. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34422 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Remove unused SATA configurationsMarshall Dawson
Picasso's SATA controller operates only in AHCI mode. Remove the Kconfig symbols previously used to select between other possibilities. Change-Id: Iaeb8b4a2540e976d2e7361faf8c6d261e60398fd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Remove SATA from AOAC registersMarshall Dawson
SATA is no longer defined in AOAC so remove its definitions. Change-Id: Ief0ab6b5f69f2d17c11d8e2ee40941ac56c077f6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update southbridgeMarshall Dawson
Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/common: Add AcpiMmio access for SMBus PCI deviceMarshall Dawson
The standard PCI register space for D14F0 is accessible at 0xfed80000. Add functions for use as helpers. Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/common/lpc: Add SuperIO decode functionMarshall Dawson
The LPC-ISA bridge supports two ranges for SuperIO control registers. Add a generic function to allow a mainboard to enable the appropriate range. Provide #define values that are more descriptive than the register's field names. Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20soc/amd/picasso: Update for USB3.1Marshall Dawson
Change to the appropriate device IDs. Remove the ehci resource call. Remove overcurrent settings, as this will be passed to AGESA in later change. Remove unused USB2 ACPI name assignment. Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update all PSP and amdfw.rom buildingMarshall Dawson
Add Kconfig options and Makefile command line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are not public information. See NDA document PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20superio: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20superio: Remove unused include <device/smbus.h>Elyes HAOUAS
Change-Id: Ic8a28493c386c0097dbf3478e6d046fdfbf28724 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20security/memory: Add x86_64 supportPatrick Rudolph
Fix compiler warning by adding an additional check for the fastpath memset. Change-Id: I9a80438995bafe7e436f3fe2180b8c9574eeff23 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35682 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20mb/lenovo/x200: Add ThinkPad X301 as a variantBill XIE
It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-19mb/lenovo/x201/dock.c: Use common southbridge gpio codeArthur Heymans
Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36128 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-19mb/lenovo/x200/dock.c: Use common southbridge gpio codeArthur Heymans
Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-18mb/google/octopus: Create Dood variantTim Chen
This commit creates a dood variant for Octopus. The initial settings override the baseboard was copied from variant bobba. BUG=b:141960652 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-18src: Remove unused include '<device/pci_ids.h>'Elyes HAOUAS
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18build: Mark bootblock files on x86 as IBBPatrick Rudolph
* Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-18util/cbfstool: Add optional argument ibbPhilipp Deppenwiese
* Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/intel/common: lpc/espi: fix wrong lock bitMichael Niewöhner
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-18superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.aslPavel Sayekat
This port is based on NCT6776 Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory supportFrans Hendriks
FBG-1701 revision 1.3 will use Kingston onboard memory. Add Kingston SPD file. When Samsung memory configuration is disabled use cpld_read_pcb_version() for using correct SPD data. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 revision 1.3 Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792 Reviewed-by: Wim Vervoorn Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18superio/smsc: Restore sio1036Marshall Dawson
Change d3a1a417 "src/superio: Remove unused superio chips" removed all unused devices except for ones used on mainboards still under review. The SMSC 1036 was inadvertenly also removed as well. This device is used in debug cards that may be connected to AMD CRBs. This patch restores the smsc1036 directory as-is and then corrects the following lint messages. * WARNING: Prefer 'unsigned int' to bare use of 'unsigned' * ERROR: else should follow close brace '}' * WARNING: braces {} are not necessary for single statement blocks Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/facebook/fbg1701: separate cpld supportWim Vervoorn
Move all code involving the cpld to a single file. Rename mainboard_read_pcb_version() to cpld_read_pcb_version(). BUG=N/A TEST=tested on fbg1701 board Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/google/hatch/var/dratini: Update DPTF parametersWisley Chen
The change applies the DPTF parameters. BUG=b:142849037 TEST=build and verified by thermal team Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-18soc/mediatek/mt8183: Compress calibration blob with LZ4Hung-Te Lin
The DRAM calibration blob can be compressed using pre-RAM algorithm (currently LZ4), which will save ~12ms in boot time. On Kodama, boot time difference: Before: 1,082,711 After: 1,070,309 BUG=b:139099592,b:117953502 TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed) BRANCH=kukui Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-18mb/google: Shrink GBB section sizeHung-Te Lin
Chrome OS firmware images have moved bitmap resources from GBB into CBFS for a long time, so the GBB should only hold firmware keys and HWID, that is usually less than 10k. ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but many recent x86 simply copy from old settings and may run out of space when we want to add more resources, for example EC RO software sync. Note, changing the GBB section (inside RO) implies RO update, so this change *must not* be cherry-picked back to old firmware branches if some devices were already shipped. BRANCH=none BUG=None TEST=make # board=darllion,hatch,kahlee,octopus,sarien Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-18mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functionsWerner Zeh
The two GPIO functions variant_gpio_table() and variant_early_gpio_table() provide the pointer to the variants GPIO table for late and early GPIO init. As these functions are variant dependent the keyword __weak must not be used as otherwise the linker might choose the tables from the baseboard. This patch removes the __weak definition making these functions overriding the general ones in baseboard/gpio.c. Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36094 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/mediatek/mt8183: Pass impedance data as a function argumentYu-Ping Wu
To make data flow more explicit, global variable 'impedance' is replaced with a local variable, which is passed as a function argument. BUG=none BRANCH=kukui TEST=Krane boots correctly Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switchHuayang Duan
The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with multiple frequencies to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequencyHuayang Duan
This patch supports voltage adjustment for each DRAM frequency, which is neccesary to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Allow modifying vddq voltageHsin-Hsiung Wang
DRAM DVFS needs to be calibrated with different vddq voltages to get correct parameters. A new API is added to allow changing vddq voltage. BUG=b:80501386 BRANCH=none TEST=measure vddq voltage with multimeter Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 03:45:38 +0000