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BRANCH=none
BUG=none
TEST=build pass and boot to oak kernel
Change-Id: I8aa9ca0fce804cc1682947b7e184781dd5d437f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9
Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9
Original-Signed-off-by: jun.gao <jun.gao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319031
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e
Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6
Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292692
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13106
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I6b05898de2d0022e0de7b18f1db3c3e9c06d8135
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e
Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6
Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292692
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13105
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BRANCH=none
BUG=none
TEST=boot to shell on Rev3
Change-Id: I77c5a8aa31ab10d82115a60bdfee1da35707619f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56
Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303207
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13103
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BRANCH=none
BUG=none
TEST=boot oak to kernel on rev1
Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae
Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18
Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292693
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The sourcecode is 99% the same. Only two lines differ, but not
in functionality.
Also rename mrccache.c -> mrc_cache.c
Tested-on: boot + suspend/resume on x220
Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14007
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The mrc_cache definition and the struct mrc_container are the same
over all intel platforms.
Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/13998
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The SST25VF064C doesn't support the auto incrementing write which
all other supported SST chips support. Allow the chips to select
their write method.
Change-Id: Ic088d35461a625469ee6973d1267d7dd11963496
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14000
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/13999
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13932
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I4497b0be6ed6c90dbb31e89013feed8ff5ff9071
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13885
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The existing MCT code proceeded to the next DRAM training phase if
the minimum lane quality standard passed for either the read or
write direction. Ensure that both pass for a given set of delay
values before proceeding to the next training phase.
Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13993
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency
must be calculated prior to DQS position training, however the read
latency calculations use read DQS delay values that have not been
set prior to DQS position training.
Set the read DQS delay values to 1UI (i.e worst case) before calculating
the read latency prior to DQS position training.
Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13995
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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A couple of arrays were not properly initialized. This
did not appear to affect operation of the codebase however
it led to some ugly values being displayed when debugging
was turned on.
Also bounds check an array index; as before this did not
appear to affect operation but was a potential point of
failure.
Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13934
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13931
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of having to supply CAR memory region during compilation
time it is possible to determine it in runtime. FSP2.0 blobs carry
a copy of UPD structure pre-populated with 'default' values. The
default value for StackSize is actually the real value blob needs.
Change-Id: I298e07bb12470ce659f63846ab096189138e594f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Different DIMM modules give different SMBIOS type 17 lengths, so we
can't use `meminfo->dimm_cnt*len' for entry struct size, otherwise
it'll give a wrong SMBIOS size when two or more different DIMMs are
installed on the machine.
Change-Id: I0e33853f6aa4b30da547eb433839a397d451a8cf
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14008
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Instead of just defaulting to disabled, remove the option for
x86 since it doesn't work there.
Change-Id: I2b84b9f866f9231943e573b873c970f420c7c9a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14017
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Change 13363 (555d6c2) introduced a bug where cbmem_add_bootmem() was
converted to use a new function. Unfortunately instead of passing a
pointer, NULL was passed due to type confusion. This change fixes that
problem by passing address of stack variable instead of NULL.
Change-Id: Ib8e1add3547cda01f71bf1dea14d3e58bdd99730
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init)
unintentionally changed the code to ignore the NVRAM setting
`tft_brightness`. Revert that hunk to restore the original behavior.
Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This adds most important MMIO reserved memory resources,
real DRAM memory resources, and some DRAM resources that
can not be used as RAM for whatever reason.
Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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UART bar gets overwritten during resource allocation stage. As result
the serial driver ends up using stale BAR so serial output does not
work. This driver simply tells resource allocator not to change BAR
of UART device.
Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Change-Id: I6a632ca7d4a19c4973c41bb102f97e0836f27a5e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13996
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Add configuration in accordance to "PCI Configuration Matrix".
Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13926
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13911
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This is the minimal setup needed to get all CPU cores enabled. That
includes sending an IPI to APs and setting up MTRRs. Microcode updates
are not performed for two reasons:
* CSE (Converged Security Engine) upgrades the microcode before
releasing reset
* Microcode update files are not available at this point in time
Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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On platforms that didn't use 32-bit addresses, enabling the
CONFIG_TRACE option (Trace function calls) would break the build due
to a cast from a pointer of a different size.
This fixes this warning:
src/lib/trace.c:29:58: error: cast from pointer to integer of different
size [-Werror=pointer-to-int-cast]
Change-Id: Iaab13c1891b6af7559ea6982ecc6e74c09dd0395
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13962
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use UDELAY_IO selected by CPU_VIA_C7, so no manual inclusion
(or secondary UDELAY implementation) is needed
Change-Id: Ib086a1bfe8ffca5757bf553c5a62a45da7a410b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i440BX boards in the chipset.
Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a port of Auron_Paine based on upstream Auron and the Auron_Paine
code originally from commit bd61dfd in Google branch
firmware-paine-6301.58.B .
Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: https://review.coreboot.org/11907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Pass memory training information to MemoryInit, so memory
training can be completed.
Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On non-x86 platforms, coreboot uses the memlayout.ld mechanism to
statically allocate the different memory regions it needs and guarantees
at build time that there are no dangerous overlaps between them. At the
end of its (ramstage) execution, however, it usually loads a payload
(and possibly other platform-specific components) that is not integrated
into the coreboot build system and therefore cannot provide the same
overlap guarantees through memlayout.ld. This creates a dangerous memory
hazard where a new component could be loaded over memory areas that are
still in use by the code-loading ramstage and lead to arbitrary memory
corruption bugs.
This patch fills this gap in our build-time correctness guarantees by
adding the necessary checks as a new intermediate Makefile target on
route to assembling the final image. It will parse the memory footprint
information of the payload (and other platform-specific post-ramstage
components) from CBFS and compare it to a list of memory areas known to
be still in use during late ramstage, generating a build failure in case
of a possible hazard.
BUG=chrome-os-partner:48008
TEST=Built Oak while moving critical regions in the way of BL31 or the
payload, observing the desired build-time errors. Built Nyan, Jerry and
Falco without issues for good measure.
Change-Id: I3ebd2c1caa4df959421265e26f9cab2c54909b68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13949
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This is a step towards isolating the timer drivers.
Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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There's no need to use a struct resource type for
fsp_find_reserved_memory(). struct resource is mainly associated
with a device and that memory is added to cbmem after memory init.
Other uses ins FSP 2.0 just use struct range_entry. Use that
instead for consistency.
Change-Id: Id7d39da1c2e23f97cdaafd7f5d281cefa6fee543
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13960
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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The FSP 2.0 implementation doesn't handle FSP modules for
SoCs that are required to be XIP. There is no notion of
"loading" in that situation where one should be copying
anything anywhere.
Additionally, the loading code does not handle overlaps within
the current running program which is doing the loading.
Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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rdev_mmap() was not followed by rdev_munmap(), thus leaking
resources. Fix the leak.
Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13958
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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The memory provided to MemoryInit() for its own usage is at the
top of the CAR region.
Change-Id: I8685b5ab138182e24123b14cac6f7b32e5e784d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13957
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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In order to enforce the semantics of struct range_entry provide
an init function, range_entry_init(), which performs the field
initialization to adhere to the internal struture's assumptions.
Change-Id: I24b9296e5bcf4775974c9a8d6326717608190215
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13956
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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For all the chipsets which were performing the following sequence:
x86_setup_fixed_mtrrs();
x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
Replace that with x86_setup_mtrrs_with_detect() since it is equivalent.
Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13936
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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Nyan is an old board that was committed before several core code
modernizations to timestamp and CBFS code. Not all of those later
patches were correctly integrated with old boards like this, and the
core code has evolved to a point where it doesn't actually boot anymore.
This patch fixes that issue and brings the Nyan boards more in line with
how later ARM platforms look.
BRANCH=None
BUG=None
TEST=My Blaze boots again.
Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717
Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328543
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13832
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Include the code to add the WRDD method to the existing
WiFi Device in the mainboard ACPI code.
BUG=chrome-os-partner:50516
BRANCH=glados
TEST=boot on chell with 'region'='us' in VPD and see that it is
properly read out by calling WRDD method on the WiFi device.
Compile for the other platforms that are modified.
Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516
Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329296
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13840
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add a country identifier field to NVS and populate it with the
call to wifi_regulatory_domain() which will (by default) do a
lookup for the 'region' identifier in VPD on a Chrome OS device.
BUG=chrome-os-partner:50516
BRANCH=glados
TEST=build and boot on chell
Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2
Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329295
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13839
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Add an ACPI file containing a generic WRDD method that is used
by Intel wireless kernel drivers to determine the country code
to be used for regulatory domain configuration of the wireless
radios.
This requires an NVS variable called 'CID1' to provide an
ISO-3166-2 alpha-2 country code or it will just return 0 instead.
This is implemented as a bare method because this needs to be
included directly into the wifi device that is defined by the
mainboard as it may have board-specific settings like _PRW that
need to be provided as well.
BUG=chrome-os-partner:50516
BRANCH=glados
TEST=boot on chell with 'region'='us' in VPD and see that it is
properly read out by calling WRDD method on the WiFi device.
Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5
Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329294
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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In ChromeOS VPD spec the right name is "region".
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/322851
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: mukesh agrawal <quiche@chromium.org>
(cherry picked from commit 21ea0663e7f3ffe3aaea6b6ce0e1216fcd9ca23e)
BUG=chrome-os-partner:50516
BRANCH=glados
TEST=build and boot on chell
Change-Id: I4ba9a9c65af3732fa263030640495ab5bea91d1f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 848f18e731eb11dd3037d12607d7364f95e64e34
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ib96036f9cd76449f170af5c3dd6ef6e8e91ded94
Original-Reviewed-on: https://chromium-review.googlesource.com/329293
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Platforms that need to initialize WRDD package with the regulatory domain
information should implement function wifi_regulatory_domain.
A weak implementation is provided here.
Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Tested-by: Hannah Williams <hannah.williams@intel.com>
(cherry picked from commit c25d7221679d1fab830d614eeabfa3436bce6ac1)
BUG=chrome-os-partner:50516
BRANCH=glados
TEST=build and boot on chell
Change-Id: I1cbdf4e940b009c74ee8ed8f4fca85f4f5c943b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 27bba336e620a2d3d331e350d4f46164e337fabc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I84e2acd748856437b40bbf997bf23f158c711712
Original-Reviewed-on: https://chromium-review.googlesource.com/329291
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Set the UPD values for MemoryInit.
* Update the FspUpdVpd.h file which specifies the parameters for
MemoryInit.
* Add the necessary values to chip.h to enable values to come from
the mainboard's devicetree.cb file
* Add the parameters to the mainboard's devicetree.cb file
* Locate the platform configuration database file (pdat.bin)
* Copy the data values from the chip_info structure into the UPDs
* Display the UPD values
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_DISPLAY_UPD_DATA=y
* Testing successful when the UPD data is displayed before the call to
MemoryInit
Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
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On Apollolake CPU memory mapping is similar to previous SoC, and
we place CBMEM right under TSEG.
Change-Id: I606f690449ba98af6e9fc3074d677c7287892164
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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UDELAY_IO is defined in src/cpu/x86/Kconfig, so it does
not need to be redefined in the AMD cpu or board Kconfigs.
Change-Id: I6676881c0ba5d1634230fc3d3c37da3afbc6fceb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13780
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The current MTRR API doesn't allow one to detect variable MTRRs
along with handling fixed MTRRs in one function call. Therefore,
add x86_setup_mtrrs_with_detect() to perform the same actions
as x86_setup_mtrrs() but always do the dynamic detection.
Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13935
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
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Add the routines to handle the UPDs for SiliconInit. Currently no
support is required.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_DISPLAY_UPD_DATA=y
* Testing successful if coreboot calls SiliconInit
Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/10012
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This romstage is minimalistic. Its goal is to set up some BARs
that FSP expects to be set and then invoke FSP driver to train
memory.
Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13805
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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On Apollo Lake SPI flash is memory mapped. The mapping is different
to previous platforms. Only "BIOS" region is mapped in contrast to
whole flash. Also, the 128 KiB right below 4 GiB are being decoded by
readonly SRAM. Fail accesses to those regions, rather than returning
false data.
Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13706
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This adds a few helper functions that are intended to assist setting
up framebuffer.
Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13802
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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FSP creates hand-off-blocks (HOBs) to exchange information with
coreboot. This adds a set of utilities to parse HOBs and extract
some useful information from them.
Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13801
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This adds Notify Phase API. This is an important call that is used
to inform FSP runtimes of different stages of SoC initializations
by the coreboot.
Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13800
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This adds SiliconInit API that is needed to be called after memory
has been trained. This call is needed to let the blob do various
initialisations of IP blocks.
Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This adds implementation of fsp_memory_init() that is used to train
memory.
Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13798
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Also re-organize some of the superio code in order
to succesfully compile the rom.
Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs.
The 10K and 40K values map to 'reserved'.
This brings the code closer to the non-FSP baytrail.
Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Split out the MTRR support into a new module: mtrr.c.
TEST=Build and run on Galileo
Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Turn on the SD controller to allow it to claim resources.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when at the UEFI shell prompt:
* After issuing:
* "connect -r"
* "map -r"
* The "dir" command displays the contents of the SD flash card
* The "drivers" command shows an SD host and SD media connection
Change-Id: I883dc87270045786ddb931bea83fc36646a128e6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If the TPM code isn't getting built in, the Kconfig symbol
CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist. This ends up creating
an invalid operating region in the ACPI tables, causing a bluescreen
in windows.
This should fix this issue:
https://ticket.coreboot.org/issues/35
"commit 85a255fb (acpi/tpm: Gracefully handle missing TPM module)
breaks Windows"
Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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This adds a few assembly lines that are generic enough to be shared
between romstage and verstage that are ran in CAR. The GDT reload
is bypassed and the stack is reloaded with the CAR stack defined
in car.ld. The entry point for all those stages is car_stage_entry().
Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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Attempt to better document the symbol usage in car.ld for
cache-as-ram usage. Additionally, add _car_region_[start|end]
that completely covers the entire cache-as-ram region. The
_car_data_[start|end] symbols were renamed to
_car_relocatable_data_[start|end] in the hopes of making it
clearer that objects within there move. Lastly, all these
symbols were added to arch/symbols.h.
Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13804
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13887
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
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The PLL multiplier value is off by one for DDR3-1866 due to a
wrong TCK value, resulting in DDR3-1600 being used by the PLL.
Needs test on real hardware !
Change-Id: I657b813889945f0d9990dd11680a3d3a25b53467
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.
This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
|
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It's mobo architecture, not a user-adjustable setting.
Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13906
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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__asm__ is more robust to compilation flags.
Change-Id: Ic7ca6e38ddd439dcfc4a62ef272ecea62416b4be
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13905
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Those options have no effect or lead to compile error on ARM due
to fundamental incompatibilities. Add proper "depends on" clauses
to hide them.
Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13904
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Instead of keeping track of all the combinations of entry points
depending on the stage and other options just use _start. That way,
there's no need to update the arch/header.ld for complicated cases
as _start is always the entry point for a stage.
Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13882
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
|
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In order to align the entry points for the various stages
on x86 to _start one needs to rename the reset_vector symbol.
The section is the same; it's just a symbol change.
Change-Id: I0e6bbf1da04a6e248781a9c222a146725c34268a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13881
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
|
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Until recently x86 romstage used to be linked at some default
address. The address itself is not meaningful because the code
was normally relocated at address calculated during insertion
in CBFS. Since some newer SoC run romstage at CAR it became
useful to link romstage code at some address in CAR and avoid
relocation during build/run time altogether.
Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
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In order to avoid collisions with other _start symbols while
grepping and future ones be explicit about which _start this
one is: the 16-bit one only used by the reset vector in the
bootblock.
Change-Id: I6d7580596c0e6602a87fb158633ce9d45910cec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13880
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
|
It's helpful to see the reset vector in objdump output. Without
it being marked executable it doesn't get displayed.
Change-Id: I85cb72ea0727d3f3c2186ae20b9c5cfe5d23aeed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13879
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Patrick at least indicated this jump after the reset
vector jump was a remnant from some construct used long
ago in the project. It's not longer used (nor could I find
where it was). Therefore, remove it.
Change-Id: I31512c66a9144267739b08d5f9659c4fcde1b794
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13878
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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This adds a set of utility functions that help load and identify
FSP blobs.
Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13797
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This adds important header files that specify calling interface between
coreboot and FSP.
Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13796
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Fill minimal info required for SMBIOS type 17.
Report
* DIMM size
* channel
* rank per DIMM
* speed in Mhz
* DIMM type
* slot
* manufacturer ID
* serial
Allows dmidecode to print the current RAM configuration.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* Linux 4.3
* dmidecode 3.0
dmidecode output:
Handle 0x0005, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 8 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR3
Type Detail: Synchronous
Speed: 1600 MHz
Manufacturer: Unknown (cd04)
Serial Number: None
Asset Tag: Not Specified
Part Number: F3-1866C9-8GSR
Rank: 2
Configured Clock Speed: 1600 MHz
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Handle 0x0006, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 8 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: Channel-1-DIMM-1
Bank Locator: BANK 0
Type: DDR3
Type Detail: Synchronous
Speed: 1600 MHz
Manufacturer: Unknown (cd04)
Serial Number: None
Asset Tag: Not Specified
Part Number: F3-1866C9-8GSR
Rank: 2
Configured Clock Speed: 1600 MHz
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13852
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Parse manufacturer id and ASCII serial.
Required for SMBIOS type 17 field.
Change-Id: I710de1a6822e4777c359d0bfecc6113cb2a5ed8e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13862
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add more manufacturer IDs for vendor:
* GSkill
* OCZ
* Transcend
Change-Id: Ic7df76b1310b2c1abea9c5d2d8fd688cb2a713b8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13863
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The code can't handle cyclic zero runs. Make sure it will never
wrap around by setting the top-most bit to constant one.
Fixes "Mini channel test failed (2)".
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13853
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Intel Speed Shift Technology is a new mechanism that replaces
Legacy P-state. ISST allows OS hints about energy/performance
preference. H/W performs the actual P-state control (autonomous)
1. Optimization frequency seclection for low residency workloads,
no longer a static knee point.
2. Optimized frequency selection for best energy to performance
trade offs.
3. Kick down frequency (from idle) fpr best responsiveness while
taking energy consumption init account.
Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits
which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes
and enable HWP accordingly.
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu and verify HWP getting enabled/disabled
using Intel P-state driver.
Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f
Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313107
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://review.coreboot.org/13835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch provides config options to enable/disable Intel SST
(Speed Shift Technology).
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu/lars, verified HWP driver load successfully.
CQ-DEPEND=CL:313107
Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/326650
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://review.coreboot.org/13843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update the DPTF configuration for the chell mainboard:
1) Enable DPTF charger control, set max current to 1975mA
according to the battery specification.
2) Enable charger effect on charger temp sensor in TRT
3) Set PL2 to 15W which is the same value configured in the CPU.
BUG=chrome-os-partner:49859,chrome-os-partner:50306
BRANCH=glados
TEST=build and boot on chell
Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c
Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329187
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13842
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add new GPIOs for touchscreen enable and reset pins and define
the one missing unconnected pin for GPP_E10.
BUG=chrome-os-partner:50518
BRANCH=glados
TEST=build and boot on chell DVT1
Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d
Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329297
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13841
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If a platform does verification of the memory init step, and it must
resume with the same slot that it booted from then it needs to set
the vboot context flag when resuming instead of booting. This will
affect the slot that is selected to verify and resume from.
BUG=chromium:577269
BRANCH=glados
TEST=manually tested on chell:
1) ensure that booting from slot A resumes from slot A.
2) ensure that booting from slot B resumes from slot B.
3) do RW update while booted from slot A (so the flags are set to try
slot B) and ensure that suspend/resume still functions properly using
current slot A.
4) do RW update while booted from slot B (so the flags are set to try
slot A) and ensure that suspend/resume still functions properly using
current slot B.
Change-Id: I77e6320e36b4d2cbc308cfb39f0d4999e3497be3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4c84af7eae7b2a52a28cc3ef8a80649301215a68
Original-Change-Id: I395e5abaccd6f578111f242d1e85e28dced469ea
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328775
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The FBC hardware for skylake does not have access to the bios_reserved
range so it always assumes 8MB is used and so the kernel will
therefore need to avoid using the last 8MB of the stolen window.
With the default stolen size of 32MB(-8MB) there is not enough space
for FBC to work with a high resolution panel.
Kernel reference:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a9da512b3ed73045253afd778e40d4298f42905b
BUG=chrome-os-partner:50396
BRANCH=glados
TEST=build and boot on chell DVT
Change-Id: I3049d7d9e7c551aad5b8fd1630d5fbd88ccb2692
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fff1f4b35e23e77cdc72c5bcc290f199494cdbbb
Original-Change-Id: If468cca5759a320f3cd2d7eb09f4bcc0117b24cb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328813
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of relying on power-on-reset values provide configuration
for all pads. PAD_CFG_NC() was used for all pads which had no nets
routed on the board. PAD_CFG_GPO(0) was used for pads which had nets
routed on the board in order to terminate them.
BUG=chrome-os-partner:50301
BRANCH=glados
TEST=Built and booted chell. Suspended and resumed on EVT.
Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9
Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327835
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13831
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Enable the EHCI and OHCI controllers.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when at the UEFI shell prompt:
* After issuing:
* "connect -r"
* "map -r"
* The "dir" command displays the contents of the USB flash drive
* A USB keyboard can issue shell commands
* The "drivers" command shows an EHCI and OHCI connection
Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Adjust the memory map to allocate MMIO from non-memory addresses.
TEST=None
Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13856
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Initialize the base addresses for:
* Power management control
* Power management status
* Reset
* Power management timer
* General-Purpose Event 0
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when:
* Register address are properly displayed by the payload
* "reset -c" performs a reset and reboots the system
* "reset -w" performs a reset and reboots the system
* "reset -s" performs a reset and turns off the power
Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13764
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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I first found the missing of #include guards when I tried to include
both sandybridge/gma.h and sandybridge/sandybridge.h, but
sandybridge.h includes gma.h in it and gives a compile error.
Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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bit (bit 10) was checked in the "SDRAM Bus Width Status" register
to determine DRAM width.
Query bit 6 instead in accordance with the Aspeed AST2050 datasheet
v1.05.
Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13807
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Improved version of
I1a115a45d5febf351d89721ece79eaf43f7ee8a0
The first version wasn't well tested due to the lack of hardware
and it was to aggressive.
With timC being direct function of timB's 6 LSBs it's critical to match
timC and timB.
Some tests increments the value of timB by a small value,
which might cause the 6bit value to overflow, if it's close
to 0x3F.
Increment the value by a small offset if it's likely
to overflow, to make sure it won't overflow while running
tests and bricks the system due to a non matching timC.
In comparission to the first attempt, only 4 out of 128 timB values
are considered bad.
Needs test on real hardware !
Fixes a "edge write discovery failed" on my test system.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/13779
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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