summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2017-10-16mb/google/fizz: enable AER for PCIe root portsKane Chen
Enable PCIe Advanced Error Reporting for PCIe root port 2, 3, 4 ,8. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21946 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16src/soc/skylake: Fix Null pointer dereferencesShaunak Saha
Fix bug detected by coverity to handle the NULL pointer dereference Coverity Issues: * 1379849 * 1379848 TEST=Build and run on skylake platform Change-Id: Iec7a88a03531bbfeb72cedab5ad93d3a4c23eef5 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21909 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16intel/common: CAR setup CQOSNaresh G Solanki
Enable CQOS on Geminilake. In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF. Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK. Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits. BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platform i.e., on Reef Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/21701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16soc/amd/common: Clean up file includesFrank Vibrans
Remove unnecessary header file includes. Change-Id: I9ad9e86f3c75903e278e898602caec04351f64b6 Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com> Reviewed-on: https://review.coreboot.org/21989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16mainboard/pcengines/apu2: use GENERIC_SPD_BINKamil Wcislo
Use GENERIC_SPD_BIN method of adding the SPD bins to final rom. Change-Id: I242e393bafac41aa7743f83b52cadf027019ee6e Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Reviewed-on: https://review.coreboot.org/21980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-16soc/amd/stoneyridge: Check UART indexMarshall Dawson
The Stoney Ridge APU has only two internal UARTs. Add checks for invalid settings. When enabling the UART, return if the console is on any UART not equal 0 or 1. The base address returned is 0 if an invalid configuration is used. All callers check the return value before using the returned value. Finally, provide an assert at the earliest availability of the console to get the notice into the cbmem console. BUG=b:62201567 TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS. Build without ST UART and inspect with objdump. Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16drivers/uart8250mem: Check for zero base addressMarshall Dawson
Before adding a new UART to the coreboot/lb table, verify that it has a non-zero base address. This is consistent with all other functions that use the uart_platform_base() function. This was tested on google/kahlee by using an invalid UART number and forcing the base address to 0. Execution was able to complete through depthcharge and into the OS. Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21996 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/stoneyridge: Update AMD firmware placement optionsMartin Roth
- Don't force the selection of placing the firmware outside of cbfs when using vboot. - Set a prompt to allow the option of placing it outside of cbfs. - Leave all Kconfig defaults the same. - Place the AMD firmware directory table in the specified location even when using the 'outside of cbfs" option. - Print where the firmware is being placed when placing it outside of cbfs. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Firmware shows up inside CBFS. Set 'outside of cbfs' option, verify firmware gets written to the correct location. Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16src/mainboard/kahlee: Default AMD FW position to 1MBMartin Roth
For Kahlee, the AMD firmware directory should be in the 1MB location so that it's in the RO cbfs section. BUG=b:65484600 TEST=Build & boot Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22003 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16arch/x86/gdt: Correct format of multi-line commentPaul Menzel
Change-Id: I87148315cdf7e420eac2f3f680251f8e963a9707 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-10-15amd/inagua: Drop unused Broadcom 5785 support codeKyösti Mälkki
Remove sample configuration code for internal Broadcom GbE device in AMD A55E aka Hudson-E1. Change-Id: Ib0262805aafc62513d9237019ade473cb1efbf1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15amd/stoneyridge: Add function to find PmControl registerMarshall Dawson
Find the PmControl register's I/O address by checking the hardware in PMx62. Don't rely on the address being the coreboot default. PmControl is the first register in the AcpiPm1CntBlk. Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15google/kahlee: Add SMI sleep handlerMarshall Dawson
Notify the EC the system is going to sleep. Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15google/kahlee: Add SMI apmc handlerMarshall Dawson
Forward the apmc call to the chromeec. Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15amd/soc/common: Print an error if an AGESA callout isn't supportedMarc Jones
Let the developer or user know that a callout isn't supported. Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15google/wizpig: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/wizpig (white label Chromebook) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new wizpig variant - Add new shared SPD file to the baseboard Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15google/ultima: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/ultima (Lenovo Yoga 11e G3) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new ultima variant Sourced from Chromium branch firmware-ultima-7287.131.B, commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode"" Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-15google/setzer: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/setzer (HP Chromebook 11 G5) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new setzer variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resourcesRichard Spiegel
Factor out the code into separate functions. Create set_lpc_resource that will set the resource for a particular child while lpc_enable_childrens_resources finds all children and calls set_lpc_resource for each child found. This creates well defined boundaries for each function. Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15pcengines boards: Update board_info filesMichał Żygowski
This updates board info of PC Engines platforms, changes board names to official manufacturer's names and adds info about ROM. Removing "Clone of" option for ALIX platforms makes them independent. Change-Id: Ie76d65ea84f14b9043a8e5b86678a9da4c187cc9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/21722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-14biostar/a68n_5200: Fix hang with board due to SPIDamien Zammit
SPI mode needs to be set early to normal and Quad I/O disabled on this board for some reason Change-Id: I4dbc52010eebf492087d0b1c155a24a307bcc8b0 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14biostar/a68n_5200: Do actual portDamien Zammit
TESTED on Biostar A68N-5200: boots to GNU/Linux With proprietary VBIOS, even the gfx works in SeaBIOS. Change-Id: Id44b81345ba189f82413042760d570a746294a1e Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14biostar/a68n_5200: Clone amd/olivehillDamien Zammit
Altered Kconfig board names to make it pass lint Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14intel/skylake: Use Sata related registers from devicetreeYouness Alaoui
Enable the use of the SataPortsEnable and SataPortsDevSlp registers which were being ignored from the devicetree and were not affecting the resulting UPD parameters. SataPortsEnable was only being copied for the first SATA port, while the other ports were left ignored. Change-Id: Iae70a4d6375fa5d1b05ee89f6b97c65dbbf28dda Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-13google/kahlee: Add AGESA_DO_RESET in bootblockMarc Jones
Support the required AGESA_DO_RESET in bootblock. BUG=b:64719937 BRANCH=none TEST=Check AGESA reset request in booblock does a reset in the serial console or ec console. Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13amd/stoneyridge: Make all AGESA reset requests immediateMarc Jones
The AGESA RESET_WHENEVER request were never doing a reset in coreboot. We don't have a way to collect a whenever and reset at some later time, so just do the reset immediately. BUG=b:64719937 BRANCH=none TEST=Check AGESA reset request in booblock does a reset in the serial console or ec console. Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21978 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-13google/fizz: Enable cr50 over SPIShelley Chen
We are changing the bootstraps in the EVTs so that the SOC communicates with cr50 over SPI instead of cr50. SPI is more reliable than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI. BUG=b:65056998, b:62456589 BRANCH=None TEST=make sure that we can boot into kernel run cold_reset and warm_reset and make sure both boot successfully. CQ-DEPEND=CL:714237 Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-13src/device: Update LTR configuration schemeAamir Bohra
This patch moves out LTR programming under L1 substate to pchexp_tune_device function, as substate programming and LTR programming are independent. LTR programming scheme is updated to scan through entire tree and enable LTR mechanism on pci device if LTR mechanism is supported by device. BRANCH=none BUG=b:66722364 TEST=Verify LTR is configured for end point devices and max snoop latency gets configured. Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/21868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-13google/relm: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/relm (white label Chromebook) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new relm variant - Add new shared SPD files to baseboard Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-13google/kefka: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/kefka (Dell Chromebook 11 3180) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new kefka variant - Add new shared SPD file to baseboard Sourced from Chromium branch firmware-strago-7287.B, commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13google/cyan variants: fix non-functional typo in gpio.cMatt DeVillier
Typo found/fixed in to-be-merged boards; applying same fix to already-merged boards. Change-Id: I15f97467a5442888165399be997b0b690a3c312a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13google/cyan variants: fix single/dual channel reportingMatt DeVillier
Fix typos in determining single/dual channel in cyan variants which resulted in all boards being reported as 4GB/dual channel in the cbmem console log. These typos were found and fixed in yet-to-be-merged variants; this patch applies the same fixes to already-merged boards. Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13nb/intel/*/gma: Port ACPI opregion to older platformsPatrick Rudolph
Port the ACPI opregion implementation that resides in drivers/intel/gma to older platforms. It allows to include a vbt.bin and allows GNU/Linux to load the opregion as ASLS is being set. Windows' Intel will likely ignore it as it relies on legacy VBIOS to be loaded at 0xc0000. Tested successfully on DG43GT (x4x) with vbt.bin, with X200 (gm45) with vendor option rom and D945GCLF (i945) with fake vbt. Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-13drv/intel/gma/opregion: Add common init_idg_opregion()Matt DeVillier
Add a new common method to initialize ACPI OpRegion. * Try to locate vbt.bin in CBFS. * Try to locate VBIOS in CBFS. * Keep existing code to probe at 0xc0000. Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at 0xc0000. Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS). In all cases linux was successfully provided with VBT from ACPI opregion. Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-12intel/common/pmc: Disable all GPEs during pmc_initFurquan Shaikh
If GPEs are not cleared during pmc_init, it could result in issues if standard wake events are generated while coreboot is initializing. e.g. (Observed on soraka): 1. Suspend to S3 2. Lidclose 3. Lidopen 4. EC wakes up the host using WAKE# pin 5. On wakeup, pmc_init occurs which does not clear GPEs 6. MP init enables SMI 7. In order to add wake event to elog, coreboot sets wake mask on the EC, which causes the EC to assert WAKE#. 8. Since WAKE# is asserted, it results in an SMI#. However, EC does not de-assert WAKE# until host queries and clears the host event bit (which does not happen since coreboot is stuck in handling the SMIs). This is one of the issues that can occur when GPEs are unnecessarily enabled in coreboot. Before the move to PMC common library, SKL PMC driver set all GPEs to 0 and hence this issue did not occur. This change explicitly disables all GPEs during pmc init in order to avoid any side-effects. BUG=b:67712608 TEST=Verified that device resumes fine using lidclose/lidopen to suspend and resume. Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21969 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh
1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12vboot: Exclude platform specific files from RW cbfsMartin Roth
Add a Kconfig option to allow platforms to exclude specific files from being copied from RO into RW sections. BUG=b:65484600 TEST=Exclude apu/amdfw from the RW cbfs sections Change-Id: I7723b63392c1620b75ceb6d8e25fe1ce2c75cf18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12soc/intel/cannonlake: add length information for communitiesBora Guvendik
TEST = Boot to OS, check if pinctrl probed successfully Change-Id: Ib20c955d535cd9c48175b4d3934b4699b6186874 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12mainboard/intel/cannonlake_rvp: Add Sleep statesVaibhav Shankar
Add sleep state to DSDT table. Change-Id: Ic14e34e29d5f881949765dee5c6b433c1499c491 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/21976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar
Add the required ACPI sleep states Change-Id: I7750062554f087e4f88da56790e4122d5fa20529 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/21975 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12soc/amd/stoneyridge: Clean up sata.cRichard Spiegel
Clean up ahci_ptr declaration. Remove incorrect PCI device IDs. BUG=b:62200375 Change-Id: I9058d9102fc8ea0bd03ea089ba98da4590dd3533 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21973 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12siemens/mc_bdx1: Add delay to wait for legacy devicesWerner Zeh
Like happend in commit efd0eb35af5e5620331d885d3140c734a6fc9098 (siemens/mc_apl1: Add delay to wait for legacy devices) add the feature to mc_bdx1 as it uses the same legacy devices. Change-Id: I355a53ce7aea70098d7bc08f24dc6a4e43d1d618 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-12intel/fsp_broadwell_de: Add timestamp functionalityWerner Zeh
Add a little code to enable timestamps on FSP based implementation of Broadwell-DE. I have tested it by reading back the timestamps with cbmem utility once the board has booted into Lubuntu. Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12sb/amd/sb700/lpc.c: Optimize code flow for less indentationArthur Heymans
This changes the code flow so less indentation has to be used. This also changes some lines to limit their length. Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21234 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12nb/intel/sandybridge/raminit: Fix setting scramble seed for CH1Arthur Heymans
The scramble seed intended for CH1 were written to the regs of CH0. Write the scramble seed for CH1 at the correct offset. TESTED on Lenovo T430, HP 2760P, Asrock B75PRO3-M. Change-Id: I3778947e96b3298c38e6d5b74988e617e1ffea7b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2017-10-12soc/intel/skylake: Enable bus master for sataKane Chen
The bus master needs to be enabled so that the busy bit in AHCI PORT_TFDATA will be cleared by controller when depthcharge tries to wait for sata to complete spin-up during AHCI init. Otherwise, the timeout will happen and cause 5 seconds delay in depthcharge. BUG=b:37639063 BRANCH=none TEST=verify that the sata timeout is gone in depthcharge Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-11mainboard/google/kahlee: Add EC_IN_RW flagMartin Roth
Depthcharge was complaining that the GPIO for this flag wasn't set. The GPIO also needs to be an input, not an output. BUG=b:67614692 TEST=Depthcharge no longer complains that there is no GPIO set for flag5. The system boots again. Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-11soc/intel/cannonlake: Change default UART number to 2Lijian Zhao
Set default UART number to 2 if 32bit PCI got selected, the proper debug print can be seen from serial port in case of switch between platforms, especially when change to lpss uart from legacy uart or vise versa. Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21544 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11mainboard/google/fizz: Enable Devslp for SATA port 1Gaggery Tsai
This patch is to enable the support of device sleep for SATA port 1 and disable unused SATA port 0. BUG=b:65808359 BRANCH=None TEST=Ran "suspend_stress_test -c 2500" and passed the test. Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2017-10-10vboot: use cbfstool truncatePatrick Georgi
Instead of a shell based parser for cbfstool print -k output. BUG=b:65853903 BRANCH=none TEST=`abuild -x -t GOOGLE_KEVIN -p none` creates a valid-looking image. Change-Id: I33b7e1c483a69e66e82541c09582be2a71356a10 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-10soc/intel/skylake: Fix broken suspend/resume for deep S3Furquan Shaikh
Change d3476809 (soc/intel/skylake: Add support in SKL for PMC common code) changed the logic for obtaining previous sleep state by unconditionally checking for PWR_FLR and SUS_PWR_FLR. In case of deep S3, SUS_PWR_FLR is set in gen_pmcon_b (just like resume from deep S5/G3) and hence the check for power failure should be done only when WAK_STS bit is not set. This is necessary to differentiate wakes from deep S3 and G3. This change restores the original logic by performing power failure check only in cases where WAK_STS bit is not set. BUG=b:67617726 TEST=Verified following: 1. When WAK_STS bit is not set and SUS_PWR_FLR is set, coreboot correctly identifies that the system prev sleep state was S5. 2. When WAK_STS bit is set and SUS_PWR_FLR is set, coreboot correctly identifies that the system prev sleep state was S3. Change-Id: Ic97bbc9911ba34aa21f4728c77fc20c5bb08f6f9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-10mb/google/poppy/variants/nautilus: add nautilus boardChris Wang
Create Nautilus board which derives from Poppy, a KBL reference board. BRANCH=master BUG=b:66462881 TEST=Build (as initial setup) Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-10ec/lenovo/h8: Serialize control method _CRSPaul Menzel
``` dsdt.aml 1461: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ``` Change-Id: Iaf9455b16b061b32248139a85890f49de7467261 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-09skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPIFurquan Shaikh
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09mainboard/intel/cannonlake_rvp: enable NVMe SSDBora Guvendik
Turn on PCIe express port 9 of PCIe controller 3, to enable NVMe SSD via M.2 socket 3 on RVP board. TEST=Boot to OS using Intel NVMe SSD Pro 6 Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21908 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-09soc/intel/*lake: Load vbt when it's neededPatrick Georgi
That removes the need for another global variable. Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21907 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08google/cyan: fix variant memory/silicon init params overrideMatt DeVillier
The mainboard_memory_init_params() and mainboard_silicon_init_params() methods already have weak definitions in drivers/intel/fsp1_1, so having them declared as weak in the cyan baseboard has the effect of them not being called at all unless overridden at the variant level. Therefore, remove the weak declarations in the baseboard and ensure that each variant has its own init functions if needed. TEST: build/boot google/cyan Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-08mb/google/poppy/variants/soraka: Add 10ms reset delay for WCOM deviceFurquan Shaikh
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time) removed the delay after taking device out of reset since it seemed unnecessary in system resume case (because there is enough time after taking device out of reset and before communication with device starts). However, without the delay, kernel driver runs into issue while talking to the device during boot-up and runtime suspend/resume. (Observed this error in dmesg: "i2c_hid i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms delay after taking device out of reset. Verified on multiple Soraka system that with 10ms delay, kernel driver does not run into any issue talking to the WCOM device during boot-up, runtime suspend/resume and system suspend/resume. BUG=b:65358919 TEST=No more errors talking to WCOM device in kernel dmesg. Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajat Jain <rajatja@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08ec/google/chromeec: Add library function google_chromeec_events_initFurquan Shaikh
mainboard_ec_init implemented by all x86-based mainboards using chromeec performed similar tasks for initializing and recording ec events. Instead of duplicating this code across multiple boards, provide a library function google_chromeec_events_init that can be called by mainboard with appropriate inputs to perform the required actions. This change also adds a new structure google_chromeec_event_info to allow mainboards to provide information required by the library function to handle different event masks. Also, google_chromeec_log_device_events and google_chromeec_log_events no longer need to be exported. Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-06google/zoombini: adapt to schematic changesNick Vaccaro
Adapt code to latest schematic changes, revision 1.1. Configure GPD2 for EC_PCH_WAKE_ODL, GPP_D5 for EC_I2C_SENSOR_SDA, GPP_D6 for EC_I2C_SENSOR_SCL, GPP_D7 for WWAN_SAR_INT_ODL, GPP_D9 for touchscreen power enable, GPP_D10 for wifi power enable, GPP_D11 for wwan power enable, GPP_D13 change to "No Connect" (was VOL_UP_ODL), GPP_D14 change to "No Connect" (was VOL_DOWN_ODL). BUG=b:66265441 BRANCH=None TEST=None Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21900 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/skylake: use locate_vbt directly instead of calling a wrapperPatrick Georgi
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
Instead of having all callers provide a region_device just for the purpose of reading vbt.bin, let locate_vbt handle its entire life cycle, simplifying the VBT access API. Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: refactor locate_vbtPatrick Georgi
All callers of locate_vbt just care about the file content and immediately map the rdev for its content. Instead of repeating this in all call sites, move that code to locate_vbt. Change-Id: I5b518e6c959437bd8f393269db7955358a786719 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06mainboard/google/reef: Override VBT selection in coralPatrick Georgi
Change-Id: I7fd667b1cf0b7c2a5e4ab7ac7748d9636a52ae54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: Allow overriding CBFS filename of VBTPatrick Georgi
When reusing the same image across multiple devices, they sometimes need different VBTs, so provide a hook for mainboard code to specify which file is required. Change-Id: Ic7865dc0e0c9ea3077b749d9d0482079877e9c4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21724 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/cannonlake: Enable MRC cacheLijian Zhao
Enable MRC cache by default. TEST=Warm reset and check coreboot serial log, MRC related log can be seen. Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/cannonlake: reduce bootblock sizeAaron Durbin
Reduce the bootblock size to 16KiB from the default 64KiB. Not all that space is necessary. Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-06soc/intel/common: remove invalid path from Kconfig includeAaron Durbin
The src/soc/intel/common/basecode/Kconfig path does not exist. Remove the inclusion of the invalid path. Change-Id: Icbd8f310cad4246b72bc869bcf4a089ae2f0c5a3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-06AGESA f16kb: Enable MRC cache equivalent fastbootKyösti Mälkki
Try restoring previous memory training results from SPI flash to improve raminit speed. Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05drivers/intel/fsp2_0: use common code to fetch vbt.binPatrick Georgi
No need for having two of everything in the coreboot codebase. Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao
Add all the SOC level DSDT tables, reference from skylake/kabylake. Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05soc/intel/common/block: Manage power state variable from common PMC blockShaunak Saha
This patch helps managing power state variables from within the library. Adds migrate_power_state which migrates the chipset power state variable, reads global power variable and adds it in cbmem for future use. This also adds get_soc_power_state_values function which returns the power state variable from cbmem or global power state variable if cbmem is not populated yet. Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21851 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/amd/stoneyridge: Pass firmware dir location to amdfwtoolMartin Roth
The amdfwtool now outputs firmware that is correctly built for the new location. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05src/mainboard/Kconfig: Add support for 10240 KiB ROM chipsJonathan Neuschäfer
The Dell Optiplex 790 desktop board has a logical 10MiB flash, so it needs to select BOARD_ROMSIZE_KB_10240. Provide it, so it can be used. Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-05soc/intel/{common,apollolake}: Add checks to handle negative valuesRizwan Qureshi
Fix issues reported by coverity scan in the below files. src/soc/intel/common/block/i2c 1375440: Improper use of negative value 1375441: Improper use of negative value 1375444: Improper use of negative value src/soc/intel/apollolake/i2c.c 1375442: Unsigned compared against 0 Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/skylake: Add config for mbx command for Intersil VR C-state issuesRizwan Qureshi
Config for activating VR mailbox command for Intersil VR C-state issues. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. BUG=b:65499724 BRANCH=none TEST= build and boot soraka. Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21680 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05vendor/intel/skykabylake: Update FSP header files to version 2.7.2Balaji Manigandan B
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-05mb/google/reef: Cache EC's SKU ID on CoralPatrick Georgi
Change-Id: I1925f51d63290b8d08366b622d5df3aab3a7484e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21737 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-10-05AGESA vendorcode: Add ENABLE_MRC_CACHE optionKyösti Mälkki
When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05AGESA: Re-enable HAVE_ACPI_RESUMEKyösti Mälkki
Note: For some of the boards affected ACPI S3 support was never tested but feature was just copy-paste from reference design. Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2017-10-04google/fizz: Configure GPP_C23 earlyDaisuke Nojiri
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has to be configured in early_gpio_table. BUG=b:67030973 BRANCH=none TEST=Verify by wpsw_boot and wpsw_cur match. Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04intel/fsp: Update cannonlake FSP headerLijian Zhao
Update FSP header file to latest version, cannonlake reference code 7.0.14.11. Details of FSP changes can be find in FSP release notes. Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBONDArthur Heymans
The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already includes this. Change-Id: Ib2de0f384a547240528b18f07327566354164699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-04soc/amd/stoneyridge: Drop some amdlib.h includesKyösti Mälkki
Change-Id: Ief00a74a9ab4cb6783ea17cebc924b5c4852f228 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03soc/intel/cannonlake: change gpio device nameBora Guvendik
TEST=Boot to OS Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21758 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03mainboard/google/soraka: Reduce Wacom resume timeRajneesh Bhardwaj
Currently the WCOMCOHO registers a reset delay of 110ms to execute their _ON_ asl power on method. This seems to be correct as per WACOM product design specifications but it introduces an unwanted delay in overall system resume time. This delay should be removed from ACPI critical path since the entire kernel resume gets blocked on this sleep call unless this is over. In the kernel I2C communication with WACOM driver starts with the resume callbacks of I2C HID driver which gets triggered after display is completely resumed. The display resume process takes at least 230ms so it's safe to reduce the delay from coreboot and unblock the critical ACPI path. BUG=b:65358919 BRANCH=None TEST=manual testing on Soraka board to ensure that touchscreen works at boot and after suspend/resume. Also verify that the overall S3 resume time is reduced by 110ms. Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/21692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-03soc/intel/cannonlake: Disable CPU ratio overrideLijian Zhao
Disable CPU Ratio override as input to FSP Memory init. Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik
Add ACPI methods for gpio, scs and pcr. TEST=Boot to OS. Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-03soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao
Add ACPI dsdt table for northbridge, report proper resources in dsdt entries. TEST=Boot up into OS fine. Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03mainboard/intel/cannonlake_rvp: Add smi support in boardLijian Zhao
Include SMI Handler support for Cannonlake RVP platform. Change-Id: I8f363e20a6eb92b3c05e16715aa052a8da18b509 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Fill the SMI usageLijian Zhao
Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Add lpc pci driverLijian Zhao
1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/skylake: Enable common LPC IPRavi Sarawadi
Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/common/block: Update LPC libRavi Sarawadi
Add support for following functionality: 1. Set up PCH LPC interrupt routing. 2. Set up generic IO decoder range settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03vc/amd/pi/00670F00: Remove HeapXXBuffer functionsMartin Roth
The HeapAllocateBuffer and HEAPDeallocateBuffer functions are not used in Stoney Ridge, so get rid of them. Change-Id: I716d5c8957ced52c25fd501697111b1b0b263467 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-03soc/amd/stoney: Allow alternative placement for AMD FW directoryMartin Roth
Allow the AMD FW directory to be placed at one of the alternative locations within the ROM. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03nb/intel/gm45: Remove UMA alignment optimizationNico Huber
This code path was only triggered in one corner case: GFX UMA set to 48MiB. It created a hole below UMA to save MTRRs. But, this hole was never accounted for when calculating cbmem_top(). Instead of trying to fix it, remove it, it's not worth the trouble. TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings. Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-03soc/amd/stoneyridge: Wait for UART to be readyMarc Jones
The Stoney Ridge UART and AMBA devices must be powered and report power and clock OK prior to using the coreboot serial console. The code used to have a delay to wait for the power and clock, but didn't check the OK bits. This caused long delays on a reboot, as each byte would time out until the console was reset again at romstage. This change also removes the UART reset. The device has just been powered and is in reset already. Testing indicates the reset isn't needed. BUG=b:65853981 TEST=Boot to Chrome OS, run the reboot command, verify that the long delay is gone. Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 06:26:26 +0000