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2020-11-30mb/google/dedede: Create sasuke variantRaymond Chung
Create the sasuke variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:172104731 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKE Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-30lenovo/g505s: remove the unused and not present devicesMike Banon
Remove the devices unused or not present on this laptop. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-30mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHzFrank Chu
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/intel/alderlake: Add initial chipset.cbTim Wawrzynczak
Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30include/device/pci_ids.h: Fix device id for gspi2Bora Guvendik
Device ID for "D18:F6 - GSPI #2" shoud be 0xA0FB BUG=none TEST=Boot to OS, verify SSDT Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48060 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak
Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-30elog: Add new wake source codesTim Wawrzynczak
Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-30mb/google/volteer/variant/copano: Add memory part supportNick Vaccaro
Add support for the following 5 LPDDR4x memory parts: - MT53E512M64D4NW-046 WT:E - H9HCNNNCRMBLPR-NEE - MT53D1G64D4NW-046 WT:A - H9HCNNNFBMBLPR-NEE - MT53D512M64D4NW-046 WT:F DRAM Part Name ID to assign ------------------------------------------- MT53E512M64D4NW-046 WT:E 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) MT53D512M64D4NW-046 WT:F 0 (0000) BUG=b:172993397 TEST=none Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30lp4x: Add new memory parts and generate SPDsNick Vaccaro
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. BUG=b:172993397 TEST=none Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-30mb/prodrive/hermes: Use PCH_DEV_SMBUS definitionAngel Pons
This allows dropping ugly preprocessor usage from this file. Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/prodrive/hermes: Encapsulate GPIO setupAngel Pons
Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30mb/prodrive/hermes: Use C-style commentsAngel Pons
Most of the existing comments are C-style already. Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30soc/amd/common: add comments and FIXME to Makefile.inc filesFelix Held
Change-Id: Ie347ee508acd900353467b4a3e0a5d1928b110e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47877 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/common: simplify conditionals in MakefilesFelix Held
If there are multiple statements that are conditional on the same Kconfig option, group them and move the condition check around the statement. If there's only one statement depending on one condition, use the short form instead. Change-Id: I89cb17954150c146ffc762d8cb2e3b3b374924de Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47876 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/common/block/cpu: move CAR-specific Makefile to sub-directoryFelix Held
Since there are sub-directories for both the cache-as-RAM case and the non-CAR case where the RAM is already initialized when the x86 cores are released from reset, move the CAR-specific parts of the Makefile.inc to another Makefile.inc in the car sub-directory. Further patches will add a Makefile.inc to the non-CAR directory. Change-Id: I43a3039237d96e02baa33488e71c5f24effe8359 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47875 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30drivers/intel/i210: Request Bus Master in .final opsAngel Pons
Commit bd31642ad8 (intel/i210: Set bus master bit in command register) is only necessary because a buggy OS expects Bus Master to be set, not because the hardware requires Bus Master during initialization. It is thus safe to defer the Bus Master request into the .final callback. Change-Id: Iecfa6366eb4b1438fd12cd9ebb1a77ada97fa2f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47401 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot
2020-11-30mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()Angel Pons
There's one copy of this function for all variants except mc_apl4. Move one copy into common mainboard.c and exit early if running on mc_apl4. Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logicAngel Pons
A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is considered valid. Instead of using a temporary buffer and memcmp(), use a single loop that exits as soon as the MAC cannot possibly be invalid. Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-30drivers/intel/i210: Define MAC_ADDR_LENAngel Pons
Define and use the MAC_ADDR_LEN macro in place of the `6` magic value. Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-11-30mb/siemens/mc_apl1/mainboard.c: Refactor loop bodyAngel Pons
Break down multi-line compound conditions into multiple if-statements, and leverage `continue` statements to avoid nesting multiple checks. Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-29mb/google/volteer: eldrid: use devtree aliases for PMC MUX connectorsScott Chao
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:172528109 BRANCH=firmware-volteer-13521.B TEST=built and USB3.0, type-c display work. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh
This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla
TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVPSubrata Banik
TEST=Able to pass MRC training on DDR4/5 SKUs Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-29mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_SERVERMichael Niewöhner
Set the FADT PM profile to ENTERPRISE_SERVER, since the currently supported X11 boards are server boards. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48088 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/supermicro/x11-lga1151-series: rework gpio setup to not use headersMichael Niewöhner
Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-29mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.initMichael Niewöhner
GPIO needs to be initialized before the IPMI device gets initialized, so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus, use mainboard_ops.init for GPIO configuration instead of using the indirection via a mainboard_enable function. To make it more visible, that we use chip.init, rename `mainboard_init` to `mainboard_chip_init`. Tested successfully on X11SSM-F including the IPMI changes. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28mb/supermicro/x11ssm-f: drop unneeded ITSS overrideMichael Niewöhner
The ITSS override is not needed for LPC_CLKOUT* pads. Drop it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: configure gpios in mainboard initMichael Niewöhner
Move gpio configuration from the Fsp callback to mainboard init. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: restructure and clean up devicetreeMichael Niewöhner
Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28soc/intel/skl: correct OC pin skip value for disabled usb portsMichael Niewöhner
Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to supposedly skip programming an OC pin for a disabled USB port. While the value is correct for the other platforms, Skylake uses 0x08 for this purpose. Correct this by using the enum value OC_SKIP (0x08) instead. Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-27{docs/,}mb/supermicro/x11ssh-tf: drop TODO sectionMichael Niewöhner
Drop the TODO comment, since there is no TODO left. Also drop the now obsolete TODO section from the board documentation. Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-27Makefile.inc: Move adding mcu FIT entriesArthur Heymans
This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27soc/intel/jasperlake: Enable VT-d and generate DMAR TableMeera Ravindranath
Update UPDs required for the creation of DMAR table. By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error. BUG=b:170261791 BRANCH=dedede TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-11-26drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfigMichael Niewöhner
Move the FSP FD PATH option down, so it gets shown in place of the split FD files, when the users chooses to use a full FD binary. Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26drivers/intel/fsp2_0: introduce possibility of using a full FD binaryMichael Niewöhner
Currently, setting a custom FSP binary is only possible by using split FSP-T/M/S FD files. This change introduces the possibility to pass a combined FD file (the "standard" FSP format). This is done by adding a new boolean Kconfig FSP_FULL_FD, specifying that the FSP is a single FD file instead of split FSP-T/M/S FD files, and making FSP_FD_PATH user-visible when the option is chosen. In this case, the other options for split files get hidden. When the user chooses to use a full FD file instead of the split ones, the FD file gets split during build, just like it is done when selecting the Github FSP repo (FSP_USE_REPO). Test: Supermicro X11SSM-F builds and boots fine with custom FSP FD set. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11Subrata Banik
List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25mb/google/dedede: Create galtic variantFrankChu
Create the galtic variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:170913840 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_GALTIC Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25mb/google/volteer: Update Eldrid USB2 port settings in overridetreeNick Chen
1. Disable M.2 WWAN and Type-A Port A1 2. Change register 4 to 3 and tuning USB2 Port1 eye diagram 3. Lower camera driving BUG=b:169105751 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25mb/ocp/deltalake: Define SMBIOS type 16 error correction type byTim Chu
RasModesEnabled Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type 16 error correction type Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-25arch/x86/smbios: Update SMBIOS type 16 error correction typeTim Chu
Add weak function for SMBIOS type 16 error correction type. Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I85b37e9cfd22a78544d03e5506ff92b1f2404f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47508 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOSMatt DeVillier
Selecting SOC_INTEL_CSE_LITE_SKU without conditioning on CHROMEOS force-selects CHROMEOS, per src/soc/intel/common/block/cse/Kconfig. Conditioning on CHROMEOS allows for non-ChromeOS targets to be built. Test: build wyvern variant with CONFIG_CHROMEOS=n Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-25soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedefAngel Pons
It is not used. Change-Id: I3ef0878811bf2ec406ded03aac6c5dfeb5bf45a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47001 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25mb/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011Stanley Wu
Lindar change amp to ALC1011 Add ALC1011 amp acpi info to devicetree BUG=b:171771736 BRANCH=firmware-volteer-13521.B TEST=build and verify ALC1011 can be recognized. Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-25mb/amd/mandolin: Add decode range for LPC debug cardNikolai Vyssotski
Some LPC debug boards hard strap SIO address to be at 0x164e/0x164d vs 0x4e/0x4d. Add support for configurable SIO address to support these cards. BUG=b:159933344 TEST=boot with LPC debug card, verify serial output Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-25mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNCWisley Chen
Add H5ANAG6NCJR-XNC. BUG=b:165461530 BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25nb/amd: Deduplicate nb_common.hAngel Pons
Save for the IO_APIC2_ADDR definition, they are equivalent. Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25device: Drop unused HyperTransport codeAngel Pons
Only two definitions are actually used somewhere, the rest is unused. Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/clevo/kbl-u: Configure GPIOs using mainboard_opsFelix Singer
Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-24mb/kontron/bsl6: Move GPIO configuration to C fileFelix Singer
Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-24mb/kontron/bsl6: Use include folder for header filesFelix Singer
Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47849 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24sb/intel/lynxpoint: Replace hard-coded IDs with definesFelix Singer
Replace hard-coded IDs with defines introduced in CB:47807. Used documents: - 328904-003 - 329003-003 Built lenovo/t440p with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47808 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsetsFelix Singer
Used documents: - 328904-003 - 329003-003 Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47807 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/**/cmos.layout: Drop copy-pasted `volume` entriesAngel Pons
This option only applies to boards using the Lenovo H8 EC code. Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNBAngel Pons
Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge boards ended up with these entries because of copy-paste programming. Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24soc/intel/xeon_sp: Enable SMI handlerRocky Phagura
SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura@fb.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCOArthur Heymans
TCO is configured by FSP. This mostly makes it possible to report TCO events in SMM if enabled. Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24soc/intel/xeon_sp: Hook up the PMC driverArthur Heymans
The soc code was already there but it was never linked. Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/google/volteer: fw_config: Add setting for new sd readersZhuohao Lee
This patch adds three settings for the new sd readers. The new assigned values are: 1. RTS5227S: 3 2. L9750: 4 3. SD_OZ711LV2LN: 5 BUG=b:173676531 BRANCH=volteer TEST=abuild -t google/volteer Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-24soc/intel/skylake: Support NHLT 1ch DMICBenjamin Doron
Allows advertising support for a 1ch array DMIC in the NHLT table. Boards use the NHLT if a microphone is connected to the DSP. Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10. A custom ALSA topology will be required for Linux. Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-24soc/intel/skylake: Use correct NHLT_PDM_DEV definitionBenjamin Doron
According to the NHLT specification[1], PDM_DEV is defined as "1" on Kabylake based platforms. coreboot currently sets it to "0" on all platforms. Add an entry to the enum and use it to define NHLT_PDM_DEV for Kabylake. "Device Type" will resume from "2" on all platforms, but entries are currently reserved. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-23nb/amd/agesa/family15tn: define macros for GNB and IOMMU devicesMike Banon
Follow the example of newer AMD code for Stoneyridge and Picasso. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23nb/amd/agesa/family15tn: define macro for internal HDMI audio controllerMike Banon
Following the example of CB:7630 done for family16kb boards (git commit 3ff4f85ccd9fdb7cd4885a10f025b5ab297a445f). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic48c7475ceadb60f825ca9e3c3427c8a7525a266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter nameKevin Chiu
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-23sb/intel/lynxpoint: Drop invalid SATA registersAngel Pons
Code was copy-pasted from older chips and has no effect on Lynxpoint. Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/siemens/mc_apl1: Use `pci_or_config16` functionAngel Pons
Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-11-23soc/intel/cannonlake: Add ICC limits for CFL-S DT 4Angel Pons
TEST=Boot with an i3-9100F and see no vr_config errors. Change-Id: Ic62ef038ad11d147a38804f694d3e056611b96db Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47445 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-23soc/intel/denverton_ns: Hook up SMMSTOREAngel Pons
Tested on Intel Harcuvar CRB, SMMSTORE is now working. Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Get rid of gpio.h and use C files insteadFelix Singer
Split up gpio.h into two seperate compilation units, gpio.c and gpio_early.c, containing the complete configuration and a minimal configuration used in early stages. Tested on clevo/l140cu and it still boots. Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Get rid of cnl_configure_pads()Felix Singer
Get rid of cnl_configure_pads() since it is a hack for the FSP. Instead, hook up to the mainboard_ops driver and configure the GPIOs using .init. Tested on clevo/l140cu and it still boots. Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Move bootblock.c and ramstage.c to mb levelFelix Singer
Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Use include folder for header filesFelix Singer
Change-Id: I50be3d9b829f624cbe460060c40482047f39774c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Move hda_verb.c to mainboard's MakefileFelix Singer
Move hda_verb.c from the variant's Makefile to the mainboard's Makefile, because every variant needs one. Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47820 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-23mb/**/cmos.layout: Indent everything with tabsAngel Pons
Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23mb/**/cmos.layout: Remove crusty commentsAngel Pons
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23soc/intel/alderlake: Update UART0 GPIO as per latest schematicsSubrata Banik
UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23mb/intel/adlrvp: Enable pre-boot display over HDMI-B portSubrata Banik
List of changes: 1. Configure CTRLCLK and CTRLDATA for HDMI 2. Enable Ddc and HPD for Port-B 3. Disable dual eDP configuration for Port-A and B TEST=Able to see depthcharge pre-boot screens over HDMI-B port. Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZESubrata Banik
According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang. Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ↵Bora Guvendik
UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and ↵Bora Guvendik
UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22soc/ti/am335x: Fix timer implementationSam Lewis
Implements the monotonic timer using the am335x dmtimer peripheral. Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44383 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22soc/ti/am335x: Enable MMU in bootblockSam Lewis
Enables the MMU primarily to allow the unaligned word reads that the FMAP code requires. Without enabling this, the chip gets data access exceptions. Enabling the MMU also gives some advantages in allowing the icache and dcache to be enabled, so is probably worth doing regardless. Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22mb/ocp/deltalake: Override SMBIOS type 4 cpu voltageTim Chu
Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected. Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-22mb/google/puff/var/dooly: update USB2 type-c strengthTony Huang
Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-11-22nb/amd/pi: Remove 00660F01 directory & filesMartin Roth
These files are not used by any platform, so remove them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/google/volteer: Remove unused devices for terrador and todorDavid Wu
Remove the following devices - Goodix Touchscreen - SAR0 Proximity Sensor BUG=b:173480406 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22vendorcode/eltan/security: Add dependency for menu itemsFrans Hendriks
Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are always displayed. Add dependency and display these items when feature is enabled only. Tested on Facebook FBG1701. Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22drivers/tpm: Move PPI stubPatrick Rudolph
As preparation to a full PPI implementation move the acpi code out of the pc80/tpm/tis driver into the generic tpm driver folder. This doesn't change any functionality. Change-Id: I7818d0344d4a08926195bd4804565502717c48fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/facebook/fbg1701/Kconfig: Add dependencyFrans Hendriks
VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22soc/intel/xeon_sp: Work around FSP-T not respecting its own APIArthur Heymans
The CPX FSP-T does not respect the FSP2.x spec and uses registers where coreboot has its initial timestamp stored. If the initial timestamp is later than some other timestamps this messes up the timestamps 'cbmem -t' reports as it thinks they are a result from a timestamp overflow (reporting that it took 100k years to boot). TEST: The ocp/deltalake boots within the span of a lifetime. Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/google/octopus: fix droid lte sku load specific wifi sar valueSheng-Liang Pan
This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex. BUG=none BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22cpu/amd/microcode: Remove dead MakefileArthur Heymans
Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmclib.c: Properly guard apm_control()Arthur Heymans
This function is only properly implemented with SMM support. Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/common/pmc.c Don't implement a weak function that diesArthur Heymans
Buildtime failures are better than runtime failures. Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmc: Only include the PCI driver when it is not hiddenArthur Heymans
On more recent Intel platforms FSP-S hides the PMC PCI device and the driver is broken for those devices so don't include it at all. Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.cArthur Heymans
pmc.c mostly contains a PCI driver, while this function just calls into SMM. Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/denverton_ns: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2020-11-22mb/google/volteer/var/voema: Update gpio and devicetree settingsDavid Wu
Based on latest schematic and gpio table of voema, update gpio and devicetree settings for voema Proto. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 22:56:19 +0000