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cbfstool usage change:
The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size".
The "locate" command was used to find a place to store ELF stage image in one
memory page. Its argument "-a (alignment)" was actually specifying the page size
instead of doing memory address alignment. This can be confusing when people are
trying to put a blob in aligned location (ex, microcode needs to be aligned in
0x10), and see this:
cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000
# output: 0x44, which does not look like aligned to 0x40000.
To prevent confusion, it's now switched to "-P/--page-size".
Verified by building i386/axus/tc320 (with page limitation 0x40000):
cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
# output: 0x44
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731
Reviewed-on: http://review.coreboot.org/2730
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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A fix to eliminate warnings when building romstage files with ChromeOS
compilers
Change-Id: Ia5d7bbdde3aa3439fd493f5795f2cc2bf4c4c187
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2781
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There should be a fixed 10ms wait after sending an INIT IPI. The
previous implementation was just waiting up to 10ms for the IPI to
complete the send. That is not correct. The 10ms is unconditional
according to the documentation. No ill effects were observed with the
previous behavior, but it's important to follow the documentation.
Change-Id: Ib31d49ac74808f6eb512310e9f54a8f4abc3bfd7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2780
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch parallelizes the AP startup for Haswell-based devices. It
does not touch the generic secondary startup code. Instead it provides
its own MP support matching up with the Haswell BWG. It seemed to be too
much trouble to support the old startup way and this new way. Because of
that parallel loading is the only thing supported.
A couple of things to note:
1. Micrcode needs to be loaded twice. Once before MTRR and caching is
enabled. And a second time after SMM relocation.
2. The sipi_vector is entirely self-contained. Once it is loaded and
written back to RAM the APs do not access memory outside of the
sipi_vector load location until a sync up in ramstage.
3. SMM relocation is kicked off by an IPI to self w/ SMI set as the
destination mode.
The following are timings from cbmem with dev mode disabled and recovery mode
enabled to boot directly into the kernel. This was done on the
baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The
kernel has console enabled on the serial port. Entry 70 is the device
initialization, and that is where the APs are brought up. With these two
examples it looks to shave off ~200 ms of boot time.
Before:
1:55,382
2:57,606 (2,223)
3:3,108,983 (3,051,377)
4:3,110,084 (1,101)
8:3,113,109 (3,024)
9:3,156,694 (43,585)
10:3,156,815 (120)
30:3,157,110 (295)
40:3,158,180 (1,069)
50:3,160,157 (1,977)
60:3,160,366 (208)
70:4,221,044 (1,060,677)
75:4,221,062 (18)
80:4,227,185 (6,122)
90:4,227,669 (484)
99:4,265,596 (37,927)
1000:4,267,822 (2,225)
1001:4,268,507 (685)
1002:4,268,780 (272)
1003:4,398,676 (129,896)
1004:4,398,979 (303)
1100:7,477,601 (3,078,621)
1101:7,480,210 (2,608)
After:
1:49,518
2:51,778 (2,259)
3:3,081,186 (3,029,407)
4:3,082,252 (1,066)
8:3,085,137 (2,884)
9:3,130,339 (45,202)
10:3,130,518 (178)
30:3,130,544 (26)
40:3,131,125 (580)
50:3,133,023 (1,897)
60:3,133,278 (255)
70:4,009,259 (875,980)
75:4,009,273 (13)
80:4,015,947 (6,674)
90:4,016,430 (482)
99:4,056,265 (39,835)
1000:4,058,492 (2,226)
1001:4,059,176 (684)
1002:4,059,450 (273)
1003:4,189,333 (129,883)
1004:4,189,770 (436)
1100:7,262,358 (3,072,588)
1101:7,263,926 (1,567)
Booted the baskingridge board as noted above. Also analyzed serial
messages with pcserial enabled.
Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2779
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch only applies to CONFIG_MICROCODE_IN_CBFS. The intel microcode
update routine would always walk the CBFS for the microcode file. Then
it would loop through the whole file looking for a match then load the
microcode. This process was maintained for intel_update_microcode_from_cbfs(),
however 2 new functions were exported:
1. const void *intel_microcode_find(void)
2. void intel_microcode_load_unlocked(const void *microcode_patch)
The first locates a matching microcode while the second loads that
mircocode. These new functions can then be used to cache the found
microcode blob w/o having to re-walk the CBFS.
Booted baskingridge board to Linux and noted that all microcode
revisions match on all the CPUs.
Change-Id: Ifde3f3e5c100911c4f984dd56d36664a8acdf7d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2778
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Having this header file in the mainboard directory breaks
the dinar build on cygwin because the header file in the
dinar mainboard is used instead of the correct header file
src/vendorcode/amd/cimx/sb700/OEM.h. The build probably works
fine on Linux systems because, due to case-sensitivity, Oem.h
will not match the #include "OEM.h" statement in
src/southbridge/amd/cimx/sb700/Platform.h.
The Oem.h file in the dinar mainboard is not used by any other
source files, and the defines in the dinar mainboard are duplicated
by defines in the correct OEM.h file. Therefore, the file can be
safely removed.
Change-Id: I81b97eca8116d63644d335edc3bb51f90c7094d9
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2776
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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The non-relocatable SMM code was changed to link against libgcc a while back
so that printk could use built-in division instead of a hand crafted div()
function. However, the relocatable SMM code was not adapted by mistake.
This patch links the relocatable SMM against libgcc, too, so we can enable it
for Haswell.
Change-Id: Ia64a78e2e62348d115ae4ded52d1a02c74c5cea4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2727
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There are changes coming to perform more complex tasks after cache-as-ram
has been torn down but before ramstage is loaded. Therefore, add the
romstage_after_car() function to call after cache-as-ram is torn down.
Its responsibility is for loading the ramstage and any other complex
tasks. For example, the saving of OS-controlled memory in the resume
path has now been moved into C instead of assembly.
Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The save_mrc_data() was previously called conditionally
in the raminit code. The save_mrc_data() function was called
in the non-S3 wake paths. However, the common romstage_common()
code was checking cbmem initialization things on s3 wake. Between
the two callers cbmem_initialize() was being called twice in the
non-s3 wake paths. Moreover, saving of the mrc data was not allowed
when CONFIG_EARLY_CBMEM_INIT wasn't enabled.
Therefore, move the save_mrc_data() to romstage_common. It already has
the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT
requirement from save_mrc_data() as well as the call to cbmem_initialize().
Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2756
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Instead of hard coding the policy for the stack and MTRR values after
the cache-as-ram is torn down, allow for the C code to pass those
policies back to the cache-as-ram assembly file. That way, ramstage
relocation can use a different stack as well as different MTRR policies.
Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2755
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This commit pulls in all the common logic for romstage into
the Haswell cpu directory. The bits specific to the mainboard
still reside under their respective directories. The calling
sequence bounces from the cpu directory to mainboard then back
to the cpu directory. The reasoning is that Haswell systems use
cache-as-ram for backing memory in romstage. The stack is used to
allocate structures. However, now changes can be made to the
romstage for Haswell and apply to all boards.
Change-Id: I2bf08013c46a99235ffe4bde88a935c3378eb341
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2754
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This structure is not used nor the variable being instantiated on the
stack. Remove them.
Change-Id: If3abe2dd77104eff49665dd33570b07179bf34f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2753
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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It was found that the Haswell reference code was smashing through the
stack into the reference code's heap implementation. The reason for this
is because our current CAR allocation is too small. Moreover there are
quite a few things to coordinate between 2 code bases to get correct.
This commit separates the CAR into 2 parts:
1. MRC CAR usage.
2. Coreboot CAR usage.
Pointers from one region can be passed between the 2 modules, but one
should not be able to affect the others as checking has been put into
place in both modules.
The CAR size has effectively been doubled from 0x20000 (128 KiB) to
0x40000 (256KiB). Not all of that increase was needed, but enforcing
a power of 2 size only utilizes 1 MTRR.
Old CAR layout with a single contiguous stack with the region starting
at CONFIG_DCACHE_RAM_BASE:
+---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
| MRC global variables |
| CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
+---------------------------------------+
| ROM stage stack |
| |
| |
+---------------------------------------+
| MRC Heap 30000 bytes |
+---------------------------------------+
| ROM stage console |
| CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
+---------------------------------------+
| ROM stage CAR_GLOBAL variables |
+---------------------------------------+ Offset 0
There was some hard coded offsets in the reference code wrapper to start
the heap past the console buffer. Even with this commit the console
can smash into the following region depending on what size
CONFIG_CONSOLE_CAR_BUFFER_SIZE is.
As noted above This change splits the CAR region into 2 parts starting
at CONFIG_DCACHE_RAM_BASE:
+---------------------------------------+
| MRC Region |
| CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
+---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
| ROM stage stack |
| |
| |
+---------------------------------------+
| ROM stage console |
| CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
+---------------------------------------+
| ROM stage CAR_GLOBAL variables |
+---------------------------------------+ Offset 0
Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE,
which represents the expected stack usage for the romstage. A marker
is checked at the base of the stack to determine if either the stack
was smashed or the console encroached on the stack.
Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2752
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add an rmodules class so that there are default rules for compiling
files that will be linked by the rmodule linker. Also, add a new type
for SIPI vectors.
Change-Id: Ided9e15577b34aff34dc23e5e16791c607caf399
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2751
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is causing a hang in depthcharge. For now just disable
this port.
Change-Id: I87a6db2d8361588e82eee640c74cea690115bed5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2764
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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By including the heap in the bss output section the size is accounted
for in a elf PT_LOAD segment. Without this change the heap wasn't being
put into a PT_LOAD segment. The result is a nop w.r.t. functionality,
but readelf and company will have proper MemSiz fields.
Change-Id: Ibfe9bb87603dcd4c5ff1c57c6af910bbba96b02b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2750
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There is a plan to utlize rmodules for loading ramstage as a
relocatable module. However, the rmodule header may change.
In order to provide some wiggle room for changing the contents
of the rmodule header add some padding. This won't stop the need
for coordinating properly between the romstage loader that may be
in readonly flash and rmodule header fields. But it will provide
for a way to make certain assumptions about alignment of the
rmodule's program when the rmodule is compressed in the flash.
Change-Id: I9ac5cf495c0bce494e7eaa3bd2f2bd39889b4c52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2749
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model
to the switch statement.
Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2747
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Rather than have to repeat this bit in every mainboard.
Also, remove the reset of the RTC power status from here.
We had done this in TOT for current platforms but did not
carry it back to emeraldlake2 where this branched from.
If we clear the status here then we don't get an event
logged later which can be important for the devices that
do not have a CMOS battery.
Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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A rmodule is short for relocation module. Relocaiton modules are
standalone programs. These programs are linked at address 0 as a shared
object with a special linker script that maintains the relocation
entries for the object. These modules can then be embedded as a raw
binary (objcopy -O binary) to be loaded at any location desired.
Initially, the only arch support is for x86. All comments below apply to
x86 specific properties.
The intial user of this support would be for SMM handlers since those
handlers sometimes need to be located at a dynamic address (e.g. TSEG
region).
The relocation entries are currently Elf32_Rel. They are 8 bytes large,
and the entries are not necessarily in sorted order. An future
optimization would be to have a tool convert the unsorted relocations
into just sorted offsets. This would reduce the size of the blob
produced after being processed. Essentialy, 8 bytes per relocation meta
entry would reduce to 4 bytes.
Change-Id: I2236dcb66e9d2b494ce2d1ae40777c62429057ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2692
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The acpi_fill_mcfg() was still using ivy/sandy PCI device ids which Hawell
obviously doesn't have. This resulted in an empty MCFG table. Instead of
relying on PCI device ids use dev/fn 0/0 since that is where the host
bridge always resides. Additionally remove the defines for the IB and SB
pci device ids. Replace them with mobile and ult Haswel device ids and
use those in the pci driver tables for the northbridge code.
Booted to Linux and noted that MCFG was properly parsed.
Change-Id: Ieaab2dfef0e9daf3edbd8a27efe0825d2beb9443
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2748
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The SMM handler resides in the TSEG region which is far above
CONFIG_RAM_TOP (which is the highest cacheable address) before
MTRRs are setup. This means that calling initialize_cpus() before
performing MTRR setup on the BSP means the SMM handler is copied
using uncacheable accesses.
Improve the SMM handler setup path by enabling performing MTRR setup on
for the BSP before the call to initialize_cpus(). In order to do this
the haswell_init() function was split into 2 paths: BSP & AP paths.
There is a cpu_common_init() that both call to perform similar
functionality. The BSP path in haswell_init() then starts the APs using
intel_cores_init(). The AP path in haswell_init() loads microcode and
sets up MTRRs.
This split will be leveraged for future support of bringing up APs in
parallel as well as adhering to the Haswell MP initialization
requirements.
Change-Id: Id8e17af149e68d708f3d4765e38b1c61f7ebb470
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2746
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The configure_mca() function was hard coding the number of
banks the cpu supported. Query this dynamically so that it
no longer clears only 7 banks.
Change-Id: I33fce8fadc0facd1016b3295faaf3ae90e490a71
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2745
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This just moves the definiton of CORE_THREAD_COUNT_MSR so
that future code can utilize it.
Change-Id: I15a381090f21ff758288f55dc964b6694feb6064
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2744
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This commit adds support for using the SMM modules for haswell-based
boards. The SMI handling was also refactored to put the relocation
handler and permanent SMM handler loading in the cpu directory. All
tseg adjustment support is dropped by relying on the SMM module support
to perform the necessary relocations.
Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2728
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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We're happy to announce coreboot support for the "Stout"
Chromebook, a.k.a Lenovo X131e Chromebook.
Change-Id: I9b995f8d0dd48e41c788b7c3d35b4fac5840e425
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2636
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is mostly a copy of Whitetip Mountain 1 with specific GPIO
map for this Customer Reference Board (CRB).
This mainboard currently has basic funcionality and is able to
boot a Linux Kernel but many of the new Haswell ULT specific
devices are not yet enabled.
Change-Id: I999452d86f00a2c245fa39b1b76080f6a3b1e352
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2725
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- Some initialization steps were done twice
- One step was missing for Panther Point HDA
- Added a 1ms delay after reset
- Increased timeout to 1ms for all codec operations
Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Haswell CPUs require a FIT table in the firmware. This commit
adds rudimentary support for a FIT table. The number of entries
in the table is based on a configuration option. The code only
generates a type 0 entry. A follow-on tool will need to be developed
to populate the FIT entries as well as checksumming the table.
Verified image has a FIT pointer and table when option is selected.
Change-Id: I3a314016a09a1cc26bf1fb5d17aa50853d2ef4f8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There was a mix of setup code sprinkled across the various components:
southbridge code in the northbridge, etc. This commit reorganizes the
code so that northbridge code doesn't initialize southbridge components.
Additionally, the calling dram initialization no longer calls out to ME
code. The main() function in the mainboard calls the necessary ME
functions before and after dram initialization.
The biggest change is the addition of an early_pch_init() function
which initializes the BARs, GPIOs, and RCBA configuration. It is also
responsible for reporting back to the caller if the board is being
woken up from S3. The one sequence difference is that the RCBA config
is performed before claling the reference code.
Lastly the rcba configuration was changed to be table driven so that
different board/configurations can use the same code. It should be
possible to have board/configuration specific gpio and rcba
configuration while reusing the romstage code.
Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Lots of things are still placeholder and need work.
Due to the useful GPIOs being run to either the EC or the SIO1007
I have hard coded developer mode on and recovery mode off.
Change-Id: I4c308bd90db03ac5bffdfde566e5adbbaabac632
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2724
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Certain SATA devices claim to support SATA 6 Gbps, but in fact have
bugs. For these devices, add a config option to force the SATA link
speed to something other than default.
Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb
Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
Reviewed-on: http://review.coreboot.org/2765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
This enables power management and clock gating on XHCI.
Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
objcopy -B provides symbols of the form _binary_<name>_(start|end|size).
However, the _size variant is an absoult symbol. If one wants to
relocate the smi loading the _size symbol will be relocated which is
wrong since it is suppose to be a fixed size. There is no way to
distinguish symbols that shouldn't be relocated vs ones that can.
Instead use the _start and _end variants to determine the size.
Change-Id: I55192992cf36f62a9d8dd896e5fb3043a3eacbd3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2760
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The bd82x6x requires some additional setting on S3/S4 entry.
Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2759
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Add the PCH function to SMM for follow-on SMM patches that
require these functions.
Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2758
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The SMRR takes precedence over the MTRR entries. Therefore, if the TSEG
region is setup as cacheable through the MTTRs, accesses to the TSEG
region before SMM relocation are cached. This allows for the setup of
SMM relocation to be faster by caching accesses to the future TSEG
(SMRAM) memory.
MC MAP: TOM: 0x140000000
MC MAP: TOUUD: 0x18f600000
MC MAP: MESEG_BASE: 0x13f000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x13f000000
MC MAP: REMAP_LIMIT: 0x18f5fffff
MC MAP: TOLUD: 0xafa00000
MC MAP: BGSM: 0xad800000
MC MAP: BDSM: 0xada00000
MC MAP: TESGMB: 0xad000000
MC MAP: GGC: 0x209
TSEG->BGSM:
PCI: 00:00.0 resource base ad000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 4
BGSM->TOLUD:
PCI: 00:00.0 resource base ad800000 size 2200000 align 0 gran 0 limit 0 flags f0000200 index 5
Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB
Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB
Adding hole at 2776MB-2816MB
Setting variable MTRR 3, base: 2776MB, range: 8MB, type UC
Setting variable MTRR 4, base: 2784MB, range: 32MB, type UC
Zero-sized MTRR range @0KB
Allocate an msr - basek = 00400000, sizek = 0023d800,
Setting variable MTRR 5, base: 4096MB, range: 2048MB, type WB
Setting variable MTRR 6, base: 6144MB, range: 256MB, type WB
Adding hole at 6390MB-6400MB
Setting variable MTRR 7, base: 6390MB, range: 2MB, type UC
MTRR translation from MB to addresses:
MTRR 0: 0x00000000 -> 0x80000000 WB
MTRR 1: 0x80000000 -> 0xa0000000 WB
MTRR 2: 0xa0000000 -> 0xb0000000 WB
MTRR 3: 0xad800000 -> 0xae000000 UC
MTRR 4: 0xae000000 -> 0xb0000000 UC
I'm not a fan of the marking physical address space with MTRRs as being
UC which is PCI space, but it is technically correct.
Lastly, drop a comment describing AP startup flow through coreboot.
Change-Id: Ic63c0377b9c20102fcd3f190052fb32bc5f89182
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Devoutly to be wish'd. To die,—to sleep;—
To sleep! perchance to dream:—ay, there's the rub;
For in that sleep of death what dreams may come,
(Since who could argue with William Shakespeare?)
Change-Id: I4e4c617dcd3ede81a0abbe16f9916562d24fa8ce
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2733
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the Persimmon DSDT.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`. PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge. However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.
This is the same change as made to Persimmon with
change-id I44f22:
http://review.coreboot.org/#/c/2592/
Change-Id: I5184df8deb7b5d2e15404d689c16c00493eb01aa
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2736
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
I am removing the _INI method from the AZHD device because
it does not seem to do anything and causes errors in the
FWTS[1] (Firmware Test Suite) test 'method'. The INI
method performs device specific initialization and is
run when OSPM loads a description table. It must only
access OperationRegions that have been indicated as
available by the _REG (Region) method. We do not have a
_REG method and during my testing, I added a REG method
but it did not seem to make a difference in the PCI
register space. The bit fields defined as NSDI (Disable
No Snoop), NSDO (Disable No Snoop Override), and NSEN
(Enable No Snoop Request) do not ever get written from
their default values. And writing to these bit fields
does not seem to be necessary because I did not notice
any change in audio functionality.
In an effort to clean up as many FWTS errors as possible,
I propose removing this method altogether. I have seen no
change in operation (audio works with and without this
method) and there does not seem to be any change in lspci
or dmesg.
FWTS information can be found here:
[1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same chagne as made to Persimmon in
Change-ID If8d86f:
http://review.coreboot.org/#/c/2726/
Change-Id: Id560ea85a38f73aaba2c35447bbce46bd9c0d0dd
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2741
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
I am removing the _INI method from the AZHD device because
it does not seem to do anything and causes errors in the
FWTS[1] (Firmware Test Suite) test 'method'. The INI
method performs device specific initialization and is
run when OSPM loads a description table. It must only
access OperationRegions that have been indicated as
available by the _REG (Region) method. We do not have a
_REG method and during my testing, I added a REG method
but it did not seem to make a difference in the PCI
register space. The bit fields defined as NSDI (Disable
No Snoop), NSDO (Disable No Snoop Override), and NSEN
(Enable No Snoop Request) do not ever get written from
their default values. And writing to these bit fields
does not seem to be necessary because I did not notice
any change in audio functionality.
In an effort to clean up as many FWTS errors as possible,
I propose removing this method altogether. I have seen no
change in operation (audio works with and without this
method) and there does not seem to be any change in lspci
or dmesg.
FWTS information can be found here:
[1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same change as made to Persimmon in
Change-ID If8d86f:
http://review.coreboot.org/#/c/2726/
Change-Id: Iae70c3d0af1cdaca31b206ad6daba4d38ee6b780
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2742
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
I am removing the _INI method from the AZHD device because
it does not seem to do anything and causes errors in the
FWTS[1] (Firmware Test Suite) test 'method'. The INI
method performs device specific initialization and is
run when OSPM loads a description table. It must only
access OperationRegions that have been indicated as
available by the _REG (Region) method. We do not have a
_REG method and during my testing, I added a REG method
but it did not seem to make a difference in the PCI
register space. The bit fields defined as NSDI (Disable
No Snoop), NSDO (Disable No Snoop Override), and NSEN
(Enable No Snoop Request) do not ever get written from
their default values. And writing to these bit fields
does not seem to be necessary because I did not notice
any change in audio functionality.
In an effort to clean up as many FWTS errors as possible,
I propose removing this method altogether. I have seen no
change in operation (audio works with and without this
method) and there does not seem to be any change in lspci
or dmesg.
FWTS information can be found here:
[1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same change as made to Persimmon in
Change-ID If8d86f:
http://review.coreboot.org/#/c/2726/
Change-Id: Iff594d4a3493531561eb25d1cceeb97bcefde424
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the Persimmon DSDT.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`. PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge. However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.
This is the same change as made to Persimmon with
change-id I44f22:
http://review.coreboot.org/#/c/2592/
Change-Id: Ie36b60973c6a5f9076bb55c8f451532711a2f8a8
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The _OSC method is used to tell the OS what capabilities
it can take control over from the firmware. This method
is described in chapter 6.2.9 of the ACPI spec v3.0.
The method takes 4 inputs (UUID, Rev ID, Input Count,
and Capabilities Buffer) and returns a Capabilites
Buffer the same size as the input Buffer. This Buffer
is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control
Dword. The OS will request control of certain
capabilities and the firmware must grant or deny control
of those features. We do not want to have control over
anything so let the OS control as much as it can.
The _OSC method is required for PCIe devices and dmesg
checks for its existence and issues an error if it is
not found.
This is the same change made to Persimmon with Change-ID
I149428:
http://review.coreboot.org/#/c/2684/
Change-Id: If6dd1a558d9c319d9a41ce63588550c8e81e595f
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2738
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The _OSC method is used to tell the OS what capabilities
it can take control over from the firmware. This method
is described in chapter 6.2.9 of the ACPI spec v3.0.
The method takes 4 inputs (UUID, Rev ID, Input Count,
and Capabilities Buffer) and returns a Capabilites
Buffer the same size as the input Buffer. This Buffer
is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control
Dword. The OS will request control of certain
capabilities and the firmware must grant or deny control
of those features. We do not want to have control over
anything so let the OS control as much as it can.
The _OSC method is required for PCIe devices and dmesg
checks for its existence and issues an error if it is
not found.
This is the same change made to Persimmon with Change-ID
I149428:
http://review.coreboot.org/#/c/2684/
Change-Id: I2701d915338294bdade2ad334b22a51db980892e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The _OSC method is used to tell the OS what capabilities
it can take control over from the firmware. This method
is described in chapter 6.2.9 of the ACPI spec v3.0.
The method takes 4 inputs (UUID, Rev ID, Input Count,
and Capabilities Buffer) and returns a Capabilites
Buffer the same size as the input Buffer. This Buffer
is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control
Dword. The OS will request control of certain
capabilities and the firmware must grant or deny control
of those features. We do not want to have control over
anything so let the OS control as much as it can.
The _OSC method is required for PCIe devices and dmesg
checks for its existence and issues an error if it is
not found.
This is the same change made to Persimmon with Change-ID
I149428:
http://review.coreboot.org/#/c/2684/
Change-Id: Iaf7b8153cec4d730efbceae3e6957d2904b8fae4
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2740
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
These enables are hidden behind IOBP for some reason.
Boot to linux with SDIO disabled and see that
the SDIO driver does not load and crash the system.
Change-Id: Icfbfa117e9e57a51d32db7f6366a9d0d790adcf0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2695
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Paul points out that some people like 1024*1024, others like
1048576, but in any case these are all open to typos.
Define KiB, MiB, GiB, and TiB as in the standard so people can use them.
Change-Id: Ic1b57e70d3e9b9e1c0242299741f71db91e7cd3f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2769
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
It's possible that TOUUD can be 4GiB in a small physical memory
configuration. Therefore, don't add a 0-size memory range resouce
in that case.
Change-Id: I016616a9d9d615417038e9c847c354db7d872819
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2691
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
One might wonder what a board named 'build' does. Rename the file to
build-snow. The fact that it is in a directory with google in the name
should be enough to identify the vendor.
Change-Id: I0b473cdce67d56fc6b92032b55180523eb337d66
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2766
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
The Link native graphics commit 49428d84 [1]
Add support for Google's Chromebook Pixel
was missing some of the higher level bits, and hence could not be
used. This is not new code -- it has been working since last
August -- so the effort now is to get it into the tree and structure
it in a way compatible with upstream coreboot.
1. Add options to src/device/Kconfig to enable native graphics.
2. Export the MTRR function for setting variable MTRRs.
3. Clean up some of the comments and white space.
While I realize that the product name is Pixel, the mainboard in the
coreboot tree is called Link, and that name is what we will use
in our commits.
[1] http://review.coreboot.org/2482
Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2531
Tested-by: build bot (Jenkins)
|
|
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the Persimmon DSDT.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`. PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge. However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.
This is the same change as made to Persimmon with
change-id I44f22:
http://review.coreboot.org/#/c/2592/
Change-Id: I9017a7619b3b17e0e95ad0fe46d0652499289b00
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2735
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Pins 78-85 are set to GPIO after power on or reset. To enable
UART B the pins must be redirected to it.
Look at W83627DHG databook version 1.4 page 185 Chip
(global) Control Register CR2C.
Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de>
Reviewed-on: http://review.coreboot.org/2626
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
I am removing the _INI method from the AZHD device because
it does not seem to do anything and causes errors in the
FWTS[1] (Firmware Test Suite) test 'method'. The INI
method performs device specific initialization and is
run when OSPM loads a description table. It must only
access OperationRegions that have been indicated as
available by the _REG (Region) method. We do not have a
_REG method and during my testing, I added a REG method
but it did not seem to make a difference in the PCI
register space. The bit fields defined as NSDI (Disable
No Snoop), NSDO (Disable No Snoop Override), and NSEN
(Enable No Snoop Request) do not ever get written from
their default values. And writing to these bit fields
does not seem to be necessary because I did not notice
any change in audio functionality.
In an effort to clean up as many FWTS errors as possible,
I propose removing this method altogether. I have seen no
change in operation (audio works with and without this
method) and there does not seem to be any change in lspci
or dmesg.
FWTS information can be found here:
[1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
Change-Id: If8d86f959822d528c44ab011a851659d486289b5
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The _OSC method is used to tell the OS what capabilities
it can take control over from the firmware. This method
is described in chapter 6.2.9 of the ACPI spec v3.0.
The method takes 4 inputs (UUID, Rev ID, Input Count,
and Capabilities Buffer) and returns a Capabilites
Buffer the same size as the input Buffer. This Buffer
is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control
Dword. The OS will request control of certain
capabilities and the firmware must grant or deny control
of those features. We do not want to have control over
anything so let the OS control as much as it can.
The _OSC method is required for PCIe devices and dmesg
checks for its existence and issues an error if it is
not found.
Change-Id: I1494285def7440972f0549b7cb73eb94dafc72c2
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
It's no longer required.
Change-Id: I621226a3bdfba9bc8edfd6e511a5337ae603ae19
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2723
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
This wasn't previously spotted because the printk's were correct.
However if one needed to get the value of the BDSM or BGSM register
the value would reflect the other register's value.
Change-Id: Ieec7360a74a65292773b61e14da39fc7d8bfad46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2689
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Currently the OS is free to use the memory located at the default
SMRAM space because it is not marked reserved in the e820. This can
lead to memory corruption on S3 resume because SMM setup doesn't save
this range before using it to relocate SMRAM.
Resulting tables:
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000002ffff: RAM
2. 0000000000030000-000000000003ffff: RESERVED
3. 0000000000040000-000000000009ffff: RAM
4. 00000000000a0000-00000000000fffff: RESERVED
5. 0000000000100000-0000000000efffff: RAM
6. 0000000000f00000-0000000000ffffff: RESERVED
7. 0000000001000000-00000000acebffff: RAM
8. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
9. 00000000ad000000-00000000af9fffff: RESERVED
10. 00000000f0000000-00000000f3ffffff: RESERVED
11. 00000000fed10000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-000000018f5fffff: RAM
e820 map has 13 items:
0: 0000000000000000 - 0000000000030000 = 1 RAM
1: 0000000000030000 - 0000000000040000 = 2 RESERVED
2: 0000000000040000 - 000000000009f400 = 1 RAM
3: 000000000009f400 - 00000000000a0000 = 2 RESERVED
4: 00000000000f0000 - 0000000000100000 = 2 RESERVED
5: 0000000000100000 - 0000000000f00000 = 1 RAM
6: 0000000000f00000 - 0000000001000000 = 2 RESERVED
7: 0000000001000000 - 00000000acec0000 = 1 RAM
8: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
10: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
11: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
12: 0000000100000000 - 000000018f600000 = 1 RAM
Booted and checked e820 as well as coreboot table information.
Change-Id: Ie4985c748b591bf8c0d6a2b59549b698c9ad6cfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2688
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The previous code w.r.t. resource allocation was getting lucky
based on the way fixed mmio resources on the system were being
chosen. Namely, PCIEXBAR was the lowest mmio space and the other
fixed non-standar BARs were above it. The resource allocator would
then start allocating standard BARs below that.
On top of that other resources were being added when
dev_ops->set_resources() was being called on the PCI domain. At that
point the PCI range limit were already picked for where to start
allocating from.
To ensure we no longer get lucky during resource allocation add the
fixed resources in the host bridge and add the memory controller
cacheable memory areas. With those resources added the range limit
for standard PCI BARs is chosen properly.
Depending on haswell board configurations we may need to adjust and
pass in the size of physical address space needed for PCI resources
to the reference code. For the time being the CRBs appear to be OK.
Lastly, remove the SNB workaround for reserving 2MiB at 1GiB and 512MiB.
Output from 6GiB memory configuration:
MC MAP: TOM: 0x140000000
MC MAP: TOUUD: 0x18f600000
MC MAP: MESEG_BASE: 0x13f000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x13f000000
MC MAP: REMAP_LIMIT: 0x18f5fffff
MC MAP: TOLUD: 0xafa00000
MC MAP: BDSM: 0xada00000
MC MAP: BGSM: 0xad800000
MC MAP: TESGMB: 0xad000000
MC MAP: GGC: 0x209
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-00000000acebffff: RAM
6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
7. 00000000ad000000-00000000af9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-000000018f5fffff: RAM
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 0000000000f00000 = 1 RAM
4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
5: 0000000001000000 - 00000000acec0000 = 1 RAM
6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
10: 0000000100000000 - 000000018f600000 = 1 RAM
Output from 4GiB memory configuration:
MC MAP: TOM: 0x100000000
MC MAP: TOUUD: 0x14f600000
MC MAP: MESEG_BASE: 0xff000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x100000000
MC MAP: REMAP_LIMIT: 0x14f5fffff
MC MAP: TOLUD: 0xafa00000
MC MAP: BDSM: 0xada00000
MC MAP: BGSM: 0xad800000
MC MAP: TESGMB: 0xad000000
MC MAP: GGC: 0x209
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-00000000acebffff: RAM
6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
7. 00000000ad000000-00000000af9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-000000014f5fffff: RAM
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 0000000000f00000 = 1 RAM
4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
5: 0000000001000000 - 00000000acec0000 = 1 RAM
6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
10: 0000000100000000 - 000000014f600000 = 1 RAM
Output from 2GiB memory configuration:
MC MAP: TOM: 0x40000000
MC MAP: TOUUD: 0x100600000
MC MAP: MESEG_BASE: 0x3f000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x100000000
MC MAP: REMAP_LIMIT: 0x1005fffff
MC MAP: TOLUD: 0x3ea00000
MC MAP: BDSM: 0x3ca00000
MC MAP: BGSM: 0x3c800000
MC MAP: TESGMB: 0x3c000000
MC MAP: GGC: 0x209
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-000000003bebffff: RAM
6. 000000003bec0000-000000003bffffff: CONFIGURATION TABLES
7. 000000003c000000-000000003e9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-00000001005fffff: RAM
e820 map has 11 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 0000000000f00000 = 1 RAM
4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
5: 0000000001000000 - 000000003bec0000 = 1 RAM
6: 000000003bec0000 - 000000003ea00000 = 2 RESERVED
7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
10: 0000000100000000 - 0000000100600000 = 1 RAM
Verified through debug messages that range limits as well as
resources were being properly honored.
Change-Id: I2faa7d8a2a34a6a411a2885afb3b5c3fa1ad9c23
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2687
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
|
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This commit updates the Lynx Point resource reservations before
the coreboot allocator assigns resources. There is no need to mark
anything as subtractive decode because there are no devices/buses
linked to the LPC device.
The I/O range reservations consists of claiming the first 4KiB
of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode
ranges are checked against the default claimed range. If those
ranges overlap or fall outside of the default range then those
resources are added.
The MMIO range reservations consist of claiming everything from
the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range
register are then conditionally added if they fall outside of
the default MMIO range.
Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2682
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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- Add ME device ID for Lynxpoint LP
- Add GPU device IDs for ULT
- SATA init tweaks from checking against DXE reference code
- Remove the ICH7 from the SPI driver so it works on all lynxpoint
without having to add more LPC device ID checks
- Add function disable for audio dsp and xhci, remove PCI bridge
- Add interrupt route registers for new devices (needs romstage setup)
Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2680
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The current code is attempting to convert from an invalid
starting temperature. Since we aren't sure where the temperature
will come from yet just return a static value.
This stops the kernel from going to S5 on boot because it
thinks the temperature is too high.
Change-Id: I433fa407e545458344af5842b353df5bc71bfdad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2679
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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This option is not required for haswell. Enabling the option doesn't
do anything aside from complicate mtrr calculation. Therefore, remove
it.
Change-Id: I897523ff7d3606eb89961674c2eb3d384e584857
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2678
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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There are 2 issues in lb_cleanup_memory_ranges(). The first
is that during sort there is a neighbor comparison that initially
starts with the current entry. The second issue is that merging
has an off by one comparison for adjacent entries.
Before:
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-00000000acebffff: RAM
6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
7. 00000000ad000000-00000000af9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed17fff: RESERVED
10. 00000000fed18000-00000000fed18fff: RESERVED
11. 00000000fed19000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-000000018f5fffff: RAM
After:
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000000efffff: RAM
4. 0000000000f00000-0000000000ffffff: RESERVED
5. 0000000001000000-00000000acebffff: RAM
6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
7. 00000000ad000000-00000000af9fffff: RESERVED
8. 00000000f0000000-00000000f3ffffff: RESERVED
9. 00000000fed10000-00000000fed19fff: RESERVED
10. 00000000fed84000-00000000fed84fff: RESERVED
11. 0000000100000000-000000018f5fffff: RAM
Change-Id: I656aab61b0ed4711c9dceaedb81c290d040ffdec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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This commit adds support for the deveveloper, recovery,
and write protect querying. It just uses jumpers on the
Basking Ridge board.
Noted ability to togggle jumpers results in toggling the
respective modes.
Change-Id: Iac189a1fa0245654591e2e9075380db422a329a0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2676
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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While looking at the Basking Ridge schematic I noticed some changes
and wanted to make sure they were reflected in the GPIO map.
Change-Id: I686653c164314ae9f68c42331d2f950751411d4a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2675
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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Needed to map VGA OPROM IDs to actual device IDs
Change-Id: I6743905c3db52519bf18f4bcc1a972aec43d3e9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2674
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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The baskingridge has a non-zero alt_gp_smi_en value in the
devicetree.cb file. It has just to be determined which GPI
pins should trigger an SMI on basking ridge. Without this change
the board would hang during boot (presumably through a SMI flood).
No more hangs once the value is zero.
Change-Id: I9704071bb7966bd3d0bbbc4aafede3f42d829b17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2673
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The Grays Reef CRB is deprecated by order of Intel. Basking Ridge
is the new hotness. Therefore, rename graysreef to basking ridge.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I203497e165d8efc99d3438c4c548140a6e9cc649
Reviewed-on: http://review.coreboot.org/2672
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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- Add device IDs for lynxpoint mobile and LP variants.
- Update the clock gating setup based on BWG
- Update the SATA programming based on BWG
- Add a DEVSLP0 mux config register
Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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The low power variant of the chipset introduces a completely
new interface to the GPIOs.
This is a 1KB region and so needs to be moved as well so it does
not conflict with other IO regions.
Also expose the gpio_get functions to ramstage and move the
prototypes to pch.h so they can be used for both GPIO interfaces.
Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2648
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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This adds microcode ffff000a and the CPUIDs for ULT.
Change-Id: I341c1148a355d8373b31032b9f209232bd03230a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2647
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Device IDs for northbridge and GPU.
Also mask off the lock bit in the memory map registers.
Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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There are enough subtle differences that it is useful to have
a Kconfig entry to differentiate the ULT/LP chipet from the
desktop/mobile versions.
Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2645
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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This commit contains a bevy of updates:
- PCI device id is updated to match Lynx Point EDS in the ME driver.
- Allocate the memory to store the consumption of the MBP.
- me_bios_payload structure is now a structure of pointers that point
into the allocated memory.
- The ICC profile structure was updated to correctly reflect the
documentation.
Verfied that output of MBP reading can handle unknown items.
Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2641
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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According to the 0.8.0 ME BWG this is a new state. It's not very clear
what exactly it entails, but the Basking Ridge CRB was tripping it when
MRC_DEBUG was enabled (presumably because of a DID timeout).
Instead of 0x17 one can now see the proper message for this state.
Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2640
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Some of the Lynx Point ids were off. Correct those and make
the pei data BAR fields consistent with the others.
Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2622
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The CS5536 companion device has three different power domains.
* working domain
* standby domain
* RTC domain
When the system is "off" only the standby domain is powered.
MFGPT[7:6] are member of the standby power domain.
MFGPT7 is used to control the backlight of the device and so the
timer gets used and configured during system boot. If the system
does a reboot the timer stays configured and the Linux driver
can not use it:
"ot200-backlight: ot200-backlight.0: MFGPT 7 not availale"
The cs5535-mfgpt has a function to hard-reset all MFGPTs but the
system hangs after the first access to a MFGPT register - cause
unknown.
/*
* This is a sledgehammer that resets all MFGPT timers. This is required by
* some broken BIOSes which leave the system in an unstable state
* (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to
* whether or not this secret MSR can be used to release individual timers.
* Jordan tells me that he and Mitch once played w/ it, but it's unclear
* what the results of that were (and they experienced some instability).
*/
static void reset_all_timers(void)
{
uint32_t val, dummy;
/* The following undocumented bit resets the MFGPT timers */
val = 0xFF; dummy = 0;
wrmsr(MSR_MFGPT_SETUP, val, dummy);
}
After playing around with this undocumented MSR it looks like I only
need to set bit 7 to free the MFGPT7.
BTW, all MFGPT[0:5] will be reset during pll_reset().
Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/2527
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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This is no longer tied to a GPIO but has a proper chipset pin.
Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2643
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The register that controls global reset is named the Power
Mangement Initialization Regiser (PMIR). Update the defines
to reflect the documentation.
Additionally, there is no core well reset control according to the
EDS. There is, however, a CF9 lock field to lock this register down.
Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2619
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The ME9 requirements have added some registers and changed some
of the MBP state machine. Implement the changes found so far in
the ME9 BWG. There were a couple of reigster renames, but the
majority of th churn in the me.h header file is just introducing
the data structures in the same order as the ME9 BWG.
Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18
Signed-Off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The IA32_ENERGY_PERFORMANCE_BIAS MSR can only be read or written
to if the CPU supports it. The support is indicated by ECX[3] for
cpuid(6). Without this guard, some Haswell parts would GP# fault
in this routine.
No more GP# while running on haswell CRBs.
Change-Id: If41e1e133e5faebb3ed578cba60743ce7e1c196f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2639
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
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In order for coreboot to assign resources properly the pci
drivers need to have th proper device ids. Add the host controller
and the LPC device ids for Lynx Point.
Resource assignment works correctly now w/o odd behavior because
of conflicts.
Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
|
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The reference code sends the dram init done command to the ME.
Therefore, there is no need for coreboot to do this.
Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2633
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Even though this is under the graysreef board it really
applies to the Basking Ridge board. A subsequent patch will
rename graysreef to baskingridge.
The GPIO pins were updated to reflect the Basking Ridge schematics
as well as the DIMM spd addresses and USB over current pins.
Change-Id: Ice4e05f5203de3024cd463dfccf0bcfec1e247c1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2632
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Add a FIXME about checking a MCHBAR register that isn't setup yet.
Also, remove revision updating because I can't find anything in the
docs that suggest this is required for haswell.
Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2631
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The intel-framework code has an updated pei_data structure.
Use the new structure and revision. Also, remove the scrambler
seed saving in CMOS since that appears to be handled in the saved
data from the reference code.
Change-Id: Ie09a0a00646ab040e8ceff922048981d055d5cd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2630
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change the hard coded values in udelay.c to use the #defines
for MSRs and BCLK.
Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2629
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Grays Reef is one of Intel's CRBs for the Haswell processor. The
platform is named Shark Bay.
GPIOs were the main focus so IRQ routing and ACPI still needs to be
further looked at.
Change-Id: Ie94b7af66f772714992a92612c76ca93b9b27088
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2621
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Boot haswell ULT and see LPT reported properly.
Change-Id: I48344a8dde6adbbf331c91231342de45b1b6c32a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2697
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is the steps outlined in the BWG.
It seems this is a lot simpler now (so far) which is good.
To test, boot to chromeos with 3.7 kernel + i915.preliminary_hw_support=1 and
see that the i915 driver complains a lot less than before and that a
splashscreen is displayed.
Change-Id: I722c90ecd351860949cedab24533f6c10e5b90e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2696
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This follows the new method outlined in the LPT BWG.
It is also very pedantic about its operation so it
is easier to read and compare against the docs and
the reference code implementation.
Change-Id: I235d634cded0c75ec0e9f53488f5b366107a18fa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2694
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add support for SMM modules by leveraging the RMODULE lib. This allows
for easier dynamic SMM handler placement. The SMM module support
consists of a common stub which puts the executing CPU into protected
mode and calls into a pre-defined handler. This stub can then be used
for SMM relocation as well as the real SMM handler. For the relocation
one can call back into coreboot ramstage code to perform relocation in
C code.
The handler is essentially a copy of smihandler.c, but it drops the TSEG
differences. It also doesn't rely on the SMM revision as the cpu code
should know what processor it is supported.
Ideally the CONFIG_SMM_TSEG option could be removed once the existing
users of that option transitioned away from tseg_relocate() and
smi_get_tseg_base().
The generic SMI callbacks are now not marked as weak in the
declaration so that there aren't unlinked references. The handler
has default implementations of the generic SMI callbacks which are
marked as weak. If an external compilation module has a strong symbol
the linker will use that instead of the link one.
Additionally, the parameters to the generic callbacks are dropped as
they don't seem to be used directly. The SMM runtime can provide the
necessary support if needed.
Change-Id: I1e2fed71a40b2eb03197697d29e9c4b246e3b25e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2693
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ib406b9d5005243d79eea5d2c0c6c86b5aa949891
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2721
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add a bootblock.c file for the northbridge and setup the
PCIEXBAR as the first thing using IO PCI config acceses.
After that all PCI config accesses can use MMIO.
Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2617
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.
This code partially gets up through the romstage just before training
memory on a Haswell reference board.
Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The original code attempted to reserve a space in RAM for coreboot to
remain resident. This turns out not to be needed, and breaks things
for the kernel since the exynos5250-smdk5250 kernel device tree starts
RAM at 0x40000000.
(This patch was originally by Gabe, I'm just uploading it)
Change-Id: I4536edaf8785d81a3ea008216a2d57549ce5edfb
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2698
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Change the OSC method to actually grant control of
PCIe capabilities to the OS instead of granting no
control. I believe the logic was backwards in the
original commit. Bits should be set when granting
control and cleared when not granting control. By
setting the return value to 0x00, we effectively
tell the OS that it cannot control any PCIe
capability. See section 6.2.9 of the ACPI spec
version 3.0 for more information.
This edit is a duplication of the OSC method that
is in the src/southbridge/intel/bd82x6x/pch.asl
file.
Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This enables branch prediction. We can probably find a better place
to do this, but for now we'll do it in snow's romstage main().
Change-Id: I86c7b6bc9e897a7a432c490fb96a126e81b8ce72
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2701
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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