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2016-05-25soc/apollolake: SOC specific SMM codeHannah Williams
Add SMI handlers that map to SOC specific SMI events Update relocation_handler in mp_ops Change-Id: Idefddaf41cf28240f5f8172b00462a7f893889e7 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14808 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25soc/intel/common: Add common smihandler codeHannah Williams
Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25vendorcode/google/chromeos/vboot2: use cbmem for postcar region selectionAaron Durbin
When the vboot cbfs selection runs in postcar stage it should be utilizing cbmem to locate the vboot selected region. Change-Id: I027ba19438468bd690d74ae55007393f051fde42 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14959 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-25console/post: be explicit about conditional cmos_post_log() compilingAaron Durbin
The current code was using !__PRE_RAM__ as a proxy for ramstage conditional compilation. In the face of postcar stage not defining __PRE_RAM__ (because it's after RAM is up) these code paths can fail to compile with a __SIMPLE_DEVICE__ defined for the entire stage. Remedy the current situation by just compiling explicity for ramstage because that was the original intent. In the future, the __SIMPLE_DEVICE__ selection for postcar can also be re-evaluated. Change-Id: I0f887f1e45f0cf5c235ae5144eaa227921e7119b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14958 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-25mainboard/intel/galileo: Enable USB device supportLee Leahy
Turn on the USB device port. TEST=Build and run on Galileo Gen2 Change-Id: Ic1fbb2cd51414ce927f2b408ccd27c7edf978744 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-25soc/intel/quark: Add USB device port supportLee Leahy
Add initialization for the USB device port. TEST=Build and run on Galileo Gen2 Change-Id: Icf83747f778f6e1ac976cd448a94311030e79e4f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-24arm64: Add stack dump to exception handlerJulius Werner
Some exceptions (like from calling a NULL function pointer) are easier to narrow down with a dump of the call stack. Let's take a page out of ARM32's book and add that feature to ARM64 as well. Also change the output format to two register columns, to make it easier to fit a whole exception dump on one screen. Applying to both coreboot and libpayload and syncing the output format between both back up. Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14931 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-24intel/amenia: Configure Trackpad IC_SDA_HOLD timeJagadish Krishnamoorthy
Elan trackpad needs greater sda hold time. Configure IC_SDA_HOLD register to increase the i2c sda hold time by 0.3us. Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-24vendorcode/chromeos/vbnv: Add CMOS init functionJagadish Krishnamoorthy
Add cmos init helper function. This function saves the Vboot NV data, calls cmos init and restores the Vboot NV data. Change-Id: I8475f23d849fb5b5a2d16738b4d5e99f112883da Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-23soc/intel/quark: Add EHCI errataLee Leahy
Move the EHCI errata from QuarkFSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I424ffd81643fbba9c820b5a8a6809b9412965f8d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14940 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-23soc/intel/quark: Rename usb.c to ehci.cLee Leahy
Rename usb.c to ehci.c since it contains EHCI specific content. TEST=Build and run on Galileo Gen2 Change-Id: Ifdb7cd937b1dffda1959b76e1c911ffd93f53cb6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14939 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-23soc/intel/quark: Switch reference from uart_dev to uart_bdfLee Leahy
Switch from using uart_dev to uart_bdf to better describe the value in use. TEST=Build and run on Galileo Gen2 Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14938 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-23soc/intel/apollolake: add support for writing logical boot partition 2Aaron Durbin
On apollolake the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. There's also a sort of recovery mechanism where there is a second data structure with similar contents halfway through the "BIOS" region. This second structure is referred as the logical boot partition 2 (LBP2), and it's optionally employed. Add support for writing the LBP2 to a specified FMAP region to accommodate platforms which require it. Change-Id: I1959a790f763b409238dea6b62408b42122e590e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14924 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-05-21program.ld: Don't exclude sbe region from verstageStefan Reinauer
This fixes compilation of coreboot on Glados Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> BRANCH=none TEST=emerge-glados coreboot works again BUG=none Change-Id: Ibaae68192a3dc070c6ecf79223da4a1e1f18b352 Reviewed-on: https://chromium-review.googlesource.com/346198 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Luigi Semenzato <semenzato@chromium.org> (cherry picked from commit d7c2c72698e81b1410f9839c77be2e77b8ed83d6) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14930 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Duncan Laurie <dlaurie@google.com>
2016-05-21apollolake: Add handler for finding ACPI path for GPIODuncan Laurie
Add a handler for soc/intel/apollolake to return the ACPI path for GPIOs. There are 4 GPIO "communities" on apollolake that each have a different ACPI device so return the appropriate name for the different communities. Change-Id: I596c178b7813ac6aaeb4f2685bb916f5b78e049b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14859 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21skylake: Add handler for finding ACPI path for GPIODuncan Laurie
Add a handler for the Intel Skylake SOC to return the ACPI path for GPIOs. Since all GPIOs are handled by the same controller they all have the same ACPI path and this is a simple handler that just returns a pointer to the GPIO device that is defined in the DSDT. Change-Id: I24ff3a6f2479d9e7eeace65d49e2f6c2e070f3e9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14843 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-21gpio: Add a function to map GPIO to ACPI pathDuncan Laurie
Add a new function "gpio_acpi_path()" that can be implemented by SoC/board code to provide a mapping from a "gpio_t" pin to a controller by returning the ACPI path for the controller that owns this particular GPIO. This is implemented separately from the "acpi_name" handler as many SOCs do not have a specific device that handles GPIOs (or may have many devices and the only way to know which is the opaque gpio_t) and the current GPIO library does not have any association with the device tree. If not implemented (many SoCs do not implement the GPIO library abstraction at all in coreboot) then the default handler will return NULL and the caller knows it cannot determine this reliably. Change-Id: Iaa0ff6c8c058f00cddf0909c4b7405a0660d4cfb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14842 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-21skylake: Add ACPI device name handlerDuncan Laurie
Add a global ACPI device name handler for the Skylake SOC that will translate skylake device paths into an ACPI path that matches the device objects delcared in the DSDT at soc/intel/skylake/acpi/*. The skylake implementation uses a global acpi_name handler for the SOC and it is not necessary to add a function to every device. This function is used by device drivers calling acpi_device_name() and acpi_device_path() to generate ACPI AML in the SSDT. Change-Id: I31cecf7905a51224e7bfc40c6c4ad2487f039097 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14841 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-21device: Add an ACPI device name and path concept to devicesDuncan Laurie
Add a function to "struct device_operations" to return the ACPI name for the device, and helper functions to find this name (either from the device or its parent) and to build a fully qualified ACPI path from the root device. This addition will allow device drivers to generate their ACPI AML in the SSDT at boot, with customization supplied by devicetree.cb, instead of needing custom DSDT ASL for every mainboard. The root device acpi_name is defined as "\\_SB" and is used to start the path when building a fully qualified name. This requires SOC support to provide handlers for returning the ACPI name for devices that it owns, and those names must match the objects declared in the DSDT. The handler can be done either in each device driver or with a global handler for the entire SOC. Simplified example of how this can be used for an i2c device declared in devicetree.cb with: chip soc/intel/skylake # "\_SB" (from root device) device domain 0 on # "PCI0" device pci 19.2 on # "I2C4" chip drivers/i2c/test0 device i2c 1a.0 on end # "TST0" end end end end And basic SSDT generating code in the device driver: acpigen_write_scope(acpi_device_scope(dev)); acpigen_write_device(acpi_device_name(dev)); acpigen_write_string("_HID", "TEST0000"); acpigen_write_byte("_UID", 0); acpigen_pop_len(); /* device */ acpigen_pop_len(); /* scope */ Will produce this ACPI code: Scope (\_SB.PCI0.I2C4) { Device (TST0) { Name (_HID, "TEST0000") Name (_UID, 0) } } Change-Id: Ie149595aeab96266fa5f006e7934339f0119ac54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14840 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21acpigen: Add function to generate ToUUID() from a stringDuncan Laurie
acpigen_write_uuid() will generate a ToUUID() 128-bit buffer object for a common universally unique identifier that is passed as a string. The resulting buffer is the UUID in byte format with a specific order of the bytes as described in the ACPI specification: ToUUID (uuid) Compiles to: Buffer (16) { uuid[3], uuid[2], uuid[1], uuid[0], uuid[5], uuid[4], uuid[7], uuid[6], uuid[8], uuid[9], uuid[10], uuid[11], uuid[12], uuid[13], uuid[14], uuid[15] } Change-Id: Ibbeff926883532dd78477aaa2d26ffffb6ef30c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14838 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21hexstrtobin: Add a library function to decode ASCII hex into binaryDuncan Laurie
This function will turn a string of ASCII hex characters into an array of bytes. It will ignore any non-ASCII-hex characters in the input string and decode up to len bytes of data from it. This can be used for turning MAC addresses or UUID strings into binary for storage or further processing. Sample usage: uint8_t buf[6]; hexstrtobin("00:0e:c6:81:72:01", buf, sizeof(buf)); acpigen_emit_stream(buf, sizeof(buf)); Change-Id: I2de9bd28ae8c42cdca09eec11a3bba497a52988c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14837 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-20sio/winbond: Expose enter/exit configuration state functionsTimothy Pearson
Certain mainboards, e.g. the ASUS KGPE-D16/KCMA-D8, require board-specific configuration changes to the SuperIO. Expose the functions needed to enter and exit configuration mode on Winbond devices. Change-Id: Ic86651872ecafcfe1398201be2b0768bbe460975 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14891 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-19src/Kconfig: Move acpi Kconfig below chipset KconfigsMartin Roth
The src/acpi/Kconfig was being sourced close to the top of the Kconfig tree, which doesn't allow it to be overridden by mainboards or chipsets. Moving it lower in the tree allows for the defaults to be overridden. Change-Id: I0b100f5535c5f383e8c6db74d0024c5ff2e8c08d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-19soc/intel/apollolake: Relocate FSP-M during insertion in CBFSAndrey Petrov
Since FSP-M is run in CAR (as opposed to XIP), its default link address may need to be changed. Since cbfstool can relocate FSP blobs, take advantage of that feature. Change-Id: I4353fe09d785c090843ce25ff4e654d45c64c381 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14866 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-19soc/apollolake/romstage: Add a timestamp at the start of romstageAlexandru Gagniuc
Change-Id: Idcfaba08e4705c6219a46dd615ae8b456a8ab5b4 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-19soc/apollolake/romstage: Call console_init before any printk()Alexandru Gagniuc
Follow the convention used on all other platforms and explicitly call console_init() before any printk(). This call was most likely ommitted by accident during rebase. Also remove the "Starting romstage..." message, as console_init() will print a standardized message. I don't have details on how this message originally appeared. Change-Id: Id91f0fc15ecbd3635d67a261907f4c6af9a499ab Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-19soc/apollolake: Pass earliest timestamp to timestamp_initAlexandru Gagniuc
We have a timestamp from before cache-as-ram setup saved in the MMX registers. Recover that timestamp, and use it as the base timestamp rather than letting lib/bootblock.c use a late timestamp. This allows more accurate profiling of the boot flow, since CAR setup time is no longer excluded from the timing information. Change-Id: I055092c600438c5260ab67509434a38f1eb77fe4 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14863 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-19lib/bootblock: Provide mechanism to pass in an early timestampAlexandru Gagniuc
This is useful, for example, in the bootblock, when a timestamp is available which predates the call to main() in lib/bootblock.c Change-Id: I17bb0add9f2d8721504b2e534dd6904d1201989c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-05-19lib/timestamp: Do not initialize cache in timestamp_cache_get()Alexandru Gagniuc
timestamp_cache_get() would call timestamp_cache_init() whenever it found a timestamp cache in the TIMESTAMP_CACHE_UNINITIALIZED state. That means that timestamp_cache_get() will never reurn a cache in the uninitialized state. However, timestamp_init() checks against the uninitialized state, as it does not expect timestamp_cache_get() to perform any initialization. As a result, the conditional branch can never be reached. Simply remove the timestamp_cache_init() call from timestamp_cache_get(). Change-Id: I573ffbf948b69948a3b383fa3bc94382f205b8f8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14861 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-19arch/x86: Include timestamp.c in all stagesAlexandru Gagniuc
timestamp.c was not included in bootblock and postcar. This means that these two stages would use the weak implementation in lib/timestamp.c instead of the arch-specific implementation based on rdtsc. This resulted in using timer_monotonic_get() which resets the timestamps from 0. timer_monotonic_get() only provides per-stage incrementing semantics on x86 because lapic implementation has counting down values. A globally incrementing counter like rdtsc provides the semantics like every other non-x86. On the test configuration, the weak implementation of timestamp_get() returned zero, resulting in wrong timestamps coming from the bootblock, while romstage and ramstage used the arch implementation and returned correct timestamps. This is a great example of why weak functions are dangerous, and how easy it is to miss subtle yet strong interactions between subsystems and the coreboot buildsystem. Change-Id: I656f9bd58a6fc179d9dbbc496c5b684ea9288eb5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14860 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-19soc/intel/apollolake: clear up ACPI timer emulation magic constantAaron Durbin
The timer emulation works by deriving a frequency based off the Common Timer Copy with a frequency of 19.2MHz. The desired frequency = (19.2MHz * multiplier) >> 32; With that knowledge update the code to let the compiler perform the necessary math based on target frequency. Change-Id: I716c7980f0456a7c6072bbaaddd6b7fcd8cd5b37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14889 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-19soc/apollolake/lpc_lib: Make cros compile passZhao, Lijian
The print of size_t can pass upstream jenkins, but fails with CROS_SDK enviornment, "%z" fits for size_t anyway. Change-Id: Ic8dbab240463f2e484b73d55e21985fae2b0d9b7 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14835 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-18rockchip: rk3399: enable sdhci clk for emmcShunqian Zheng
If booting from sdcard/usb, kernel can't recognize the /dev/mmcblk0. Before kernel find it's root cause, we add this workaround patch to enable clk for emmc. BRANCH=none BUG=chrome-os-partner:52873 TEST=boot from sdcard and check the /dev/mmcblk0 exists Change-Id: Ie36cc6fdbc24db8c30984c02ccfe2f8aaaf30cd2 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 39b87ec3c73d6f56efc8c3f52b7ed759e548ee85 Original-Change-Id: I88a9cc2e3ea5a56aadfdbd94ef910daaf92a7eb7 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341632 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14856 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: configure emmc clkLin Huang
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18ec/google/chromeec/acpi: Add MKBP supportGwendal Grignou
Allow EC to send an interrupt using ACPI SMI when a MKBP event is available. This will be used by the sensor stack. Update all ACPI branch except those without sensors with: for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+ | cut -d '/' -f 2 | grep -v -e cyan -e lars); do echo $i cd $i git diff ../lars/ec.h | patch -p 5 cd - done BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890 Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14854 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-18rk3399: set proper configuration of SDMMC interfaceVadim Bendebury
For proper interface operation the drive strength on all pins is set to 8 mA and all pull ups/pull downs disabled, this matches the current kernel configuration. BRANCH=none BUG=chrome-os-partner:53257 TEST=it is possible to boot Chrome OS on Gru from various micro SD cards which were failing to boot before. Change-Id: Ie43e52a52cd0513d48d0ecc8ac02fbb100baf9a4 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6bb0549ed728ac3c5faab6cbe16e2487400e67ed Original-Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344491 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14853 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rk3399: add GPIO register definitions for SDMMC0Vadim Bendebury
The code needs to be able to set drive strength for the pins used for SDMMC0 interface. This patch adds the definitions for the two registers, as per page 378 of the RK3399 TRM Part 1. Instead of calculation of the reserved range size just use known offsets of the registers included in the structure. BRANCH=none BUG=chrome-os-partner:53257 TEST=with the upcoming driver change it is possible to boot chrome OS on Gru from various micro SD cards which were failing before. Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: c6d6dc5e5e6cc81c173603d4eb21ae803a47815d Original-Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344490 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14852 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18gru: set correct gpio for SD card detectVadim Bendebury
The only outlier at this time is Kevin rev 0, treat it specially, the rest of the targets use the same GPIO. BRANCH=none BUG=none TEST=gru still boots off SD card just fine Change-Id: Ic603093a990d27166b16175db3303f155b4775aa Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5788c5add1d1f803e7b22fb53215b6003ac04d03 Original-Change-Id: Ic5183f08dd1119f9588f243bd9e9c080d84687f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344151 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14851 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18Gru: support 4GB sdram on gruLin Huang
now we use 4GB sdram on gru board, enable it. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from kevin board Change-Id: Icc483a8ba91c5deea85e6e4009a8a132851b1853 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: efa94aee02bedf51d73c91059b06afcbb1320282 Original-Change-Id: I26f77ff4ad9b2aa35ab5ff50f23984796f4f06bc Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342585 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14850 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: improve sdram driverLin Huang
improve rk3399 sdram drvier, so we can support DDR3, and check the cs training result, so we make sdram work more stable. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from kevin, do memtester in kernel and pass Change-Id: I508bf26fb8163bab2d725a91ead929df585e04a7 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 4d83a87c459167145b7260f9af5c0380caddc056 Original-Change-Id: Id385f1343804a829b6589f89f4cfbb6565d41417 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342664 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14849 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: add tsadc driverShunqian Zheng
This patch configures clock for tsadc and then makes it in automatic mode to generate TSHUT when CPU temperature is higer than 120 degree Celsius. BRANCH=none BUG=chrome-os-partner:52382,chrome-os-partner:51537 TEST=Set a lower tshut threshold(45C), run coreboot and check that coreboot reboot again and again. Change-Id: I0b070a059d2941f12d31fc3002e78ea083e70b13 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 05107bd6a3430e31db216c247ff0213e12373390 Original-Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342797 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/14848 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: revert the common tsadc headerShunqian Zheng
The tsadc of rk3288 and rk3399 are similar but not enough to share the same common driver, and we also decide to add a polarity setting for mainboards on rk3399 tsadc header. So we'd better split the tsadc header for each SoC. BRANCH=none BUG=chrome-os-partner:51537 TEST=build veyron_jerry Change-Id: I41f08965e6d7ce16da1754d4d2512c826cf8aff5 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b36ee54c4146623bcacd83fe7d55a4fc78bae792 Original-Change-Id: I629599f9e30d863cabf764e1372c38f0f39d5480 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342796 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14847 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: add routines to set vop clocksShunqian Zheng
Let vop aclk sources from CPLL, and vop dclk from NPLL. The dclk freq is decided by the edid mode pixel_clock which may require high accuracy like 252750KHz. The pll_para_config() can calculate the dividers for PLL to output desired clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=check display with the other patches Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 0f019b055fffebe9ea3928aae1e25b0ad4feef81 Original-Change-Id: Icef58f87041905961772b69c6b8170d5a866a531 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342335 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14846 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18AGESA vendorcode: Build a common amdlibKyösti Mälkki
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18AGESA vendorcode: Move compiler class definitionKyösti Mälkki
Change-Id: Ia4cef7d584e43f1911db2f81d8b86ed406b75aad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-18soc/intel/apollolake: Enable ACPI PM1 timer emulationAndrey Petrov
Enable emulation for ACPI PM1 timer. This is needed by FSP-M MemoryInit. Change-Id: I7a441f5f1673e6430697615ae7251da948e77548 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/apollolake: Remove hardcode for TCO watchdog timerAndrey Petrov
Change-Id: Ie528b0ee3d447dcb819ccb7c0f832885da0f4257 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14820 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18soc/intel/apollolake: Work around FSP-M CAR layoutAndrey Petrov
As of now FSP-M can not be relocated and it can not be instructed to use a specific resource for temporary memory. As result coreboot is forced to use CAR layout dictated by default FSP-M configuration. Change CAR size to 1MiB, link romstage at such CAR address so it doesn't overlap with FSP-M's default heap/stack. Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18soc/intel/apollolake: Do not use StackBase FSP-M parameterAndrey Petrov
Currently, StackBase field doesn't work and changing it from default value leads to crash. Change-Id: Id3f3ea9a834d0c04a8381938535109d6a729cca2 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFSAndrey Petrov
Add recipes that insert FSP blobs into CBFS and get rid of CBFS names hardcoding. Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-18soc/intel/apollolake: Take advantage of common opregion codeAndrey Petrov
Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add IGD OpRegion supportAndrey Petrov
Add helper function that fills OpRegion structure based on VBT file content and some reasonable defaults. Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add utility to load VBT fileAndrey Petrov
Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18mainboard/intel/galileo: Add I2C chip initializationLee Leahy
Add I2C chip initialization for the Galileo boards. TEST=Build and run on Galileo Gen2 Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14829 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18soc/intel/quark: Add I2C supportLee Leahy
Add the I2C driver. TEST=Build and run on Galileo Gen2 Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14828 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Fix spelling errorLee Leahy
Change Memroy to Memory in comment. TEST=None Change-Id: Ic57fcf962be6a302dcd7b52b9256a182577e734b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14881 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Perform GPIO initializationLee Leahy
Set the base address and enable the GPIO and legacy GPIO controllers. Call the mainboard routine to initialize the GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17mainboard/intel/galileo: Add GPIO initializationLee Leahy
Add Kconfig to configure coreboot for a specific Galileo board. Configure the GPIOs for the specific Galileo board. TEST=Build and run on Galileo Gen2 Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17acpigen: Fix ?: operator confusionJonathan Neuschäfer
strlen(string) was on the "negative" side of the selection operator, the side where string is NULL. Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae Reported-by: Coverity Scan (CID 1355263) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-17soc/intel/quark: Add GPIO register accessLee Leahy
Add register access routines for the GPIO and legacy GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I0c023428f4784de9e025279480554b8ed134afca Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add LPC symbolsLee Leahy
Add LPC_DEV and LPC_FUNC symbols TEST=Build and run on Galileo Gen2 Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Reformat include/soc/pci_devs.hLee Leahy
Replace # define with #define Align the right hand column to prepare for further expansion TEST=Build and run on Galileo Gen2 Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp1_1: Simplify union referencesLee Leahy
Simplify the union references to enable Coverity to properly process the routine. Found-by: Coverify CID 1349854 TEST=Build and run on Galileo Gen2 Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14870 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp1_1: Replace for/break with returnsLee Leahy
Coverity does not like the use of for/break, switch to using returns instead. Found-by: Coverity CID 1349855 TEST=Build and run on Galileo Gen2 Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add Ioh.h from EDK-IILee Leahy
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and coreboot implementations. TEST=Build and run on Galileo Gen2 Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14824 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-05-17drivers/intel/fsp2_0: Fix array indexing errorLee Leahy
Don't allow an array index of 2 to be processed by the code referencing the array. Found-by: Coverity CID 1353337 TEST=None Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14868 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-17mainboard/google/reef: add first pass of full pad configurationAaron Durbin
This is an initial stab of configuring the reef pads. Change-Id: I8d8060745af6fbada268c6c6f3492b985ddf9eb8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14831 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2016-05-16vboot: Call verification_should_run directly in the if statementPaul Kocialkowski
Using a dedicated variable is slightly less readable and makes the code less consistent, given that other test functions are called directly in the if statements. Change-Id: If52b2a4268acb1e2187574d15cc73a0c1d5fe9bb Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14817 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-16acpigen: Add functions to generate _STA() and _PRW()Duncan Laurie
Add helper functions for generating some common objects: acpigen_write_STA(status) will generate a status method that will indicate the device status as provided: Method (_STA) { Return (status) } Full status byte configuration is possible and macros are provided for the common status bytes used for generated code: ACPI_STATUS_DEVICE_ALL_OFF = 0x0 ACPI_STATUS_DEVICE_ALL_ON = 0xF acpigen_write_PRW() will generate a Power Resoruce for Wake that describes the GPE that will wake a particular device: Name (_PRW, Package (2) { wake, level } Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14795 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16acpigen: Add an abstracted integer output methodDuncan Laurie
In order to produce smaller AML and not rely on the caller to size the output type appropriately add a helper function that will output an appropriately sized integer. To complete this also add helper functions for outputting the single OpCode for Zero and One and Ones. And finally add "name" variants of the helpers that will output a complete sequence like "Name (_UID, Zero)". Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-16acpigen: Add helper functions for stringsDuncan Laurie
Add helper function to emit a string into the SSDT AML bytestream with a NULL terminator. Also add a helper function to emit the string OpCode followed by the string itself. acpigen_emit_string(string) /* Raw string output */ acpigen_write_string(string) /* OpCode followed by raw string */ Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14793 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-16acpigen: Add helpers for word/dword outputDuncan Laurie
Add helpers for writing word and dword values in acpigen and use them throughout the file to clean things up: acpigen_emit_word - write raw word acpigen_emit_dword - write raw dword acpigen_write_word - write word opcode and value Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-16sconfig: Add a new generic device typeDuncan Laurie
Add support for a basic generic device in the devicetree to bind to a device that does not have a specific bus, but may need to be described in tables for the operating system. For instance some chips may have various GPIO connections that need described but do not fall under any other device. In order to support this export the basic 'scan_static_bus()' that can be used in a device_operations->scan_bus() method to scan for the generic devices. It has been possible to get a semi-generic device by using a fake PNP device, but that isn't really appropriate for many devices. Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid everything being rewritten. Clean up the local paths that leak into the generated configs. Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16sconfig: Add 10bit addressing mode to i2c device typeDuncan Laurie
Use the second token for an i2c device entry in devicetree.cb to indicate if it should use 10-bit addressing or 7-bit. The default if not provided is to use 7-bit addressing, but it can be changed to 10-bit addressing with the ".1" suffix. For example: chip drivers/i2c/generic device i2c 3a.1 on end end Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13mainboard/google: add reef reference boardAaron Durbin
This adds the initial scaffolding for the reef reference board. One big thing missing is the GPIO configuration. Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f Signed-off-by: Aaron Durbni <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13soc/intel/apollolake: provide common LPDDR4 memory initAaron Durbin
Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. Change-Id: I686eb3097c33399a3b94af89237f7fe1b2d34c2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14790 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13vendorcode/intel/fsp1_0: Don't break GCC strict aliasingStefan Reinauer
Change-Id: I6b345670db7df652b8b712b721dfe2905373e0d5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14630 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-05-13HobLib: Don't break GCC strict aliasingStefan Reinauer
Change-Id: I1bd33e423b0fcb69597e001b61c6ea916f5fe44a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14622 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-13AMD fam14: Blacklist Intel Centrino n6235 from PCIe ASPMKyösti Mälkki
PCI device ID of this mini-PCI-e WLAN card is 8086:088e. With this card inserted on pcengines/apu1 mini-PCI-e slot J17, system halts late in ramstage, in agesawrapper AMD_INIT_MID. Offending operation is enabling PCIe ASPM L0s and L1 for the card. That is, writing PCIe capability block Link Control [1:0] = 11b in the card's configuration space. AGESA already has a blacklist for the purpose of masking such unstable ASPM implementations. Change-Id: I9623699c4ee68e5cdc244b87faf92303b01c4823 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/8496 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-13soc/intel/apollolake: implement common gpio APIAaron Durbin
In order for apollolake mainboards to utilize the common GPIO API it actually needs to be implemented. Change-Id: I41de8d5d9f3c39e7e796eae73b01cb29e9c01347 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14797 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13ec/google/chromeec: don't guard function declarationsAaron Durbin
In order to allow using the same C source to be compiled for multiple stages (with #if/#endif guards) one needs the necessary function delcarations. Therefore, remove the guards. Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14796 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12soc/intel/apollolake: use common FADT infrastructureAaron Durbin
Instead of having the mainboards duplicate the same boilerplate code utilize the common FADT infrastructure to reduce duplication. Change-Id: If824619fd619433974e588050a933d2c19b97ec8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14779 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12AGESA vendorcode: Drop alternate image dispatcherKyösti Mälkki
Not used as we link AGESA into same romstage and ramstage ELF. Change-Id: Ia427b9c0cc88b870de75df14bba4ca337a28adff Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12AGESA f12: Build as libagesa.aKyösti Mälkki
Change-Id: If48fffee1441b6bb012a8d99abb794f7a35efcf6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14412 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12AGESA f16kb: Build as libagesa.aKyösti Mälkki
Change-Id: I9faeda508694f950f1b025765e2ac63bc91747fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14411 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12soc/apollolake: Handle non-standard ACPI BAR in PMC deviceAlexandru Gagniuc
The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means that probing may not work. In that case, a resource still needs to be created for the BAR. BONUS: We now avoid the need to declare the MMIO resources as fixed. Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14634 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriateAlexandru Gagniuc
FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12soc/intel/common/mrc_cache: Don't assume FMAP is tied to CHROMEOSAlexandru Gagniuc
The old code only checked for an RW_MRC_CACHE region when CONFIG_CHROMEOS was selected. This assumption is not necessarily true, as one can have FMAP without a CHROMEOS build. As a result, always search FMAP first before falling back on CBFS for locating the MRC cache region. The old logic where CHROMEOS builds would fail when RW_MRC_CACHE was not found is preserved, such that behavior does not change. Change-Id: I3596ef3235eff661af055968ea641f3e9671cdcd Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14757 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12drivers/intel/fsp2_0: Add timestamps around all calls to the blobAlexandru Gagniuc
Change-Id: I384cef0f5b4b71dbd7ad6d1d508e7c6395bf3f2d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-12soc/apollolake/uart.c: Do not NOOP .set_resources() and friendsAlexandru Gagniuc
When SOC_UART_DEBUG was not set, the boot would hang somwhere in ramstage, as evidenced by POST codes reported from the EC. This was traced to the .set_resources and .enable_resources members of the UART PCI driver being set to NOOP. Although the exact mechanism of failure is not known, this change eliminates the hang. Change-Id: Ic2f3d56a964ec890ebfa1e1a7770f1ae2eb22281 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14771 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12intel/amenia: Enable touchscreen in ACPIFreddy Paul
Add support for Elan touchscreen on I2C3 for amenia BUG=None TEST=Boot to Chromium OS and verify if touchscreen is working. Change-Id: Ic75bef0e5878bd5b8c0d727400679663d9f591e3 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14768 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-11ec/google/chromeec: provide way to query ioport rangeAaron Durbin
In order to provide other stages access to the ioport range required by the ChromeEC provide google_chromeec_ioport_range() function to fill in the details. Currently, the ioport range is only consumed by the LPC implemenation. Also allow ec_lpc.c to be built for the bootblock stage. Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14769 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-11lib: remove FLASHMAP_OFFSET config variableAaron Durbin
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-11soc/samsung: Don't compile in unused uart divider tablesStefan Reinauer
Change-Id: I58b2c3c52444d9a755d05529992507086a423f1a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14620 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-05-11soc/intel/quark/include/soc: Update the Intel licenseLee Leahy
Remove the phrase "which accompanies this distribution" from the license. Re-format the license to fit in 80 columns. TEST=Build and run on Galileo Gen2 Change-Id: I8d893cf1270b95b27eab7142b276ebfce24ec2ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14774 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-11cbfstool/fsp: Rename fsp1_1_relocateFurquan Shaikh
FSP 2.0 uses the same relocate logic as FSP 1.1. Thus, rename fsp1_1_relocate to more generic fsp_component_relocate that can be used by cbfstool to relocate either FSP 1.1 or FSP 2.0 components. Allow FSP1.1 driver to still call fsp1_1_relocate which acts as a wrapper for fsp_component_relocate. Change-Id: I14a6efde4d86a340663422aff5ee82175362d1b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-05-11util/cbfstool: Allow xip/non-xip relocation for FSP componentFurquan Shaikh
Currently, convert_fsp assumes that the component is always XIP. This is no longer true with FSP 2.0 and Apollolake platform. Thus, add the option -y|--xip for FSP which will allow the caller to mention whether the FSP component being added is XIP or not. Add this option to Makefiles of current FSP drivers (fsp1_0 and fsp1_1). Change-Id: I1e41d0902bb32afaf116bb457dd9265a5bcd8779 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-10arch/arm64: add FRAMEBUFFER region macros to memlayoutLin Huang
BRANCH=none BUG=chrome-os-partner:51537 TEST=build pass Change-Id: Id3dd3a553370eada1e79708dc71afc2d94d6ce93 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0949b0d9ec12eff7edb3d7de738833f29507c332 Original-Change-Id: I8052f86d4d846e5d544911c5b9e323285083fb5c Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340024 Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10qualcomm/ipq40xx: drop commentPatrick Georgi
The origin of UART config is less interesting than having the config be correct. Change-Id: I834e3a54105a8fd7d62f388e4a9ad0992ecec807 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14767 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)