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Some DIMMs have invalid strings when it comes to device part number
(bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused
space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ),
all others should be ASCII.
Create a test that detects invalid strings and replace invalid
characters with *. If a replacement was made the output string then must
be <Invalid (replaced string)>.
BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Use code to examine SMBIOS,
while testing different valid and invalid strings.
Remove string injection before committing.
Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Kahlee DIMM have invalid string when it comes to part number
(bytes 0x149-0x15c). We currently force a NA string, but grunt has the
proper strings. Just let the string go through, and a second commit
within smbios.c will be responsible for testing the string and taking
proper action.
BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Remove string injection before
committing.
Change-Id: I427262873f9ec80f459245e5f509e28a68de3074
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change removes extra newline characters from print statements for
wake masks.
Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Coverity scan has found an error where a NULL pointer is dereferenced.
The bug would happen if the devicetree does not contain a valid entry
for PCA9538. In this case the code
* if (dev->path.i2c.device == PCA9538_SLAVE_ADR)
would dereference to a NULL pointer.
This patch fixes this issue. Thanks coverity!
Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL))
Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.
dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.
BUG=b:72523836
TEST=none
BRANCH=fizz
Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This change adds a config option to allow mainboard to override
the console loglevel. When the option is set, the platform has
to define the function get_console_loglevel returning a valid
loglevel value.
This allows a mainboard to sample a GPIO to switch the loglevel
value between different environments (qualification vs production)
without re-flashing.
Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.
BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.
Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.
TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858
Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This commit defines a set of macros for defining GPIO configuration that
are easier to read than the raw iomux function values used today.
TEST=None
BUG=b:72875858
Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Turn on PCH iSCLK for meowth platform.
BUG=None
TEST=Boot up into OS and check register programming with iotools, the
command is iotools mmio_read32 0xfdad8000, returned value is 0x03.
Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order for ddr2.h and ddr3.h to be included in the same file it
cannot have conflicting definitions, therefore rename a few things and
move some things to a common header.
Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed
from the latest EC codebase, so don't try to build them by default
anymore.
Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.
BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.
Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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EMMC and SD Controller port id listed here, the port id definition came
from Cannonlake BIOS Writer Guide 570374.
BUG=None
TEST=None
Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add NHLT and dt support for meowth with max98373 amp.
BUG=b:71724897
TEST='emerge-meowth coreboot' compiles correctly
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373
Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Since FSP version 7.x.11.43, more HDA Audio link options are exposed,
so included that into coreboot. Users can modify that base on platform
implementations.
BUG=None
TEST=Boot up with debug build version FSP and check the debug print
result on meowth platform.
Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.
Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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finalize()
This patch ensures common code provides an option to register a
SOC specific SMI handler before booting to OS (specifically during ramstage).
Change-Id: I50fb154cc1ad4b3459bc352d2065f2c582711c20
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tung Lun Loo <tung.lun.loo@intel.com>
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This function performs SBI communication
Input:
* PID: Port ID of the SBI message
* Offset: Register offset of the SBI message
* Opcode: Opcode
* Posted: Posted message
* Fast_Byte_Enable: First Byte Enable
* BAR: base address
* FID: Function ID
* Data: Read/Write Data
* Response: Response
Output:
* 0: SBI message is successfully completed
* -1: SBI message failure
Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23809
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow bootblock to get access to the entire static device tree
as other stages can access independently.
TEST=SMM code now can access devicetree.cb variables.
Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Once the FADT reports that they don't exist it makes no sense to have
them in ACPI's device tree.
Change-Id: Ice82f0de592b6ca955148479fecc8506a7cdcddc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: dhaval.v.sharma@intel.com
Reviewed-on: https://review.coreboot.org/23835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SKL/KBL PCH does not support legacy devices. This change removes the
setting of ACPI_FADT_LEGACY_DEVICES flag in FADT for SKL/KBL.
It helps Linux kernel to disable controllers required to support legacy
devices only e.g. i8237 DMA controller.
BUG=b:72679357
Change-Id: Ie2a85a719997157f52b0eab7254689f5a56ba05b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a function to configure interrupt settings for a GPIO. This does
not currently configure GEVENT signals.
The second function returns the GPIO interrupt status and clears the
flag if set.
BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt
Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The rationale is to allow the mainboard to override the default
baudrate for instance by sampling GPIOs at boot.
A new configuration option is available for mainboards to select
this behaviour. It will then have to define the function
get_uart_baudrate to return the computed baudrate.
Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Save the UMA values from AGESA to use in resource
allocation in ramstage.
Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23817
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some assumptions are made with respect to CONFIG_ROM_SIZE being the
actual size of the boot medium, e.g. when automatically creating an
fmap with and RW_MRC_CACHE region. With this patch the user is
warned when this is detected.
Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The result is shorter and (IMHO) more readable code.
Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.
BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/,
the Intense PC does not look like a laptop. In its documentation it is
described as "mini-PC" or "Single Board Computer".
This patches moves the Intense-PC into the correct category on the
Supported Motherboards page.
Due to thermal considerations, I have not removed the "select
SYSTEM_TYPE_LAPTOP" in Kconfig.
Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC")
Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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These exceptions were new in the Privileged Architecture spec 1.10.
We need to delegate them to S-mode.
Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Update encoding.h to the version shipped with spike commit
0185d36 ("Merge pull request #165 from riscv/small_progbuf"),
and copy the license header from the LICENSE file.
Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.
As a first step, pass the bootrom-provided FDT to the payload,
unmodified.
Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Due to changes in the RISC-V Privileged Architecture specification,
Linux can now be started in physical memory and it will setup its own
page tables.
Thus we can delete most of virtual_memory.c.
Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.
NOTE: Spike does support RVC, but currently doesn't select
ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
support RVC.
Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.
Add the necessary alignment directive before trap_entry.
Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
... and fix them in the process.
The Kconfig help text seems to be a slightly better place for such
documentation than a comment in Kconfig.
Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The ATF tegra210 platform supports more than the currently used
'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h
in the ATF tree.
Add the missing parameters and set them accordingly. The passed UART id
is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the
same port for console output as coreboot.
Successfully tested with UARTB.
Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Don't always set up UARTA, but instead honor
CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the
chosen UART.
Now the matching clock for the used UART is set up.
(The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which
in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.)
Change-Id: Ife209d42af83459136a019c21c2a069396ab36db
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
These small helper functions aim at supporting the user setting
CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.
Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
These are required to honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx later
on.
Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This patch syncs ec_commands.h with the one in chromeec.
BUG=b:70294260
BRANCH=none
TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz.
Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Fizz fails to show pictures on a type-c monitor because VBIOS runs
before DisplayPort link is ready.
With this patch, when firmware needs to display something, Fizz calls
google_chromeec_wait_for_display to make sure display is ready.
The penalty is up to 2 sec per boot in dev and rec boot. Normal boot
won't affected unless there is EC update.
BUG=b:72387533
BRANCH=none
TEST=Verify screens are displayed on Fizz as follows:
1. Put DUT in normal mode
2. Flash EC image to trigger EC sync (critical update)
3. Trigger manual recovery (insert)
4. Hit ctrl+d to switch to dev mode (to-dev)
5. Confirm to reboot (dev warning)
6. Warm reboot (dev warning)
7. Cold reboot (dev warning)
8. Flash EC image to trigger EC sync (critical update)
9. Trigger manual recovery (insert)
Change-Id: I90befe94f93e13904987acda50b2598d034b0031
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The google_chromeec_wait_for_display API checks whether a display is
ready or not. It waits in a loop until EC says it entered DisplayPort
alternative mode or times out in 2 seconds.
BUG=b:72387533
BRANCH=none
TEST=See 23746 "mb/google/fizz: Wait until display is ready"
Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
The google_chromeec_pd_get_amode API checks whether TCPM is in a
specified alternate mode or not.
BUG=b:72387533
BRANCH=none
TEST=See 23746 "mb/google/fizz: Wait until display is ready"
Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Soraka, Poppy & Nautilus are designed to operate at max power of
45 Watt. Hence set psys_max to 45W.
BUG=b:66066340
BRANCH=None
TEST=Build and boot soraka.
Change-Id: If6f624733830b462329b5f539c20e2aea664143e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/23757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.
Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.
Remove the setup from model_15_init.c because this is duplicated
functionality.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
AMD's fixed MTRRs have RdDram and WrDram bits that route memory
accesses to DRAM vs. MMIO. These are typically hidden for normal
operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to
BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at
reset, should be set for configuration during POST, then cleared for
normal operation.
Attempting to modify the RdDram and WrDram settings without unhiding
them causes a General Protection Fault. Add functions to enable and
disable MtrrFixDramModEn. Unhide/hide as necessary when copying or
writing the fixed MTRRs.
Finally, modify sipi_vector.S to enable the bits prior to writing
the fixed MTRRs and disable when complete.
This functionality is compiled out on non-AMD platforms.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The board does no support eMMC so no need to configure it.
Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The board does not have memory down, only 2 DDR4 Slots.
Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
SMBIOS structure type 17 is not being generated because memory info is
not being stored to cbmem. This has to happen after AGESA AmdInitLate
has run, but before SMBIOS is generated. There's a need to convert
format between AGESA generated info, and what is required in cbmem.
Create a procedure that transfers information between AGESA and cbmem,
and call it from agesawrapper_post_device() after AmdLateInit is called.
BUG=b:65403853
TEST=build and run kahlee, verify if SMBIOS structure type 17 is being
generated, and if associated strings are what should be expected.
Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.
BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.
Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Switch to use common version of PCR asl.
BUG=NONE
TEST=Boot up into chrome OS properly on cannonlake rvp platform.
Change-Id: I4975704434d4743bcc0fb6062115da349166c3a6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.
BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK
Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Using common PCR asl for skylake/kabylake platform.
BUG=None
TEST=None
Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Access to PCH Private Configuration Space Register can be addressed via
SBERG_BAR, the method is generic across several generations of Intel
SOC.
BUG=None
TEST=None
Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Fill the missing GPIO pin definitions, includeing community 3.
Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22482
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.
BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.
Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This change enables DPTF and configures the policy. DPTF parameters were
provided by internal power team.
BUG=b:67877437
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23731
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Read cse file was not getting cached and taking about 500ms on every boot.
Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add the missing *r* of the possessive pronoun *your*.
Change-Id: I2b520f398a904eb8e4412835d90bde1ee0b504b7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Procedures acpi_device_scope() and acpi_device_name() can under certain
conditions return NULL. Check the return before using them.
This fixes CID 1385944
BUG=b:73331544
TEST=Build kahlee.
Change-Id: Ifcdf905100d22a1d828394f8685641eb432bb836
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23760
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Procedure mrc_cache_get_current() returns -1 for error, 0 for pass. Do
check the return in procedure get_s3nv_info.
This fixes CID 1385943
BUG=b:73333332
TEST=Build kahlee
Change-Id: I0f6a58380a38d13120e997dcd966423d3c2af091
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.
Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Show mainboard version in the console log so that one can easily see it.
Change-Id: I33bae8b340fce13c0cbe525521828929038b069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.
Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C
bus. Add a chip driver to support this chip.
Beside the pure chip driver two interface functions are provided to read
the state of the pins and write output values to the pins.
As the slave address of this chip is hardware configurable the function
pca9538_get_dev() is used to get the right slave address. This function
needs to be implemented in mainboard code if one needs to use the
interface functions to read and write I/O state.
Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fixes: b8dc63bdfe ("ic2/designware: Move Intel i2c logic to shared driver")
Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23714
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
1. Add PeciSxRest option.
2. Add Thermal Velocity Boost option.
3. Add VR power deliver design option.
4. Match MrcChannelSts.
TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Reviewed-on: https://review.coreboot.org/23677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add missing license and include guard and remove unneeded include.
BUG=b:72121803
TEST=compiles
Change-Id: Ic359ed262086596a98131669f8eecd531857187a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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LAPIC setup is required to set virtualwire mode for legacy interrupts.
This was omitted when stoneyridge was changed to use the common mp_init.
BUG=b:72351388
TEST=Verify keyboard now works in SeaBIOS
Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Original SPD provided by the vendor had bytes after 254 shifted by 16
bytes. This change fixes the SPD data based on the latest details
received from the vendor.
BUG=b:72749394
TEST=Verified that the device with this memory part boots to OS fine.
Also, mosys is able to dump the right memory information.
Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This adds a struct for registers along with some bits from ATF to
the generic PL011 driver. It also adds a naive implementation of
uart_tx_flush() which was previously stubbed out.
Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I89cf4b996405af616f54cf2d9fabd4e258352b03
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23036
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are now a few architectural extensions available for ARMv8, some
of which introduce instructions or other features that may be useful.
This allows the user to select an extension implemented on their SoC
which will set the -march option passed into the compiler.
Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:69011806, b:72179988
BRANCH=master
TEST=Verify touchscreen on meowth works with this change.
Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/23551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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TEST=Run powerd_dbus_suspend and resume with button press
BUG=b:69614064
Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22732
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add/update the romstage and ramstage paths to check for S3 resume
and call the appropriate AGESA functions.
TEST=Suspend/Resume Kahlee with full S3 patch stack
BUG=b:69614064
Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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AMD support in coreboot has typically not used the AmdS3FinalRestore()
Entry Point. Add a call to it immediately prior to resuming to the OS.
BUG=b:69614064
TEST=Check console log for execution
Change-Id: Iadc4438d8cda9766002f6edade3c7b00b23b98b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new functions that can execute InitRtb, InitResume, LateResume,
and FinalResume.
Note that the name AmdInitRtb supersedes the deprecated AmdS3Save.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The Arch2008 spec describes an AmdS3FinalRestore Entry Point that
coreboot has been missing. Add the helper function that can call
into the blob to execute this.
BUG=b:69614064
Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The AGESA spec states that "Failure to release a structure can cause
undesired outcomes."
Uncomment the one in AmdInitLate(). The function only dealocates the
structure used for the AGESA entry point, and not the internal data
used by coreboot.
Release the structure in AmdInitEnv(). This appears to have been an
omission years ago when duplicating agesawrapper.c for every mainboard
was still common.
BUG=b:70671742
TEST=Build and boot Kahlee, inspect console log
Change-Id: Ib1ff94ec2acdc845c5e4b4ed7088061cfc0c55f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22888
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add functions that the wrapper will call to get and save the S3 data.
The wrapper requires two types of data saved:
* Non-volatile: Information that is the minimum required for bringing
the DRAM controller back online. This change uses the common
mrc_cache driver to manage the storage
* Volatile: May be stored in DRAM; information required to complete
the system restoration process.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Commit 07fe618 [chromeec: Add support for reading second battery info]
added a mutex as part of the ACPI code to determine battery statuses.
Windows is extremely picky about ACPI code, and attempting to acquire
a level 1 mutex without first having acquired a level 0 mutex causes
Windows to hang on boot. Since there's no reason to use a level 1
mutex here, change it to level 0.
Test: Boot Windows on device with ChromeEC without hanging
Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fine tune 14" BigDaddy USB#2 2.0 strength:
PERPORTPETXISET: 7
PERPORTTXISET: 1
IUSBTXEMPHASISEN: 3
PERPORTTXPEHALF: 0
this value could have USB#2 2.0 EA/function pass.
BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23649
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.
Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.
BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.
Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, we were seeing device boot into the recovery screen with
error code 0x5a. This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.
BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
the OS.
Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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