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2013-01-11Fix console.c with serial support disabledStefan Reinauer
During the ARM port, disabling serial console became broken. This patch fixes it. Change-Id: I40460596073918a08c19bb9c991cada341cca940 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2136 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11cbmem: replace pointer type by uint64_tStefan Reinauer
Since coreboot is compiled into 32bit code, and userspace might be 32 or 64bit, putting a pointer into the coreboot table is not viable. Instead, use a uint64_t, which is always big enough for a pointer, even if we decide to move to a 64bit coreboot at some point. Change-Id: Ic974cdcbc9b95126dd1e07125f3e9dce104545f5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2135 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11exynos5250: Hacked up lowlevel_init_cDavid Hendricks
This is the first lowlevel init routine that gets called in romstage. It's fugly and needs a lot of clean-up, but does the job for now. Change-Id: Id54bf4f1c3753bcbed5f6b5eeb4b48bc3b41ce93 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2133 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11exynos5250: Temporarily remove intermediate rule in MakefileDavid Hendricks
This cannot be used until we get the BL1 mess sorted out. Change-Id: I2490addb31256e27caa89ebb5b1501296e6903bd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-11AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITSZheng Bao
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-10armv7: replace magic constant for romstage locationDavid Hendricks
This replaces 0x02023400 with an SoC-specific Kconfig variable. Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: add *(.data) back into .romdata sectionDavid Hendricks
This doesn't seem to be strictly required (so far), but makes sense. Change-Id: I18416c427ff886507ae09c7fc1a018baf94af24a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2131 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: update board_init_f function signatureDavid Hendricks
We don't pass arguments when we jump out of assembly code. Change-Id: Iccf3a6f713e260b08f9ff47e8b542b9e96369166 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: delete some unused filesDavid Hendricks
Change-Id: I4601b97cbd7dbfb6ee742b3920d2aac4ac49b958 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2121 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-10snow: add max77686 driver in romstage and ramstageDavid Hendricks
Change-Id: Id3e20b1ab5d85cfd22e2dae2750f32007b7f8f74 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2123 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10exynos5250: clean-ups for clock_initDavid Hendricks
This does some clean-up for the exynos5250 clock_init.c: - No global data. - Remove some unused #includes - Hard-code the memory type for Elpida DRAM. This will need to be fixed eventually (or the system will be unstable), but is good enough for early bring-up and until we finish other re-factoring. Change-Id: Icd2cf8ba35058cbd1131666db311dfb77ef1a160 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2127 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10exynos5250: un-comment a lot of code which was left out earlierDavid Hendricks
Turns out initializing power rails is necessary, even for getting serial output. Change-Id: I3042c1001ae43b1e793ee6cb90bb79b8db0f8fd1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2126 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10size optimizations for max77686David Hendricks
This contains some size optimizations for the Maxim MAX77686 driver: - change max77686_para.vol_{min,div} from u32 to u16 (currently their max value is 50000 so it should be fine) - remove max77686_para.regnum which takes 4 bytes for each and is not used (Patch was originally written by Hung-Te Lin, I'm just uploading it) Change-Id: I24044427c49467e99380d1f60ebc59e69c285b22 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2124 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10Fix 2 infinite loops if IMC doesn't respondMartin Roth
ACPI code: The ACPI code is not currently being compiled in by default, but assuming that it will be at some point, I'm fixing the loop that waits for the IMC to respond after sending it a command. The loop now exits after 500ms, similar to the function in agesa. Agesa Code: a 16 bit variable will always be less than 100000. Change to be a 32 bit variable. Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-09Fix typo in SB800 Kconfig for IMC positionMartin Roth
The cimx/sb800 IMC Firmware location Kconfig option has a typo which would could set it to the wrong location. Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-08qemu-x86: Implement more featuresStefan Reinauer
This patch switches the Qemu target to use (pseudo) Cache As RAM and enables some ACPI code. This allows to use the CBMEM console and timestamp code with coreboot in Qemu. Right now, the ACPI code is commented out because leaving it in breaks IDE. Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2113 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-05ARMv7: drop __ASSEMBLY__Stefan Reinauer
We moved to using __ASSEMBLER__ years ago since it is set by as. Change-Id: I60103ba23ebe87be1d0bc63beed0ef5b05eed4f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2111 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-05ARMv7: drop __KERNEL__Stefan Reinauer
It's a bad Linux heritage.. We have no userland in firmware. Change-Id: Ib19e5ba713078ca37514571213d19f418417b964 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2108 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Flatten the treeRonald G. Minnich
It makes no sense to have directories with one file. Change-Id: I65ba93dda5e6a4bcc5a7cc049c1378ebf5d6abcd Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2105 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04Revert "armv7: pass bootblock offset from Kconfig into cbfstool"Ronald G. Minnich
This reverts commit ec8d35fe911ab35a5f40fd5b452f5463857b244a We are almost certain that this is not necessary. Change-Id: I70e94f883be95655da00a0b127ed9ffd7c81c63b Reviewed-on: http://review.coreboot.org/2104 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-01-04ARMv7: Make ABI compatible to reference toolchainStefan Reinauer
Our reference toolchain uses -mabi=aapcs whereas we started forcing -mabi=aapcs-linux. Drop this to prevent ABI incompatibility. Also drop -fno-common since that's set in the top level Makefile.inc already. Change-Id: I4afdcf5da9a5d86c2f9e5de5c7d523ccd2f5f1e0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2103 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04ARMv7: drop libgcc copyStefan Reinauer
We accidently checked in some files from libgcc as well as a Makefile from u-boot and a duplicate implementation of div0. Drop all those files to reduce the confusion. Change-Id: I8ff6eabbced6f663813f8cc55f19c81839d03477 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2102 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Clean up ARMv7 architecture KconfigStefan Reinauer
There was a misuse of bool that would cause the dcache policy to not be set up correctly, but instead present options "y" and "n" in the Kconfig menu. Also, TINY_BOOTBLOCK was removed a while ago, everything is TINY_BOOTBLOCK now. Hence remove the option. Change-Id: I5c28ac828955c69614c7bdaf106f79db51e68723 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2101 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Make PCIe config options depend on PCIe supportStefan Reinauer
Change-Id: I42452a044dc75e35876fcea1736481e538eed663 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2100 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04rd890: clear IO-APIC before setupAladyshev Konstantin
Add function "clear_ioapic" before "setup_ioapic" for RD890 northbridge like it is done for SB700 and SB800 chipsets ("amd/cimx/sb{7,8}00"). No functionality change is noticed. Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2045 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-04Tyan s8226: change lapic of lapic_cluster 0 to 0x10Siyuan Wang
There are two CPUs on s8226 and each CPU has 8 cores. CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27. So the first core's lapic is 0x10 rather than 0x20. Change-Id: I925114d44f2f4974eb62c3832d8c9139a2a06c96 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/2099 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Change "VERSION*" to more determined name "CBFS_HEADER_VERSION*".Hung-Te Lin
The 'VERSION' in CBFS header file is confusing and may conflict when being used in libpayload. Change-Id: I24cce0cd73540e38d96f222df0a65414b16f6260 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2098 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04cleanup some exynos5250 uart codeDavid Hendricks
This just cleans out some unused headers and tidies up the early serial code. TODO: Clean-up or replace FDT code, make "base_port" easier to configure. A bit of cleanup based on earlier patches. Change-Id: Ie77ee6d4935346e0053c09252055662f1a45d5f5 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2084 Tested-by: build bot (Jenkins)
2013-01-04make early serial console support more genericDavid Hendricks
This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. The UART code structure needs some rework, but the use of ROMCC, romstage, and then ramstage makes things complex. uart.h now includes all .h files for all uarts. All 2 of them. This is actually a simplifying change. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2086 Tested-by: build bot (Jenkins)
2013-01-04update CFLAGS for armv7David Hendricks
This updates $CFLAGS used for armv7. Most of them were just added to be consistent with what u-boot does. The important ones here are -march=armv7-a and -mthumb (to allow 16-bit Thumb instructions). I removed the hard float support because it got errors and coreboot should never use floats anyway. We're still having trouble with enums but I want to see how far it gets with this patch. Also, put the flags in a form that makes diffs easier to read. It's almost impossible otherwise. Finally, move some flags to the architecture Makefile, and rely on the fact that some are set for all architectures. Depends-On: I6f730d017391f9ec4401cdfd34931c869df10a9e Change-Id: Ia8a1ae22959933e06f7b996d1832cea40819f1ff Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2075 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03Rename mainboard_smi.c to smihandler.cPatrick Georgi
This mirrors the naming convention of handlers in northbridge and southbridge. Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2058 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03armv7: pass bootblock offset from Kconfig into cbfstoolDavid Hendricks
This replaces a somewhat useless calculation used earlier (which always evaluated to 0) with an offset to specify the location of the Coreboot bootblock. Change-Id: Ib85aaccf138cebeb6bf8aedf82308861206dff48 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2094 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03snow: Stuff to support building image with BL1David Hendricks
This patch does two things which will take effect in follow-up patches: 1. Add an intermediate Makefile rule for dd'ing BL1 into the coreboot.rom pre-image. This is modeled after a similar hack for the bd82x6x southbridge. 2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to pass the bootblock offset into cbfstool. Change-Id: I89da255dc903c387b754b06a11bb3439035ead87 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2093 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03Add (hacked-up) s3c24x0_i2c filesDavid Hendricks
These are needed for communicating with the PMIC on Snow. We'll tidy them up as we go along... Change-Id: I197f59927eae0ad66191862d052de2a8873fb22f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2078 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-03import SPL files for board_i2c_{claim,release}_bus()David Hendricks
This imports SPL (second phase loader) files from U-Boot. Most of the content of these files will eventually go away since they're fairly U-Boot specific. For now they are here to make Jenkins happy. Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2081 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-03armv7: create init.S for early ARMv7 initDavid Hendricks
The old start.S file did a lot of work and had AP-specific #ifndef's. The new init.S will eventually contain only bare minimum generic ARM code for use by the bootblock. Processor-specific stuff and things that take place later in the boot process should go elsewhere. Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2083 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03Fix strcpy()Stefan Reinauer
'nough said. It was broken since 2006. Change-Id: I312ac07eee65d6bb8567851dd38064c7f51b3bd2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2062 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-02AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functionsAladyshev Konstantin
Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE". This results in a failure of init late function: "agesawrapper_amdinitlate failed: 1" It happens because TRUE = 1 = AGESA_UNSUPPORTED. Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem. Only family f15tn does not have such bug. This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family? Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15). Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2070 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2013-01-02Supermicro H8QGI: Pass callout pointer to AmdReadEventLog functionAladyshev Konstantin
I have issues when AmdReadEventLog function tries to use BiosCallouts interface. So it is necessary to provide callout pointer to this function. Change-Id: I4080e5f07d5d28c41688b2a7deff944b7a0f7bf7 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2064 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2012-12-30rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_opsDenis 'GNUtoo' Carikli
That code will be used to disable the internal GFX card and enable the external PCIe card. The following lines from function `rs780_internal_gfx_enable()` are taken and reversed. /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); l_dword &= ~(1<<0); l_dword |= 1<<1; pci_write_config32(nb_dev, 0x8c, l_dword); It has been tested on the M4A785T-M with the following card inside the PCIe 16x slot: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2065 Tested-by: build bot (Jenkins)
2012-12-30M4A785T-M: Add support for external GFX.Denis 'GNUtoo' Carikli
This commit enables the external graphics card. In order to work, the internal graphic card has to be disabled, that is done in src/device/device.c through: vga_onboard->ops->disable(vga_onboard); which calls the RS780 disable operation introduced in the following commit: "rs780: add .disable pcie_ops" This commit was tested with and without the following card: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers): Dec 20 19:43:32 <Aladyshev> If you list your internal card in devicetree.cb, coreboot will distinguish external and internal VGA and choose external one Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/2067 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29Add AMD Hudson blobs by CONFIG_REQUIRES_BLOBS dependencyMarc Jones
If a 3rd party blob option is selected, make sure that it makes the user select CONFIG_USE_BLOBS as otherwise the build will fail. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc Reviewed-on: http://review.coreboot.org/2080 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29remove obsolete include paths from INCLUDESDavid Hendricks
Change-Id: I621fd49b1f1b96ef388c61ff1abc2130ad2163a5 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2082 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29import i2c header from u-bootDavid Hendricks
This just imports a header. We may wish to modify the i2c interface and/or unify it with the smbus interface we currently have. Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29corrections for MAX77686 config variableDavid Hendricks
Fix some minor discrepancies which prevented the MAX77676 from getting compiled in properly. Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2076 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29move iRAM config variable to exynos5250 KconfigDavid Hendricks
Since these don't seem very generic and depend on the BL1, let's move them to the CPU-specific Kconfig. Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2077 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29Simplify romstage.ld for armv7David Hendricks
This is still a work-in-progress, but it seems to work better than before and is less complicated... Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2041 Tested-by: build bot (Jenkins)
2012-12-28Supermicro H8QGI: Add onboard VGA to devicetree.cbAladyshev Konstantin
Supermicro H8QGI has integrated Matrox G200 16MB DDR2 graphics. List it in devicetree.cb to mark it as onboard VGA to coreboot. This change makes menuconfig option "Use onboard VGA as primary video device" work. Change-Id: Ia6b9f60e3ae705689f22babd544ad6e628a85df1 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2042 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28Supermicro H8QGI: fix bus_sp5100[] clear in get_bus_conf.cAladyshev Konstantin
Fix little mistake in get_bus_conf code Change-Id: I8c09e501082caa0a20266b007c0744630a356de0 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2046 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28BiosCallOuts: Replace REQUIRED_CALLOUTS define with flexible variableAladyshev Konstantin
Size of BiosCallouts[] struct can be calculated as: CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); There is no longer need for REQUIRED_CALLOUTS define. Originally that change was done for AMD Persimmon in commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 without deleting the define. This was ported to some of the other boards and for some the define was not removed. The AMD Inagua, Parmer and Thatcher boards were already adapted but the define was left in. So just remove it for those. Tested on Supermicro H8QGI. Change-Id: Ia09795579a1170fa20ab94a30feb1af6821153d2 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2049 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28USBDEBUG: Enable the EHCI in AMD SouthbridgeZheng Bao
Since SB800, USB2.0 debug port is dev 0x12, func 2. Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1880 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-21Supermicro H8QGI: Fix routing from 16 to 55 in ACPI tableAladyshev Konstantin
H8QGI board has 2 IO-APICS with 56 IRQ’s: IOAPIC[0]: GSI 0-23 - SB700 southbridge IOAPIC[1]: GSI 24-55 - RD890 northbridge `gDefaultApicDeviceInfoTable[]` structure in northbridge code vendorcode/amd/cimx/rd890/nbIoApic.c has IO-APIC interrupt mapping for HT and IOMMU set to last 31 IRQ pin (24+31=55). CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = { // Group Swizzling Port Int Pin {0, 0, 31}, //HT {0, 0, 31}, //IOMMU […] Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT. Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2047 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19Add back dummy free()Stefan Reinauer
GNU CC coverage needs free() and it's highly desirable to leave the code as genuine as possible. Change-Id: I4c821b9d211ef7a8e7168dc5e3116730693999c6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2051 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-19No need to contact AMD for firmware anymorePatrick Georgi
We ship it in the 3rdparty repository. Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2060 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-19Remove colors from build system outputPatrick Georgi
While "payload none" is undesirable for instant flashing, assume that it was a conscious user choice. (more immediate: jenkins isn't happy with escape sequences) Change-Id: I9958b34a037b4d10bb7dba893335a63917623a70 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2055 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19Get stdint.h in sync between ARMv7 and x86Stefan Reinauer
- add s8, s16, s32 types to x86 Change-Id: Ib9c260fc4f72029492f2d935dbb822cc3ff83cc4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2050 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-15Fix a compare against undefined variable in acpi.cMartin Roth
Initialize the pointer fadt to NULL to prevent a later comparison (if (fadt == NULL)) when the pointer had the *possibility* of never having been initialized. Change-Id: Ib2a544c190b609ab8c23147dc69dca5f4ac7f38c Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2037 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-12-14AMD S3: Rename generated s3.rom for make cleanZheng Bao
Add prefix coreboot_ to let make clean find it and delete it. Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2029 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-12SB800: Add IMC ROM and fan control.Martin Roth
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800 platforms. - Allows user to add the IMC rom to the build and to configure the location of the "signature" between the allowed positions. - Allows for no fan control, manual setup of SB800 Fan registers, or setup of the IMC fan configuration registers. - Register configuration is done through devicetree.cb. No files need to be added for new platform configuration. - Initial setup is for Persimmon, but may be extended to any cimx/sb800 platform. Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Rename generated hudson_romsig.bin for make cleanMartin Roth
The file generated when the IMC or XHCI binaries are included in the rom was named $(obj)/hudson_romsig.bin. The problem with this is that it doesn't get deleted when the user does a make clean. changing the name to coreboot_hudson_romsig.bin makes this happen. Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1978 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Fix SPI BAR special case in lpc_set_resourcesMartin Roth
There was already a special case for the SPI base address in lpc_set_resources for southbridge/amd/cimx/sb800 and southbridge/amd/agesa/hudson, but it needed to be modified to keep from killing the IMC rom during initialization. As soon as the BAR is disabled by setting the new base address, the IMC dies. The fix is to make sure it's still enabled when setting the new base address instead of setting the new address then re-enabling it. Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER to more accurately describe what we're using. Change-Id: I216d75b722c4332c239d487111a9880eabf59e91 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1975 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Claim the SPI bus before writes if the IMC ROM is presentMartin Roth
The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-12Fix ARMv7 payload handlingStefan Reinauer
cbfstool was called with the wrong parameters Change-Id: I405d0fd7c84b46da3c98a36fd19ef0034dc175cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2022 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Fix maxim max77686 driverStefan Reinauer
With driver-y going away, the current driver code didn't get compiled in with upstream. Change-Id: I9bff45a35c995888a482bdc22a1573f6bfb88211 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2027 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add support for Google Parrot ChromebookStefan Reinauer
AKA Acer C7 Chromebook See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html for more information. Thank you to Sage Electronic Engineering, LLC for making this possible! http://www.se-eng.com/ Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2026 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add support for ENE932 EC w/ Compal firmwareStefan Reinauer
Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2024 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add minimal mainboard support for snowRonald G. Minnich
This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2018 Tested-by: build bot (Jenkins)
2012-12-12Fix UART8250 console prototypesStefan Reinauer
and disable IO mapped UARTs on ARMV7 per default Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2021 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-12Fix up Maxim MAX77686 driverStefan Reinauer
... to fit into the naming convention Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2020 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-11Remove un-needed i2c.h includeRonald G. Minnich
When we need i2c for this cpu we will use the coreboot smbus code. Change-Id: I4ba4cc9ae10e5ca830d621ee9c8d9f7bd2129e2f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-11Correct the location of the include fileRonald G. Minnich
The max include file is in src/drivers/power. Change-Id: I2e663b472cade17fc50edbb449c0e54fd4a991eb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2017 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-10Removed an unneeded include fileRonald G. Minnich
This file builds fine without including arch/types.h Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Icd38cf429576a2a1a33ebca84389526feddfc169 Reviewed-on: http://review.coreboot.org/2015 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-08stddef.h: move to generic codeStefan Reinauer
stddef.h should be fairly generic across all platforms we'd want to support, so let's move it to generic code. Change-Id: I580c9c9b54f62fadd9ea97115933e16ea0b13ada Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2007 Tested-by: build bot (Jenkins)
2012-12-08WIP: Initial ARMv7 architecture implementation in corebootStefan Reinauer
The first ARMv7 CPU we're going to support is the Exynos 5250 used in the Google Snow ChromeBook. Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2004 Tested-by: build bot (Jenkins)
2012-12-08WIP: Add support for non-8250 built-in UARTsStefan Reinauer
Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08cbfs_core.h: support for ARMv7 CBFS master headerStefan Reinauer
Change-Id: I59626200b4a92d90b46625f8dcc2ed28e6376e46 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2008 Tested-by: build bot (Jenkins)
2012-12-08WIP: Initial support for Samsung Exynos 5250 ARM CPUStefan Reinauer
Samsung SoC files, including Exynos5 (a Cortex-A15 implementation). Since this is an SoC we'll forego the x86-style {north,south}bridge and cpu distinction. We may try to split some stuff out before the final version if prudent. Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2005 Tested-by: build bot (Jenkins)
2012-12-08Limit SPI device debug prints with CONFIG_DEBUG_SPI_FLASHMarc Jones
Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH, which would cause long delays durring boot when SPI devices were written. Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1965 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08Fix Yabel compilation on non-x86 platformsStefan Reinauer
Mostly preventing inb/outb being used on non-x86 Change-Id: I0434df4ce477c262337672867dc6ce398ff95279 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08Only include libgcc wrappers on x86Stefan Reinauer
ARM does not need them, and they're causing trouble Change-Id: I6c70a52c68fdcdbf211217d30c96e1c2877c7f90 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2009 Tested-by: build bot (Jenkins)
2012-12-08Allow PCI option rom execution only on systems with PCI supportStefan Reinauer
... on all other systems it will fail terribly ;-) Change-Id: I7f8d10b71b2dbc798b28aee7c36872685c793fd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2001 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-07Add function to map vendor/device to generic VBIOS IDsDave Frodin
Change-Id: I4d7c4ec2b91c97eacf96770c150c2b9a61309053 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-06Disable CMOS_POST and IO_POST on non-PC80 systemsStefan Reinauer
Because they use outb instructions, they are bound to fail on non-PC80 systems like ARM. Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1974 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2012-12-06Unify assembler function handlingStefan Reinauer
Instead of adding regparm(0) to each assembler function called by coreboot, add an asmlinkage macro (like the Linux kernel does) that can be different per architecture (and that is empty on ARM right now) Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1973 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06driver/spi: Add support of MX25L3235DZheng Bao
Tested on Thatcher. Change-Id: I648171ba0d03be1e984c182f6d0f082241e3f51c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06Drop ARCH_ARM in favor of ARCH_ARMV7Stefan Reinauer
The ARM architecture is really many architectures, and most of them need their own toolchain. After discussing with Ron and David, we decided that we're going to call the architecture of our ARM board armv7.. This patch cleans out the remainders of ARCH_ARM in the tree and moves on to consistent ARMv7 naming. As of now, we only support little endian ARMv7 CPUs. We can fix that for big endian if/when it comes our way. Change-Id: Id70c7ef615f600e4d09961d811e7ac974fce4811 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1968 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-05Conditionally include mc146818rtc in console.cDavid Hendricks
get_option() is used to get a config option (debug loglevel) from CMOS. However, not all machines have CMOS, so define a dummy inline function that will return an error code so the caller (console_init()) will use the default loglevel. Change-Id: I6adf371d79164178f40a83f7608289a6a7673357 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1962 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-01Drop TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I38ea2ed2be4d9240ec8cb6d5dc5b3cc578cdaefb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-01Add include files for samsung s5p-commonRonald G. Minnich
These are from u-boot but have been cleaned up somewhat to remove references to linux include files. Change-Id: I5fe3954a11d8c4aa792620ef5e1a5ee8932b8578 Signed-off-by: Hung-Ti Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1930 Tested-by: build bot (Jenkins)
2012-11-30Rename devices -> deviceStefan Reinauer
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Drop boot directoryStefan Reinauer
It only has two files, move them to src/lib Change-Id: I17943db4c455aa3a934db1cf56e56e89c009679f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1959 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-30src/lib/Makefile.inc: Add license headerStefan Reinauer
Change-Id: If8bce4ebde9101ac9087fcbd43adc0e08c26352d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/1957 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Make set_boot_successful depend on PC80_SYSTEMStefan Reinauer
Set_boot_successful depends on CMOS parts that non-PC80 platforms do not have. For now, make the current path depend on CONFIG_PC80_SYSTEM, and make the alternative empty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I68cf63367c8054d09a7a22303e7c04fb35ad0153 Reviewed-on: http://review.coreboot.org/1954 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Only compile PC80 drivers when CONFIG_PC80_SYSTEM is setStefan Reinauer
Change-Id: Iac2f3ebf68c9c1df296fc81d10ee97053a9d5469 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1956 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30build system: Treat cmos.default as text filePatrick Georgi
It's a more easily maintainable format than a 128 byte binary blob Change-Id: Ic9b9f53cd025b5f89a21971930fabf6592f95d67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1867 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Supermicro h8scm: add agesa version of supermicroSiyuan Wang
Supermicro h8scm has a C32 CPU socket, the details of this board is: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support family 15 CPU, so we update this mainboard with this patch. This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation. If you want to change the frequency of memory, please edit the macros "BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT" in src/mainboard/supermicro/h8scm/buildOpts.c Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1510 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30AMD SB800: Interrupt routine for PCI slots on PersimmonZheng Bao
Set the correct device number in the pcie interrupt routine in ACPI asl. The device number is decided by which address pin is connected to IDSEL. Table 3-1: IDSEL Generation Primary Address AD[15::11] Secondary Address AD[31::16] 0 0000 0000 0000 0000 0001 0 0001 0000 0000 0000 0010 0 0010 0000 0000 0000 0100 0 0011 0000 0000 0000 1000 0 0100 0000 0000 0001 0000 0 0101 0000 0000 0010 0000 0 0110 0000 0000 0100 0000 0 0111 0000 0000 1000 0000 0 1000 0000 0001 0000 0000 0 1001 0000 0010 0000 0000 0 1010 0000 0100 0000 0000 0 1011 0000 1000 0000 0000 0 1100 0001 0000 0000 0000 0 1101 0010 0000 0000 0000 0 1110 0100 0000 0000 0000 0 1111 1000 0000 0000 0000 1 xxxx 0000 0000 0000 0000 On persimmon, PCI slot 0's IDSEL is connected to AD19, so the device number is 3. Slot 1's IDSEL is connected to AD20, so the device number is 4. Change-Id: Ic0fb7ac1c87ec306bf314e4d2b8c2bdc9031081b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30Persimmon: Disable the unused PCI clocksDave Frodin
Change-Id: I4b735fe4e6441f99236e43b34695fdac95b8888a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1875 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30AMD S3: Leverage the public SPI routineZheng Bao
Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30Create a a new configuration variable for PCIRonald G. Minnich
Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
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