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2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20soc/apollolake: Include PCI _OSC methodHannah Williams
Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15110 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20ACPI S3: Cleanup RSDP referenceKyösti Mälkki
Variable name shadows parameter name used on other functions, and it can be local anyway after function removal. Change-Id: I3164b15b33d877fef139f48ab2091e60e3124c3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15240 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-20soc/intel/common: Add _OSC methodHannah Williams
Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
Instead of programming unsupported CAS use the highest supported value. Start at DDR3 maximum of CAS 18T. Increase error message verbosity level. Useful for overclocking. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Allows to run a DDR3-1600 DIMM at 933Mhz. Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15217 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Calculate the value from current DDR frequency. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20arch/x86/smbios: Add DRAM manufacturerPatrick Rudolph
Add Ramaxel DRAM manufacturer id. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The manufacturer name shows up in dmidecode. Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15183 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20include/device/dram/ddr3: Add additional frequenciesPatrick Rudolph
IvyBridge memory controller supports more frequencies than SandyBridge. Required for future patches. Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15182 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Simplify calculation of value. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15181 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
Set max_mem_clock_mhz in devicetree to 933Mhz. Allows to run the memory at up to DDR3-1866. The same frequency was allowed within the first vendor bios, but Lenovo than decided to limit it to DDR3-1333. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The RAM is now running at DDR3-1600 instead of DDR3-1333. This gives about 4% performance increase in glmark2 using the Intel GPU. Change-Id: If15be497402d84a2778f0434b6381a64eda832d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15158 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-20amd/fam_10h-fam_15h: allow building without microcode updatesArthur Heymans
CPU_MICROCODE_MULTIPLE_FILES relies on SUPPORT_CPU_MICROCODE_CBFS, which is not set if CPU_MICROCODE_CBFS_NONE is set. This makes selecting CPU_MICROCODE_MULTIPLE_FILES conditional. Change-Id: I0c28f99a1b868bbf90a6f048cce3bea4ff849f76 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15259 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-20amd/geode: Fix comment about ACPI S3Kyösti Mälkki
As RAMTOP gets removed, comment becomes inaccurate. Change-Id: Iaf25b88a4065d15c0c0682425b1d033e4a36590f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20VIA C7 NANO: Fix early MTRR settingKyösti Mälkki
It would not be possible to set MTRR for range 1MiB to 4MiB. Our RAMTOP is power of 2 and enabling cache for bottom 1MiB should cause no problems. Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-19intel/broadwell: Remove old USBDEBUG backup store in CARKyösti Mälkki
Required EHCI state is maintained as a CAR_GLOBAL to have it properly migrated. Change-Id: I8df413bec6faae4952670710c8ac804e0331c966 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15236 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-18emulation/qemu-i440fx qemu-q35: Asmlinkage for romstage main()Kyösti Mälkki
Change-Id: I66238525c5c4d97313a589373144741f1be97483 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15226 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-18intel: Fix romstage main() with asmlinkageKyösti Mälkki
Backport from haswell. Change-Id: I585639f8af47bd1d8c606789ca026c6d2d0cc785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18AMD boards: Fix romstage main() declarationKyösti Mälkki
Boards incorrectly used intel include file for AMD board. Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-18dmp/vortex86ex: Drop excessive includeKyösti Mälkki
Change-Id: Ieeae96d53627768de98006074c8c8e826b1741fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15233 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki
Reference to CACHE_AS_RAM was from the days we had romcc boards using socket_mPGA605. Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15224 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17google/reef: Update EMMC DLL setting in all modeZhao, Lijian
Update tuned DLL setting on all other mode, including SDR12 SDR25 and DDR50. Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/15210 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15197 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
This Kconfig is deprecated, new platforms need to locate ramstage stack in CBMEM instead. Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15189 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-16google/reef: Add NVRAM and LEGACY sections to chromeos.fmdFurquan Shaikh
Now that the flash size is increased to 16MiB, add RW_NVRAM and RW_LEGACY sections to chromeos.fmd file. BUG=chrome-os-partner:54390 Change-Id: I6c79d35295c4bc774f05f8045ac920474d7a791f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15192 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16google/reef: Update flash size to 16MiBFurquan Shaikh
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region accordingly. BUG=chrome-os-partner:54390 Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15191 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16mb/google: Remove whitespace from devicetree on bdw boxes.Prabal Saha
Change-Id: I189836282b4ad084fbbb74199b24505f5e141b60 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/15207 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins)
2016-06-16google/rikku: Upstream Acer Chromebox CXI2Matt DeVillier
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to upstream, using google/guado as a baseline. original source: branch firmware-rikku-6301.110.B commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F] TEST=built and booted Linux on rikku with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.bin) external reference code (refcode.elf) Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12802 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-15intel/apollolake: Correct the offsets in gnvsFurquan Shaikh
Offsets start from 0 instead of 1. Fix this in the gnvs definitions. BUG=chrome-os-partner:54342 Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15180 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-15intel/apollolake: Add CBMEM console to GNVSFurquan Shaikh
CBMEM console stores all the console logs in CBMEM. Address of this location in CBMEM where console logs are stored needs to be passed up to OS using GNVS. 1. Add CBMC to GNVS fields in globalnvs.asl 2. Add cbmc member to global_nvs_t structure in nvs.h 3. Initialize gnvs->cbmc to address of cbmem console BUG=chrome-os-partner:54342 Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15177 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-14drivers/intel/fsp2_0: Add FSP return types for resetAndrey Petrov
FSP methods may require reset under certain conditions. That is indicated by returning specific return code. Add the missing return status codes. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I460353c5f835548a98255bd3e11dbfd08260ea52 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15185 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-14Added CL7 supportElyes HAOUAS
according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf" Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) page 16 and page 60, CL7 support added Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/14976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-14google/reef: Correct use of globalnvs.aslFurquan Shaikh
Use the correct globalnvs.asl from apollolake. BUG=chrome-os-partner:54342 Change-Id: I1a5b8f61c540bdb2668b532f032350d8e4d48010 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-14google/reef: Update EMMC DLL settingsZhao, Lijian
Update EMMC DLL setting for reef board, after that system can boot up into EMMC successfully. BUG=chrome-os-partner:54228 TEST=Boot up into EMMC and check with Rootdev Change-Id: I614cd624dce9069c5565599a955f87906bcea53b Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/15156 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/quark: Add C bootblockLee Leahy
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. This is the first piece in supporting FSP 2.0. Move esraminit from romstage into the bootblock. Replace cache_as_ram with car_stage_entry.S and code in romstage.c TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12bootblock: Declare common bootblock_pre_c_entry routineLee Leahy
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC value as a uint64_t value. TEST=Build for amenia and Galileo Gen2 Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15124 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
2016-06-12soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()Aaron Durbin
If a bridge has the primary bus equal to the secondary bus the busmaster_disable_on_bus() will infinitely call itself. Avoid the inifinite recursion by checking current bus number against the secondary bus number. BUG=chrome-os-partner:54262 TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx signals which means no more infinite recursion. Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15157 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-12soc/intel/apollolake: save GNVS pointer to SMM handlerAaron Durbin
Like other boards there will likely be information needed from GNVS in the SMM handler. Therefore, it's important that the point is stashed accordingly. BUG=chrome-os-partner:54275 TEST=Noted GNVS messages from SMM console on reef. Change-Id: If12b69731330a1e0af7f8fe880635e5ffd02d715 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15152 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/apollolake: allow DEBUG_SMI to workAaron Durbin
The UART support is needed in SMM in order for DEBUG_SMI to function. BUG=chrome-os-partner:54262 TEST=Ran on reef with DEBUG_SMI enabled. Can observed SMI messages. Change-Id: Ibd6b12e27d5776046b400adf72f24133b9e54af8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15151 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/apollolake: provide fake PM1 SMI status bitAaron Durbin
It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12soc/intel/apollolake: add SMI status bit definitons and use themAaron Durbin
Provide the bit definitions for the SMI status register. Also, utilize them which means deleting some of the handlers that can't exist because there are no status bits. BUG=chrome-os-partner:54262 Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12riscv-spike: Replace custom UART with a memory-mapped 8250Jonathan Neuschäfer
Since the HTIF is a non-standard interface, and coreboot already has a 8250 driver, I started implementing an 8250 core for spike[1]. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15150 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12arch/riscv: Compile with -mcmodel=medanyJonathan Neuschäfer
In the default (medlow) code model, pointers are loaded with a lui, addi instruction sequence: lui a0, 0xNNNNN addi a0, a0, 0xNNN Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't load pointers just above 0x80000000, where RISC-V's RAM now lives. The medany code model gets around this restriction by loading pointers trough auipc and addi: auipc a0, 0xNNNNN addi a0, a0, 0xNNN This way, any pointer within the current pc ±2G can be loaded, which is by far sufficient for coreboot. Change-Id: I77350d9218a687284c1337d987765553cf915a22 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15148 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12arch/riscv: Add misc.c to bootblock/romstage to get udelay()Jonathan Neuschäfer
The uart8250mem driver needs it. Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12arch/riscv: copy read/write8/16/32 from x86Jonathan Neuschäfer
Change-Id: I12de8f82499074f0fbbc1c09210b00c6a9614c1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constantJonathan Neuschäfer
Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14962 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12intel/apollolake: Use custom reset callsFurquan Shaikh
Due to USB LDO issue in current steppings, cold reboot needs to be temporarily disabled. Thus, hard_reset call should be the same as soft_reset. Once future steppings are available INTEL_COMMON_RESET can be enabled again. Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15143 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
Remove code duplication and use the common function store_current_mrc_cache instead. No functionality is changed. Tested on Sandybridge Lenovo T520. Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15074 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-12rockchip: rk3399: pass board specific message to BL31Lin Huang
Sometimes we need to pass board specific messages to BL31, so that BL31 can do board specific operation based on common code. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I096878699c6e6933debdf2fb3423734f538691ae Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: af83e1b Original-Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349700 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15116 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12mt8173: dram: Add more sample points to improve dram timing marginPH Hsu
BRANCH=none BUG=chrome-os-partner:52959 TEST=verified on elm-EVT SKU1/SKU2, Oak-rev5 2GB/4GB models. Change-Id: I228c629d9a3d6cd8fc5c4e8ba24cc52d5283b4e6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3c19e7d Original-Change-Id: I22356aa8d196c4c126742cfc7e85cc693acd9b39 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347716 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12oak: Select VBOOT_EC_SLOW_UPDATE Kconfig optionJulius Werner
All current Oak boards have PD chips with update speeds that range from slow (Oak) to "OMG it's so awfully slow I could make a cup of coffee and it would still not be done" (Elm). Set the flag that enables the "Your system is applying a critical update. Please don't turn it off." message on EC software sync so that our users don't accidentally carry it back to the store and demand a refund while it's still not done booting. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak in normal mode with a new EC-RW image. Confirmed that I saw the magic screen. Change-Id: I000eab36d26b61b25d1f0da505f02ced15457255 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 274644b Original-Change-Id: I64ba698985d5fbcf2b94115df72b70a5319106ac Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348787 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15114 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devicesJulius Werner
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the board can skip display initialization in the normal boot path. It's name is a left-over from a time when this could only happen by avoiding loading the VGA option ROM on x86 devices. Now we have other boards that can skip their native display initialization paths too, and the effect to vboot is the same. (Really, we should rename oprom_matters and oprom_loaded to display_skippable and display_initialized or something, but I don't think that's worth the amount of repositories this would need to touch.) The only effect this still has in today's vboot is to reboot and explicitly request display initialization for EC software sync on VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still, the vboot flag just declares the capability (for skipping display init), and it should be set correctly regardless of whether that actually makes a difference on a given platform (right now). This patch updates all boards/SoCs that have a conditional path based on display_init_required() accordingly. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak, confirmed that there's no notable boot time impact. Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c242f7 Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348786 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12rockchip: gru: Add USB DRD DWC3 controller supportLiangfeng Wu
This patch adds code to initialize the two DWC3 USB host controllers, and uses them to initialize USB3.0 on the gru rk3399 board. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB3.0 on gru/kevin rk3399 platform Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0306a9e Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8 Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347524 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15112 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11arch/x86: Support "weak" BIST and timestamp save routinesLee Leahy
Not all x86 architectures support the mm register set. The default routine that saves BIST in mm0 and a "weak" routine that saves the TSC value in mm2:mm1. Select the Kconfig value BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to save the BIST and timestamp values. TEST=Build and run on Amenia and Galileo Gen2. Change-Id: I8119e74664ac3522c011767d424d441cd62545ce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15126 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11mainboard/intel/galileo: Support bootblock in CLee Leahy
Initialize the GPIOs during the boot block to properly route the SOC UART pins. TEST=Build and run on Galileo Gen2 Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15133 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloops in assembly_entry.SLee Leahy
Use Kconfig values to enable debug spinloops in assembly_entry.S. This makes it easy to debug the assembly code. TEST=Build and run on Galileo Gen2 Change-Id: Ic56bf2260b8e3181403623961874c9289f3ca945 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloopLee Leahy
Conditionally add a debug spinloop to enable easy connection of JTAG debuggers. TEST=Build and run on Galileo Gen2 with a JTAG debugger. Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15127 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-10Revert "soc/intel/apollolake: Do not use StackBase FSP-M parameter"Brandon Breitenstein
This reverts commit 5ede3d8ccebde6f26c6b24f6458e57d99d5f3957. No longer needed due to FSP being updated, with the 139_40 release, to accept StackBase field BUG=chrome-os-partner:52784 BRANCH=none TEST=built and booted with FSP 139_40 Change-Id: Ic832d8dc4ca87631f5fef80d4d41558d9a72630a Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-10soc/intel/apollolake: FSP Header file update for FSP 139_40Brandon Breitenstein
FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs with the 139_40 release. In order to successfully pass through memory/silicon init the header files must be updated to the latest versions BUG=chrome-os-partner:52784 BRANCH=none TEST=built and booted Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15066 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09util/checklist: Add bootblock supportLee Leahy
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK selected. TEST=Build and run with Galileo Gen2 Change-Id: I922f761c31e95efde0975d8572c47084b91b2879 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15130 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09vendorcode/intel/fsp1_1/checklist: romstage - Add car_stage_entryLee Leahy
Add car_stage_entry as an optional routine in the checklist. TEST=Build and run on Galileo Gen2 Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09mainboard: Support ROM_SIZE > 16 MiBLee Leahy
Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size limitation of 16 MiB by specifying 16 MiB as the ROM size. TEST=Build and run on neoncity Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15108 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09soc/intel/apollolake: Update FSP header filesBora Guvendik
Update autogenerated FSP 2.0 generic header files based on FSP release 136_30. Changes were made to avoid duplicating some of the structs for every SoC. BUG=chrome-os-partner:50765 TEST=Build coreboot Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7145 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7584 Reviewed-on: https://review.coreboot.org/15081 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09intel/amenia: Program EMMC dll settingZhao, Lijian
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15092 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09soc/intel/apollolake: Add EMMC DLL APIZhao, Lijian
Starting from 136_30,FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 Reviewed-on: https://review.coreboot.org/15084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09skylake: Support common LPSS I2C driverDuncan Laurie
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers that are present on the Skylake-LP PCH with a 120 mHz clock. The required lpss_i2c_base_address() method is implemented separately for verstage/romstage and ramstage environments. This provides methods to convert to and from "struct device" and the I2C controller bus number for that device. These are used to provide support for the "I2C Bus Operations" that are present in the coreboot devicetree. To support the I2C controller before ramstage an early init function is provided to do minimal initializaiton of the PCI device and assign a temporary base address for use before memory. The final base address is assigned during device enumeration and used during ramstage. Because it is usually not necessary to enable I2C controllers before ramstage a config register for the devicetree is provided to perform early initialization of this controller. In addition the bus speed can be set in the devicetree and that speed will be applied when the device is initialized. If not provided the default speed is set to I2C_SPEED_FAST. This was tested with the google/chell mainboard by reading and writing from the trackpad and codec devices during both verstage and ramstage. Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15105 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09lib: Build reg_script for bootblockLee Leahy
Allow reg_script to be used during the bootblock. TEST=Build and run on Galileo Gen2 Change-Id: I55fe0be3f50116927b801ce67a3f23bb1931f6e7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15131 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09arch/x86: Enable SSE in bootblock_crt0.SLee Leahy
Don't write reserved bits in the Quark platform. Follow the previous boot behavior and just enable SSE. TEST=Build and run on Galileo Gen2 Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09lib: Add asmlinkage attribute to bootblock_main_with_timestampLee Leahy
Add asmlinkage to bootblock_main_with_timestamp so that it may be called directly from the assembly code. TEST=Build for Amenia and Galileo Gen2 Change-Id: Iefb8e5c1ddce2ec495b9272966b595d5adcebc1c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15125 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09skylake: Move I2C bus configuration to separate structureDuncan Laurie
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09skylake: gpio: Add support for setting 1.8V tolerantDuncan Laurie
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses that are at 1.8V. This is currently done by passing in a value to FSP but it is needed earlier than FSP if the I2C bus is used in verstage. This does not remove the need for the FSP input parameter, that is still required so FSP doesn't disable what has been set in coreboot. The mainboards that are affected are updated in this commit. This was tested by exercising I2C transactions to the 1.8V codec while in verstage on the google/chell mainboard. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c Reviewed-on: https://review.coreboot.org/15103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09skylake: Add function to set PRR for protecting flashDuncan Laurie
Add a function similar to broadwell to set the PRR for a region of flash and protect it from writes. This is used to secure the MRC cache region if the SPI is write protected. BUG=chrome-os-partner:54003 BRANCH=glados TEST=boot on chell, verify PRR register is set and that the MRC cache region cannot be written if the SPI is write protected. Change-Id: I925ec9ce186f7adac327bca9c96255325b7f54ec Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Id: abb6f645f5ceef3f52bb7afd2632212ea916ff8d Original-Change-Id: I2f90556a217b35b7c93645e41a1fcfe8070c53da Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349274 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/15102 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09soc/intel/common: Add LPSS I2C driverDuncan Laurie
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15101 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09device: i2c: Add support for I2C bus operationsDuncan Laurie
In order to support doing bus operations on an I2C device that is described in the devicetree there needs to be some linkage of the device and the existing opaque I2C controller bus number. This is provided in a similar fashion to the existing SMBUS operations but modified to fit within the existing I2C infrastructure. Variants of the existing I2C helper functions are provided that will obtain the bus number that corresponds to this device by looking for the SOC-provided I2C bus operation structure to provide a function that will make that translation. For example an SOC using a PCI I2C controller at 0:15.0 could use: soc/intel/.../i2c.c: static int i2c_dev_to_bus(struct device *dev) { if (dev->path.pci.devfn == PCI_DEVFN(0x15, 0)) return 0; return -1; } static struct i2c_bus_operation i2c_bus_ops = { .dev_to_bus = &i2c_dev_to_bus } static struct device_operations i2c_dev_ops = { .ops_i2c_bus = &i2c_bus_ops ... } With an I2C device on that bus at address 0x1a described in the tree: devicetree.cb: device pci 15.0 on # I2C0 chip drivers/i2c/sample device i2c 1a.0 on end end end That driver can then do I2C transactions with the device object without needing to know that the SOC-specific bus number that this I2C device lives on is "0". For example it could read a version value from register address 0 with a byte transaction: drivers/i2c/sample/sample.c: static void i2c_sample_enable(struct device *dev) { uint8_t ver; if (!i2c_dev_readb(dev, 0x00, &ver)) printk(BIOS_INFO, "I2C %s version 0x02x\n", dev_path(dev), ver); } Change-Id: I6c41c8e0d10caabe01cc41da96382074de40e91e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15100 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09soc/intel/quark: Pass serial port address to FSPLee Leahy
Pass the serial port address to FSP using a UPD value in the MemoryInit API. TEST=Build and run on Galileo Gen2 Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15079 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08rockchip: rk3399: Add support i2sXing Zheng
This patch enable and configure the clocks and IOMUX for i2s audio path, and the i2s0 clock is from CPLL. Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155 for the i2s clock div and gate setting. BRANCH=none BUG=chrome-os-partner:52172 TEST=boot kevin rev1, press ctrl+u and hear the beep voice. Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c58fa7 Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68 Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347526 Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: enable EC SPI interfaceVadim Bendebury
This configures and enables SPI interface #5 used for EC communications on Gru/Kevin. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the appropriate depthcharge change it is possible to trigger booting Chrome OS from the SD card by pressing '^U' on Gru keyboard at the right time. Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: b5cc177 Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346632 Reviewed-on: https://review.coreboot.org/15032 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: configure board GPIOsVadim Bendebury
Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later. Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346631 Reviewed-on: https://review.coreboot.org/15031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08veyron: Add exception_init() to romstageJulius Werner
I'm not even sure how this slipped through... looks like it had never been there in the first place. Anyway, on ARM exceptions should always be reinitialized in all stages to make sure the handlers are still around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one). Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08rk3399: add ability to configure SPI5Vadim Bendebury
This defines mux settings for the GPIO bank responsible for SPI interface #5. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate with the EC on gru: pressing Ctrl-U during boot allows to start Chrome OS from the SD card. Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4f92452 Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346630 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/15030 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c587880 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/15029 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h headerAlexandru Gagniuc
Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08soc/apollolake: Add SOC specific c-state tableHannah Williams
Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08soc/intel/common: Add common code for acpi c/p/t-state entriesHannah Williams
Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08mainboard/intel/amenia: Enable VIRT_DEV_SWITCHRavi Sarawadi
Enable virtual dev switch config. BUG=None TEST= On Dev FW screen, press SPACE key to boot to normal mode Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/15080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08Intel/amenia: Make the device address more readableZhao, Lijian
Use central header file to include device address and interrupt line to avoid confusion. Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7248 Tested-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7580 Reviewed-by: N, Harshapriya <harshapriya.n@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08adi/rc-dff: Add Initial implementaionChris Ching
* Add ADI vendor Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes, only string and ifdef names changed. Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/14778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08mainboard/lenovo/x220: Clean up codeJan Tatje
thermal.h still has references to X230 in include guard since it seems to have been copied from that port. Code formatting changes in romstage.c. Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56 signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/15071 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-08mainboard/google/reef: Configure sd card pinsJagadish Krishnamoorthy
Since the sd card cmd, data, cd lines are configured as native mode, allow the native controller to control the termination. Configure SDCARD_CLK_FB which is used for calibrating the timing of the actual clock buffer. BUG==chrome-os-partner:53747 TEST=verify sd card detection Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/348377 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15096 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-08lenovo/x60: add hda_verb.cArthur Heymans
This creates a config for the x60 audio based on values taken from vendor bios. The pin config is stored in (for linux 4.5 at least): /sys/class/sound/card0/hw*/init_pin_configs In the left column there is the pin number. In the right column there is the default configuration of that pin. (This has to be done while running the proprietary bios) More information on the sound card can be found in: /proc/asound/card0/codec#* This also hold the information of /sys/class/sound/ What is improved: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Before this had to be done manually in alsa or pulseaudio. TEST= check if internal microphone is used by default in pavucontrol if you are using pulseaudio. Plug in a jack with headphones and check if there is sound output through these and not the build-in speaker. Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15063 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-07intel/amenia: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14987 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07google/reef: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15069 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07Kevin/Gru : Update Board ID table.jongpil19.jung
Add board id table as kevin/gru configuration. BUG=chrome-os-partner:53519 BRANCH=chromeos-2016.02 TEST=check boot on Kevin board. Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43 Original-Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345736 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15028 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07soc/intel/apollolake: Add missing DRAM density constantsAndrey Petrov
Add missing constants for DRAM density. This resolves boot issue, because misconfigured density results in incorrect memory mapping. Change-Id: I3bad911bf406bfc5677059490d0e89fcbf735b70 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15059 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-06-07rockchip: gru: update the hynix lpddr3 config to run at 928MHzShunqian Zheng
Update the DDR config and DRAM driver to allow running at up to 928MHz. Kevin config/clock rate are not being changed, but Gru now runs at 928 MHz. BRANCH=none BUG=chrome-os-partner:51537 TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru, Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9 Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/343984 Original-Reviewed-by: Stephen Barber <smbarber@chromium.org> Reviewed-on: https://review.coreboot.org/15027 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-06rk3288: Remove duplicate timestamp_init()Julius Werner
Fix bug introduced by merging http://review.coreboot.org/9606 and http://review.coreboot.org/10740 in the wrong order. Change-Id: I75dd22cd0cf30c7d91e4fa5171cb482a80eb64ca Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-06intel/skylake: Fix typo in commentPaul Menzel
Correct the spelling of *firmware* in a comment. Change-Id: I44bcd95f754ff839d582dc2150e1883a6315da9e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-05pcengines/apu1: Add SMBIOS SKU fieldKyösti Mälkki
Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14997 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 19:08:34 +0000