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2019-11-27google/fizz: add libgfxinit supportMatt DeVillier
Change-Id: Idd7bfa4a97770f525c3f25f04f90c4bf092e4ae1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27google/glados: add libgfxinit supportMatt DeVillier
Both linear framebuffer and vga text mode verified on chell and caroline variants Change-Id: I106e7bb761055581634176a112816be8447e6745 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27AGESA,binaryPI: Remove early_all_cores()Kyösti Mälkki
This was implemented to make sure it gets called before attempting any PCI MMIO access. Now that we have one central romstage_main() implementation this extra precaution is no longer useful. Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27binaryPI: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
The remaining (active) binaryPI boards moved away from BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now. As the cache_as_ram.S is also used with AGESA, this slightly reduces the codesize there for romstage and postcar as well. This commit is actually a revert for the vendorcode parts, AMD originally shipped the codes using 'invd' for the CAR teardown, but these were changed for coreboot due the convoluted teardown that used to happen with non-empty stack. Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27binaryPI: Drop S3_DATA_POS and S3_DATA_SIZEKyösti Mälkki
Direct SPI flash manipulation is forbidden, need to go through respective FMAP and rdev APIs. Change-Id: I765a6084fb26398008f38c0403f808bae19fdae1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37192 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27binaryPI: Disable boards from buildKyösti Mälkki
As per the 4.11 release requirement, CAR_GLOBAL_MIGRATION=n is a mandatory feature, which most binaryPI boards lack as they use BINARYPI_LEGACY_WRAPPER. Disable all binaryPI platforms, except pcengines/apu2, from the build for the time being. If a platform does not reach POSTCAR_STAGE=y and C_ENVIRONMENT_BOOTBLOCK=y within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: Id81ab0f168034187ecf62203b5a33ac6ba49a35d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27pcengines/apu2: Switch away from BINARYPI_LEGACY_WRAPPERKrystian Hebel
Adopting the mainboard code to use hooks from state_machine.h. No post codes are changed, except for those which were explicitly sent in mainboard/romstage.c. Boot time is reduced by more than 7%, from 5.029s to 4.657s (coreboot timestamps, measured for loglevel 7). POSTCAR_STAGE is required since coreboot 4.11 release. TEST=boot PC Engines apu2 and launch Debian Linux with 4.14.50 kernel Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-27amdfam10: Clean leftover prototypesKyösti Mälkki
Change-Id: Ic3278cb1148c34284aba59f6f588713b683ca90b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-26soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-TSubrata Banik
It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26amd/pi/00730F01: Add support without BINARYPI_LEGACY_WRAPPERKrystian Hebel
A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. TEST=boot PC Engines apu2 with POSTCAR_STAGE patch Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32421 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26soc/intel/cannonlake: Add chip config to override CPU flex ratioSubrata Banik
This patch provides options to override descriptor default CPU flex ratio from coreboot code. cpu_ratio_override to provide the required CPU ratio. Note: Don't override the flex ratio if cpu_ratio is 0. BUG=b:142264107 TEST=Without override flex_ratio is 0 and verified booting to OS after overriding with flex_ratio value 5. Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-26soc/mediatek/mt8183: disable BBLPM of DCXO coreWeiyi Lu
When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM). Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided and crystal voltage will drop from 1.8V to 0.7V or lower. In order to ensure the stability by always outputting an accuarate system clock when system is running. We should disable BBLPM when only XO_SOC enabled. BRANCH=kukui TEST=accurate 26MHz provided and correct crystal voltage swing Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37136 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26southbridge/intel/common/spi.c: Define __SIMPLE_DEVICE__Arthur Heymans
This simplifies PCI config space accessors. Change-Id: Idf0f90ee2dc1dcb0003ef5d56eff44ca9a5634e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-26sb/intel/common/spi: Add Baytrail/Braswell supportArthur Heymans
The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-26security/vboot: Remove duplicate offsetof() definitionJacob Garber
This macro is already defined in commonlib/helpers.h Change-Id: I1fce2936757b13807e254f4a844f583b938bf349 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Alex James <theracermaster@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-26soc/nvidia/tegra: Remove duplicate macrosJacob Garber
These macros are already defined in stdbool.h or commonlib/helpers.h Change-Id: I6e474fc233d3134c89c29840471797b1e0c9e3c3 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-26arch/x86: SMBIOS: Improve core count reportingAndrey Petrov
Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-26soc/amd/exit_car.S: Drop redundant enabling cacheArthur Heymans
This is already done in arch/x86/exit_car.S Change-Id: Ie954aa11d5e76aaa3e2185ba552aafe8d075feb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-26nb/intel/sandybridge: Fix mrc.bin pathArthur Heymans
The mrc.bin uses a lot of stack. The BSP stack size is kept the same for both romstage bootpaths, mrc.bin and native, in order for the CAR symbol/setups to be compatible. Change-Id: Ic422980ca1a0549b6937e30a433ce52e0d7a595c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37185 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25mb/samsung: remove header guards for SuperIOMatt DeVillier
SuperIO header needs to be included regardless of Kconfig option, otherwise compilation fails due to missing prototype for try_enabling_LPC47N207_uart() if DRIVERS_UART_8250IO is not set. Change-Id: I0eda4aee2cbb114bde33e862940a64675469693d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-25binaryPI: Remove FieldAccessors.[ch]Kyösti Mälkki
SAGE brought these in outside AGESA specifications and they had some ill semantics. They were already removed from StoneyRidge. Change-Id: I59d0c450583b2ff58031c127aae881d1f3799338 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-25soc/intel/tigerlake: Add Jasperlake soc KconfigMaulik V Vaghela
Add Kconfig option for Jasperlake soc and make tigerlake as a base soc. This will allow us to differentiate between soc features. Change-Id: Id5001dc498a7d7d5c7903dc3a3762da740fc9c8e Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2019-11-25hatch: Enable EC sync in romstageTim Wawrzynczak
Now that the EC software sync in romstage ("early EC sync") patches have landed, it's time to enable this for Hatch. BUG=none BRANCH=hatch TEST=verify EC sync runs in romstage Change-Id: Ie567ab081b95b2302b051812fbf46e183c76bab6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37025 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25binaryPI: Use Kconfig to define the number of IOAPICsMichał Żygowski
Define the number of IOAPICs in a Kconfig to get rid of AmdGetValue calls being not conformant to AGESA API. Change-Id: I532597dd326093455358a23aef3b3ea0d0a14f75 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-25cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
Console is not yet enabled in bootblock. This will be done in a different CL. Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-25mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCKArthur Heymans
This feature and therefore the boards using it, will be deprecated soon. Change-Id: I1e970dd0613702346b5764d2b56012a72ed62cde Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37155 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-25Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans
Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-25soc/intel/broadwell: Fix 'dead increment'Elyes HAOUAS
Dead increment spotted out using clang-tools. Change-Id: Icfab0b9ce97722fe97a0306cb45fbc2bd072bad6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-25mb/google/octopus: disable fmap cache for all octopus devicesPatrick Georgi
Meep was just the first one to fail, but the others aren't any better. Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37163 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25sb/intel/i82801ix: Update comment on default decoded IO rangesArthur Heymans
Now the comment matches what is programmed into LPC_EN. Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36995 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-23AGESA,binaryPI: Move SCI enable outside table creationKyösti Mälkki
Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: I37810771090dd9b0377f9a72c7a17ef1564ccf68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36812 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23soc/amd: Move SCI enable outside table creationKyösti Mälkki
Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: Id7f79fc959766813d60f847482567579a02db124 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-23vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bssKrystian Hebel
This fixes issue that became visible after implementing post-CAR stage on top of `340e4b80904f lib/cbmem_top: Add a common cbmem_top implementation`. Compilation error was: Forbidden global variables in romstage: ffffff00 d top.2205 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/36976 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23mb/google/kahlee/treeya: Set touchpad hold time to 400nsPeichao Wang
According to SI team request, need to tune I2C bus 2 data hold time more than 300ns BUG=b:144736027 TEST=build firmware and measure I2C bus 2 data hold time Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Idc58a595c77eba8544f27682a284be6aac5dbe25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36945 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22src/console: Bring back support for printf'ing 64bit intsPatrick Georgi
commit f96d9051c2 (Remove MIPS Architecture) accidentally enabled a MIPS special case to not support 64bit integers in printf for all platforms. This removes that MIPS-only special case entirely. Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22sb/intel/ibexpeak: Decode more LPC IO rangesArthur Heymans
3b452e0 "nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak" introduced a regression where the GAME_L decode range was not set up, which is used by the WACOM digitizer on the Thinkpad X201T. Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36994 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22cpu/intel/gen1/smmrelocate: Fix stale commentArthur Heymans
Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-22cpu/intel/smm: Drop em64t save stateArthur Heymans
This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 0x17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22sb/i82801ix: Use macros instead of hard-coded IDsFelix Singer
This patch replaces hard-coded PCI IDs with macros from pci_ids.h and cleans up some code. Change-Id: Ie6ea72ac49eb015ef5cbaa98ed2b3400072000b5 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22soc/intel/icelake: Make CpuMpPpi implementation default for ICLSubrata Banik
TEST=Could able to build and boot ICL DE system Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-22drivers/ipmi: Add IPMI get system GUID supportJohnny Lin
Tested on OCP Mono Lake. Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-22soc/intel/common/intelblocks: Define PAD_CFG0_MODE_NF7Nick Vaccaro
BUG=b:142961277 BRANCH=none TEST=none Change-Id: Ibe0991b2e0d13e07d65906201597f9021cfc7156 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-22cpu/x86/smm: Use PRIxPTR to print uintptr_tJacob Garber
Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This fixes a compilation error when targeting x86_64 or using Clang 9.0.0. Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-22device/hypertransport: Drop unused codeArthur Heymans
Change-Id: I6a8b176fa6f8832f6f7bb37118861d530fdefd5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37066 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/t410: Fix I2C SPD addressPatrick Rudolph
Use correct address for second DIMM. Tested on Lenovo T410: * Both DIMMs are found and are usable Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOsShelley Chen
Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding explicit configuration for Kohaku in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=None ./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22src/drivers/ipmi: Implement BMC Get Self Test Result functionMorgan Jang
According to IPMI SPEC, it is recommended that BIOS includes provisions for checking and reporting on the basic health of BMC by executing the Get Self Test Results command and checking the result. TEST=Check the result in response data to confirm the BMC status is fine or not. Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-22purism/librem_skl: add/use VBT fileMatt DeVillier
Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v2/3/4,15v3/4 boards, verify functional display after resume from S3 when using libgfxinit. Change-Id: I6bc5dab60e3601d56dae4300efee255d7c58329d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37068 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/{x201,x60}/smihandler: Use mdelay instead of udelay for large valuesPeter Lemenkov
Change-Id: I7d20a850f8c2a1fcdee358c9e73d4c04eb3d7de8 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37006 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22arch/acpigen.h: Correct PARENT_PREFIX encoding valueElyes HAOUAS
The encoding value for PARENT_PREFIX is 0x5e. (ACPI specification version 6.3 page 1073) Change-Id: Ibbacb8b445157b377772f09572f87f8300a278dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36652 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22Makefiles: Remove -D__PRE_RAM__Kyösti Mälkki
All cases of testing for __PRE_RAM__ have been converted to equivalent ENV_xxx definitions from <rules.h>. Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22soc/intel/skylake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot soraka. Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-22arch/x86: Remove spinlocks inside CARKyösti Mälkki
This was only used with amdfam10h-15h, where cache coherency between nodes was supposed to be guaranteed with this code. We could want a cleaner and more generic approach for this, possibly utilising .data sections. Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22drivers/pc80/rtc: Remove CMOS spinlockKyösti Mälkki
This was only used with amdfam10h-15h, and only in romstage while commentary elsewhere says concurrent CMOS and CBFS access caused issues. We would want a cleaner approach on this, if re-implemented. Change-Id: I8512196cb55ff2b4542b1421a1bbae540450115a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22cpu/amd/microcode: Remove microcode update routineKyösti Mälkki
This was only used with native amdfam10h-15h. Change-Id: Id8e06b25c6ec716c07aee46fce10903c62b6d684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-21device/pci: Reduce scope of dev_find_slot()Kyösti Mälkki
We only keep it around because soc/intel debugging still depends on it. Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-21arch/x86: Remove copy_and_run()Kyösti Mälkki
Nothing but a wrapper for run_ramstage() with an ugly name. Change-Id: Ie443a27cf18f829496ddadcc19c4ebec6a0b5a59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21drivers/crb: Replace __RAMSTAGE_ guardsKyösti Mälkki
Change-Id: Ie2e6cdddc1edb95c442a4240267fe1fd6a11d37e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36698 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21drivers/pc80/tpm: Replace __RAMSTAGE_ guardsKyösti Mälkki
Change-Id: Ia6e161c3b4fc44292cdac692a2918c522680d60d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36631 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21cpu/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21cpu/x86/lapic/lapic_cpu_init.c: Drop unused guardsArthur Heymans
Both model_2065x and model_206ax use the parallel mp init codepath. Change-Id: I6440d413761361ee8b69d5c76b69409bd7528b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37065 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21Kconfig: Remove not found sourcesElyes HAOUAS
Change-Id: I3691a4162eecbd48321348e136f72b73da74e225 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21drivers/intel/fsp1_0: Drop supportArthur Heymans
No platform is using this. Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21soc/intel/fsp_broadwell_de: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21mb/*/*: Remove BROADWELL_DE boardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21soc/intel/fsp_baytrail: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-21mb/*/*: Drop FSP_BAYTRAIL supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21nb/sb/cpu: Drop Intel Rangeley supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-21mb/*/*: Drop Intel Rangeley mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id38eada2d08426520261d4824990a49f8302976b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-20device: Add back dummy HT_CHAIN_UNITID_BASEKyösti Mälkki
This should be defined by mainboard. Add a dummy default to fix master while HyperTransport files are still around referencing this. Change-Id: I58188a200a2cad5fa20affee1844117ba71ac338 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37036 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20nb/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-20sb/nvidia/mcp55: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/nvidia/ck804: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I56cb6d0a04056b10af1e53afb697883329235c87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36972 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/broadcom/bcm21000: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I5e9250a7c7adb7dffd64422637ba760155d966d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36971 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/broadcom/bcm5785: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I2305e0d9de0d4b1768e171f4c65d07306e7c3801 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-20sb/amd/sr5650: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I63551b9ad861fecb689036c9f26c3b0950a8b8e9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36969 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/sb800: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/*/*: Use proper header for pm_iowrite()Arthur Heymans
These boards don't include any from sb/amd/sb800. Change-Id: I2dbe39df6e4c5a86a0714b396bb89b03bbafd164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36987 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/sb700: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/rs780: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I00d260f22badb712a963b907f7beb8fbb5b71eac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36966 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/amd8132: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I83d7025280b75088c37049f34564610612996e1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36965 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/amd8111: Remove supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I5d7f3bfca47b86e4fd761f9462bc7297b487fdee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36964 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/*/*: Drop AMDFAM10 mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/via/common: Drop unused codeArthur Heymans
Change-Id: I803b9bba4067435e471e9565d3286f11a0a361a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36960 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20nb/via/vx900: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ie971893da06fd3b1ac41dda398b1caeec3ee32db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20cpu/via/nano: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I6d9771e97619c3775f8325daf4b8453cd51d6571 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20mb/via/epia-m850: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id6aa669542bcfd774fa5571d790f59f156a39a4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20soc/intel/skylake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Also fix the register offset in a comment in reset code. Tested successfully on X11SSM-F by reading ETR3. Change-Id: If190c3c66889ede105d958b423b38ebdcb698332 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/icelake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I3e450a473ccdf99221e82e0f857879039d78991b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36572 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/cannonlake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/common: pmclib: make use of the new ETR address APIMichael Niewöhner
Make use of the new ETR address API in the ETR3 register related functions. Further, disabling and locking of global reset is now done at once to save one read-modify-write cycle, thus the function was renamed accordingly and the now redundant disabling in soc/apl got removed. Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20soc/intel/skylake: add soc implementation for ETR address APIMichael Niewöhner
Add soc implementation for the new ETR address API. Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20include/device: add a comment to pci mmio cfg addr helpers and cachingMichael Niewöhner
Add a comment to the newly introduced MMIO address helpers for PCI config registers, that the pointer returned may change during the boot processs and, thus, must not be cached. Change-Id: Ieb90ae9d67a3b944d35587dec54756a17c27c86f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20purism/librem_bdw: add/use VBT fileMatt DeVillier
Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v1/15v2 boards, verify functional display after resume from S3 when using libgfxinit. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I44d75486da3083cd1f07ea82dc18688db84a621e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36916 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/lenovo/x201: Remove unnecessary GPIO settingsArthur Heymans
GPIO49 is strapped high, so setting it low likely increases power usage. GPIO53 is hooked to a testpad so there is no reason to set it here. Change-Id: I00fb38c90417b673c2b36191c20279474eb0dc21 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20/mb/google/hatch: Create jinlon variantWisley Chen
Create new variant for jinlon BUG=b:144150654 TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto board Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:50:05 +0000