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2020-07-06sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRSKeith Hui
Only two mainboard groups use this southbridge: emulation/qemu-i440fx: Nothing creates or consumes this ACPI path. asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O resources, which are being declared in DSDT. It is not doing anything useful and causes ACPI errors in Linux kernel[1][2], so it has to stop. [1] https://review.coreboot.org/c/coreboot/+/38601 [2] https://review.coreboot.org/c/coreboot/+/38304 Change-Id: I770047610e02c08191613b57c989b3bc1d464684 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06arch/x86: Remove RELOCATABLE_RAMSTAGEKyösti Mälkki
We always have it, no need to support opting-out. For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage located inside CBMEM, which is only true with ARCH_X86. Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer/var/voxel: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for voxel. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06mb/google/zork: Apply cereme telemetry settings for dalbozChris Wang
Currently, the telemetry settings are not for the pollock platform and might causethe power and performance issue. so applied the Pollock reference board settings to Dalboz to improve the performance, and the values need to be updated after the SDLE test finished. BUG=b:157961590,b:152922299 TEST=Build. Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Apply USB2 default phy tune parameter for Zork familyChris Wang
Apply the default USB2 phy tuning parameter for Zork family BUG=b:155132211 TEST=Build, verified the default value been applied on trembyle and the USB2 device works well. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I1f00b04173796d70147e232bafa405487b0761e1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Add USB2 phy tuning parameter for SI tuningChris Wang
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength. BUG=b:156315391 TEST=Build, verified the tuning value been applied on Trembyle. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I3d31792d26729e0acb044282c5300886663dde51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06mb/google/volteer: Add support for passive USB-C daughterboardCaveh Jalali
The USB-C SBU and HSL orientation configuration depends on the USB daughterboard used on the system. This patch adds an additional configuration for supporting passive USB daughterboards using "probe" directives to select the appropriate configuration at runtime. BUG=b:158673460 TEST=verified active USB DBs enumerate at USB3 speeds in linux Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-06mb/google/dedede: Create Boten Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of boten will use 16 MiB SPI ROM. So create a legacy Boten variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the boten and boten_legacy variant. Cq-Depend: TBD Change-Id: Idf7732768aa7fbf2281a4cbf47b7b5b4f8ef51da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06mb/google/dedede: Create Drawcia Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of drawcia will use 16 MiB SPI ROM. So create a legacy Drawcia variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the drawcia and drawcia_legacy variant. Cq-Depend: TBD Change-Id: Ifb5a4778abe38a396e35963a3270b0d3cc9809e0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06soc/amd/common: Fix missing gpio_banks.h includeKyösti Mälkki
Change-Id: I2c92280f3bbd80bd7a0d3abfb2fddcef997e144e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/amd/picasso/memlayout: Verify bootblock is 16-bit alignedRaul E Rangel
The bootblock must be 16-bit aligned for it to boot. BUG=b:159081993 TEST=Made sure trembyle still compiles. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart InitMaulik V Vaghela
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it. Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot BUG=None BRANCH=None TEST=FSP is able to push debug logs on UART with this setting Cq-Depend: TBD Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-07-06vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2194. BUG=b:159193895 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42471 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06soc/amd/picasso: Use PSP Sx command only for S3Marshall Dawson
Skip sending MboxBiosCmdSxInfo for sleep states other than S3. The PSP only acts on S3 and ignores all others. As a result, the command register is not cleared upon return and coreboot reports a timeout. BUG=b:153622879 TEST=Use halt from command line, verify command skipped. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-05arch/x86: Support x86_64 exceptionsPaul Menzel
* Doesn't affect existing x86_32 code. Tested on qemu using division by zero. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_initFurquan Shaikh
This change drops the check for ENV_RAMSTAGE in mainboard_ec_init() since it is included only in ramstage. Also, the content of ramstage_ec_init() is moved into mainboard_ec_init(). Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43118 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop mainboard_ec_init() from romstageFurquan Shaikh
mainboard_ec_init() does nothing in any stage other than ramstage. So, this change drops the call to mainboard_ec_init() from romstage.c. Additionally, it also drops ec.c from romstage and verstage. Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop unused function variant_romstage_entry()Furquan Shaikh
This change drops the function `variant_romstage_entry()` which is unused on zork. Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Drop codec.aslFurquan Shaikh
This change drops codec.asl file from Chrome EC since it is now unused. Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Use SSDT generator for Chrome EC audio codec deviceFurquan Shaikh
This change drops the inclusion of codec.asl in DSDT for `GOOG0013` device and instead uses the newly added Chrome EC audio codec driver for filling in the device node in SSDT. TEST=Verified that following node gets generated: Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (ECA0) { Name (_HID, "GOOG0013") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Add driver for audio codec deviceFurquan Shaikh
This change adds driver for audio codec device (HID `GOOG0013`) living behind Chrome EC. This driver generates the required ACPI node for the codec device. In a later change, GOOG0013 device will be dropped the .asl file. Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43041 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/KconfigFurquan Shaikh
This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the Kconfig file in i2c_tunnel is sourced unconditionally, but the configs in i2c_tunnel/Kconfig are conditionally defined based on the evaluation of if condition. This change addressed the feedback received on https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kconfig#200. Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/kahlee: Drop macro H1_PCH_INTFurquan Shaikh
This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion. Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-05arch/x86/Makefile.inc: Drop unused reset.c ruleAngel Pons
No x86 mainboard has a reset.c file. Change-Id: I167629c7addf485944926d57cf0228606c0f32e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42582 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/supermicro/x9scl: Select IPMI_KCSAngel Pons
Needed for `chip drivers/ipmi` in the devicetree. Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41687 Reviewed-by: Michael Niewöhner Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05drivers/pc80/tpm: Remove support code if TPM is disabledKyösti Mälkki
Change-Id: I7015d4bf6f536c5cea8e1174db81f09f756ae0e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner
2020-07-05mb/lenovo/x230s: Add MAINBOARD_HAS_LPC_TPMKyösti Mälkki
With devicetree listing drivers/pc80/tpm, it is compulsory to have the corresponding driver included in the build. Followup work will drop the associated weak function declaration that util/sconfig currently generates. Change-Id: Ife8deb2c973ab7c7b820244b6f72efd3b56570ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/poppy-nocturne: Add SX9310 driver unconditionallyKyösti Mälkki
Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41726 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05drivers/pc80/tpm/tis: Add x86_64 supportPatrick Rudolph
Fix integer with different size to pointer conversion on x86_64. Change-Id: Ic06a32d549b694310f4c724246f28fed15acf83f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42983 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05include/cpu/x86/lapic: Add support for x86_64Patrick Rudolph
Fix integer with different size to pointer conversion. Change-Id: I9c13892b2d79be12cc6bf7bc0a5e3a39b64032a1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/intel/pmc_mux: Rename con driver to connTim Wawrzynczak
For historical reasons, Windows has issues with certain names being used for files and directories, 'con' or 'CON' being one of them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in order to work around this issue. TEST=built volteer (only user of this driver as of now) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-04smbios: TYPE_NONE and TYPE_OTHER are already takenPatrick Georgi
Change-Id: Ic66f7c919a71cb53773d5056e5f756cd6faf4909 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43135 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04post_code: reorganize order of postcode definesSindhoor Tilak
Currently, the certain postcode values aren't in increasing order of values. The change, just reorganzies the defines in increasing order of the values Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net> Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU dataJohnny Lin
It implements the SMBIOS IPMI FRU mapping table defined in https://www.opencompute.org/documents/facebook-xeon-motherboard-v31 22.3 SMBIOS FRU mapping table. Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE. For type 11 string 1 to 6 are common and implemented in this driver, the rest are project dependent and can be added in the mainboard code. Tested on OCP Tioga Pass. Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40308 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04soc/intel/xeon_sp/cpx: update HOB display codeJonathan Zhang
Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB. Build hob display into romstage, in addition to ramstage. Memory map HOB data is a big structure. Update the soc_display_memmap_hob() to assist trouble shooting of FSP interface. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42841 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSIONJohnny Lin
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMCJohnny Lin
There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04arch/x86/smbios: Add SMBIOS type8 dataBryantOu
Refer to section 7.9 Port Connector Information of DSP0134_3.3.0 to add type 8 data, the table of data should be ported according to platform design and MB silkscreen. Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-04lib/coreboot_table: Add Intel FSP version to coreboot tableJohnny Lin
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION when PLATFORM_USES_FSP2_0 is selected. Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120" Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-04drivers/pc80/tpm: Remove LPC_TPMKyösti Mälkki
Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm is present in devicetree.cb it is necessary to always include the driver in the build. Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-04mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04soc/intel/xeon_sp: Add read CPU PPIN MSR functionJohnny Lin
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP Tioga Pass and Delta Lake. Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/ipmi: Add IPMI KCS support in romstageJohnny Lin
It's necessary to run IPMI commands in romstage for writing error SEL such as memory initialization error SEL, and also for other usages such as starting FRB2 timer, OEM commands, etc. Add CONFIG_BMC_KCS_BASE for BMC KCS port address that can be used across romstage and ramstage. Change-Id: Ie3198965670454b123e570f9056673fdf515f52b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40234 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04soc/intel/tigerlake: Remove unused EHL DID from TGL SoCSubrata Banik
TEST=Able to build and boot TGLRVP. Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-03mb/google/volteer: Enable CSE Lite SKU for ES2 platformsJamie Ryu
BUG=b:158140797 TEST=build and boot volteer with CSE Lite SKU Cq-Depend: chrome-internal:3100721 Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42070 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu
A UPD HybridStorageMode allows a platform to dynamically configure the PCIe strap configuration required if an Optane device is connected. The strap configuration is done by HECI commands between FSP and CSE to override the default PCIe strap value, and the updated strap value is stored in SPI RW data to be used on the next boot. CSE Lite supports the strap override when running on CSE RW partition, while CSE RO partition does not support it because CSE RO is not allowed to access SPI RW data. The strap override failure on CSE RO causes FSP not initializing PCH Clkreq and PCIe port mapping and this results NVMe and Optane initialization failure. By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is done by the default PCIe configuration and Optane is detected as a single NVMe storage device on CSE RO boot in recovery mode. Both NVMe and Optane devices detection as well as OS installation to these storage devices are verified on CSE RO boot in recovery mode. BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/zork: adjust eSPI virtual irq settingsAaron Durbin
The eSPI polarity macros were reversed. Those are fixed so adjust the corresponding values related to the correct expectations of the IRQ path: eSPI virtual wire IRQs are active level high. The EC sends active level high virtual wire IRQs. The default interrupt encodings in ACPI for P2/S devices are active edge high. Therefore, there is no need to override anything. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03soc/amd/common: fix eSPI virtual wire polarity encodingAaron Durbin
eSPI interrupts are active level high. The eSPI polarity register in the chipset inverts incoming signals if the corresonding bit is 0 in the register. Therefore, all active high (edge or level) virtual wire interrupts need to ensure they are not inverted. And really the sender of the interrupts should be conforming to the the eSPI spec. As such inverting any signals should not be necessary, but this register in the chipset allows for fixing up those misbehaviors. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03mb/intel/cannonlake_rvp: Unconditionally select audio driversKyösti Mälkki
Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41706 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/coffeelake_rvp: Unconditionally select audio driversKyösti Mälkki
Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41705 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPIKyösti Mälkki
Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41703 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03drivers/intel/pmx_mux: Remove redundant declarationKyösti Mälkki
Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41871 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03soc/intel/common: Only touch Time Window Tau bits in supported SoCsTim Wawrzynczak
The Time Window Tau bits are only supported by Comet Lake/Cannon Lake onwards, so skip setting those bits for earlier SoCs. Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in WyvernEdward O'Callaghan
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in NoibatEdward O'Callaghan
BUG=b:160296662 BRANCH=none TEST=none Change-Id: I5298e1779461995a98722099b397692351767089 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in FaffyEdward O'Callaghan
BUG=b:160295948 BRANCH=none TEST=none Change-Id: I3600340d3448457942c827a463b458b280fea19a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in KaisaEdward O'Callaghan
BUG=b:160296661 BRANCH=none TEST=none Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in DuffyEdward O'Callaghan
BUG=b:160296325 BRANCH=none TEST=none Change-Id: Iffa6997029d0babfd6dd504a6cc212bd74de3a8f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42972 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/pcengines/apu1/mainboard.c: reorder includesPiotr Kleinschmidt
Originally, there was problem with PC Engines apu1 platform which returned serial number value as -64. It was caused by wrong value of dev->bus->secondary. Source of the problem is in Porting.h header file. It contains '#pragma pack(1)' which affects struct device. As mainboard.c uses different binary layout because of this attribute, reference dev->bus->secondary lands at wrong memory address. This patch reorder includes and put <AGESA.h> and <AMD.h> at the end of list, making struct device consistent. As a result bus number value in device's structure is correct and hence serial number. TEST=`dmidecode -t 2` command in Linux Debian Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42512 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02nb/intel/ironlake: Clean up code style (except raminit)Angel Pons
Reflow lines, correct coding style and align struct members, among other things. As raminit is very large, handle it on a follow-up. Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change. Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/google/zork: Generate I2SM ACPI device at runtimeFurquan Shaikh
This change moves the generation of I2SM ACPI device from static asl file to runtime generation by ACP device driver. dmic_select_gpio is set to match version 3+ of Trembyle and Dalboz schematics. In order to maintain backward compatibility, dmic_select_gpio is updated at runtime using variant_audio_update for board versions that are prior to version 3 of reference schematics. The only difference from static generation is that the device I2SM is added under ACPD (i.e. ACP device) instead of CREC (Chrome EC device). It does not make any functional difference from the kernel perspective. BUG=b:157603026 TEST=Verified that the following device gets generated in SSDT: Scope (\_SB.PCI0.PBRA.ACPD) { Device (I2SM) { Name (_HID, "AMDI5682") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "I2S machine driver") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x000D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "dmic-gpios", Package (0x04) { \_SB.PCI0.PBRA.ACPD.I2SM, Zero, Zero, Zero } } } }) } } Verified audio via speakers and mic input. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253638 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02soc/amd/picasso: Add support for generating I2S machine deviceFurquan Shaikh
This change adds support in ACP device driver to generate I2S machine device (AMDI5682) in SSDT. It expects mainboard to provide chip config `dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the device. BUG=b:157603026 TEST=Verified that I2S machine device is correctly generated for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252557 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP deviceFurquan Shaikh
This change adds support for .acpi_name and .acpi_fill_ssdt_generator device operations for the ACP device. BUG=b:157603026 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I84bb8150dada99def85b685535706aa609de227f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252556 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02acpi_device: Replace polarity with active_low in acpi_gpio for GpioIoFurquan Shaikh
As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the corresponding GPIO should be treated as active low. Thus, if GPIO has active high polarity or if it does not have any polarity associated with it, then the `active_low` argument is supposed to be set to 0. Having a `polarity` field in acpi_gpio seems confusing because GPIOs might not always have polarity associated with them. Example, in case of DMIC-select GPIO where 0 means select DMIC0 and 1 means select DMIC1, there is no polarity associated with the GPIO. Thus, it would be clearer for mainboard to use macros without having to specify a particular polarity. In order to enable mainboards to provide GPIO information without polarity for GpioIo usage, this change also adds `ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros. BUG=b:157603026 Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02acpi_device: Add helper macros for setting acpi_gpio fieldsFurquan Shaikh
This change adds helper macros for initializing acpi_gpio fields for GpioIo/GpioInt objects. This allows dropping some redundant code for each macro to set the structure fields. Change-Id: Id0a655468759ed3035c6c1e8770e37f1275e344e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02drivers/generic/gpio_regulator: Drop unused driver for gpio_regulatorFurquan Shaikh
Proposal for gpio_regulator usage in ACPI never got accepted upstream for Linux kernel. So, the gpio_regulator driver in coreboot remains unused. This change drops this unused driver. Change-Id: Ia1e0ae4f955b9ffc8346d957f755499419d8cbc7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02mb/ocp: remove sonorapassJonathan Zhang
Sonora Pass server program was terminated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42948 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02soc/amd/common: fix SPI bar resource usageAaron Durbin
The ACPI code was not masking off the correct bits for publishing the SPI bar to the OS. It resulted in a dmesg messagelike: system 00:00: [mem 0xfec10002-0xfec11001] has been reserved And /proc/iomem entry fec10002-fec11001 : pnp 00:00 These addresses are wrong because they are including bits of a register that are not a part of the address. Moreover, the code does not publish the eSPI register area either. The eSPI registers live at 0x10000 added to the SPI bar. Lastly, both regions are less than a page so only report a page of usage for each. Stoney Ridge's SPI bar register defines the address as 31:6 while Picasso's SPI bar register defines the address as 31:8. Use Picasso's valid mask for both cases because no one is assigning addresses that are aligned to less than 256 bytes. With the fixes, dmesg reports: system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved And /proc/iomem indicates: fec10000-fec10fff : pnp 00:00 fec20000-fec20fff : pnp 00:00 BUG=b:160290629 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/42959 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/google/faffy: update DPTF parametersTim Chen
Modify DPTF parameters for faffy from thermal team. BUG=b:160292247 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage verify the parameters are correct Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-01nb/intel/ironlake/northbridge.c: Drop thunk functionsAngel Pons
Just call the called function directly. Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01mb/google/zork: Move EC wake to happen in ramstageFurquan Shaikh
Currently, EC wake signal (GPIO_24) is configured early on in romstage. However, there is no need for that since EC wake is not really required to be configured until ramstage. This change moves GPIO_24 configuration to happen in ramstage. BUG=b:159832123 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42952 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01mb/google/zork: Fix pad configurations for wake signalsFurquan Shaikh
This change updates the pad configurations for wake lines as follows: 1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake using GPIO controller block. This is because pen eject signal is not dual routed and the trigger filtering is set by the kernel driver differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and instead has to fall back to using GPIO controller wake. 2. All other wake signals (EC, trackpad, fingerprint) need to be configured as SCI. This allows OS to enable/disable wake from these sources if required. Example: powerd disables wake from trackpad when in tablet mode. Hence, all other wake sources use SCI. BUG=b:159832123 TEST=Verified wake using pen eject and EC. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42951 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01mb/google/dedede: set tcc_offset value to 10Sumeet R Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42906 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01nb/intel/ironlake: Drop copy-pasted and unused macroAngel Pons
Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I78856707864563e392626a494f0e77eec9802002 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Use `pci_update_config32()`Angel Pons
Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Simplify BAR handlingAngel Pons
Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake/ironlake.h: Clean upAngel Pons
Align values and drop copy-pasted, wrong and unused definitions. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/ironlake: Drop copy-pasted and dead codeAngel Pons
This function was copy-pasted, comments included, from Sandy Bridge. However, it is only called with 0x0044 as the northbridge's PCI ID. Therefore, `bridge_silicon_revision() & BASE_REV_MASK` will always evaluate to 0x40, which never equals `BASE_REV_SNB`, that is, 0x00. As the condition is always false, treat this code as dead and drop it. Following a similar reasoning, all direct comparisons against SNB steppings will always be true, because `bridge_silicon_revision()` returns at least 0x40 which is always larger than either `SNB_STEP_D0` or `SNB_STEP_D1`. So, drop all but the code path that is actually used. Change-Id: I5219a6af3df98ed77c9c4abfb9a63c2ebf8171bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01mb/google/zork/var/morphius: Enable support for garaged stylusFurquan Shaikh
This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for morphius. BUG=b:158814699,b:158719244 Change-Id: I3530a0aa83ec69559436687205c64524b862799b Signed-off-by: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Drop unused/unnecessary GPIO macrosFurquan Shaikh
This change drops macros for GPIOs which are unused or don't really require extra indirection (same across all variants). BUG=b:159283649 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1a94327103a419f26b1d7feda4c995363ada7281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork/var/ezkinil: Fix GPIO_86 configuration for bid3Furquan Shaikh
Board version 3 for Ezkinil follows Trembyle reference v3.51 schematics and hence GPIO_86 does not need a variant specific override. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7e04baad976f94d0d94e7196f0408c3c3237b2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/42940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Drop GPIO_27 configuration for trembyle referenceFurquan Shaikh
This change drops GPIO_27 configuration for trembyle reference boards since it is unused. BUG=b:159453643 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I57dd78e8abcc61802ca85158e7ff348460ad1d8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Add support for active low wifi power enableFurquan Shaikh
A late change went into v3+ of reference schematics which inverted EN_PWR_WIFI to meet PCIe reset/power timings for WiFi device. This is incorporated into v3.51+ for Trembyle reference and v3.2+ for Dalboz reference. However, some variants are built with v3+ reference schematics, but without the inversion of EN_PWR_WIFI polarity. Thus, we need to add support for following combinations: 1. Pre-v3 Schematics 2. V3+ Schematics 3. V3+ Schematics + Active low wifi power This change adds a new Kconfig `VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW` that sets the minimum board ID that has EN_PWR_WIFI active low in hardware. Variants that missed this change in V3+ integration (berknip and vilboz) have board IDs set to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS + 1. For others, this defaults to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS. BUG=b:159749536 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib8da7fba5f4a518a51b203d6a01a9551e261d8b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Move GPIO sleep table to dalboz and trembyle referenceFurquan Shaikh
This change moves variant_sleep_gpio_table() definition to dalboz and trembyle references to allow each to make their own changes. BUG=b:159749536, b:159453643 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I15b19cea05f1a540c56b6bc0507306d2348ac17f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalbozFurquan Shaikh
This change moves PCIE_RST1_L deassertion to happen as part of variant_pcie_power_reset_configure() instead of variant_romstage_entry() since romstage is guaranteed to run 100ms+ after PP3300_NVME is enabled. This is one of the first things that coreboot on x86 does as part of early mainboard configuration. Additionally, this change also drops deassertion of PCIE_RST0_L on bid 1 for dalboz since PCIE_RST0_L is already deasserted much earlier in the boot flow. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261996 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Configure GPIO_40 as drive low in sleep pathFurquan Shaikh
This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in sleep path so that the PERST# to NVMe device keeps asserted until coreboot reconfigures it as high on S3 resume path. This is similar to the earlier change for PCIE_RST1_L but helps platforms that use NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain, hence it retains state across S3 entry/exit. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie79e946eee8f393863630226ae2183e653030415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep pathFurquan Shaikh
This change configures PCIE_RST1_L as GPO driven low on the sleep path. This is required to keep PERST# asserted to devices until coreboot deasserts it on S3 resume path. Without this change, on S3 resume, PCIE_RST1_L gets deasserted sooner than required resulting in violation of PCIe reset timings. With this change, the behavior of PCIE_RST1_L is as follows: 1. GPIO27 is configured as NF (PCIE_RST1_L) in coreboot bootblock/romstage and driven high. 2. On S3 entry, GPIO27 is configured as GPO driven low. * Boot out of G3: Timing should be met since GPIO_27 is pulled down by default until coreboot configures it. * S3 resume: Timing should be met since GPIO_27 is configured as GPO low and it retains state across S3 entry/exit. So, should be low until coreboot configures it. * Warm reset: Timing should be met since it is configured as NF. So, hardware guarantees the reset timing as seen in "warm reset.jpg" in #46. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261116 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Turn off power to camera and pen in sleep pathFurquan Shaikh
This change turns off power to camera and pen devices when entering sleep since they do not act as wake sources in S3. Power to trackpad and WiFi is left enabled since they are wake sources for S3. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I21bcdd53370372c7d43c3b685abb2a9171e42d22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261115 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01mb/google/zork: Add support for GPIO configuration on sleep pathFurquan Shaikh
This change adds support to configure GPIOs on the sleep path. This is required to turn off power to devices that do not act as wake sources and to assert reset to devices. Currently, variant_sleep_gpio_table() returns an empty table by default. In the following changes, entries will be added to gpio_sleep_table. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253642 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01nb/intel/ironlake: Remove unused structsAngel Pons
These were copied from gm45, but are not used. Drop them. Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01nb/intel/pineview: Drop undefined function declarationAngel Pons
This function isn't defined anywhere for Pineview. Drop its declaration. Change-Id: I38a01d6ba5aaa91de08702c1eb8a2e8c70688192 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entryJamie Ryu
This is a W/A to avoid a communication issue with CSE Lite over Heci interface. This will help to avoid boot failures with CSE Lite until the permanent fix is available. BUG=b:159884143 TEST=build and boot volteer with serial and non-serial image Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01mb/google/nightfury: Override VBT selection for nightfury 2nd skuSeunghwan Kim
Override VBT for nightfury SKU_ID = 2 to support different panel. BUG=b:159051021 BRANCH=firmware-hatch-12672.B TEST=Built and verified using different VBT by SKU_ID Change-Id: I9450814aadc43cc7991457c3793f109b889186b9 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-01mb/google/zork: update G2 TS RST delay timeKevin Chiu
in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even rst delay time already meets spec definition: 10us (minimum). Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine on those specific m/b+BOE(G2 TS) panel. BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-01mb/prodrive/hermes/variants/baseboard: configure sataHotplugJonas Loeffelholz
Configure sataHotPlug in devicetree, as this functionality is now available for this soc. Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42804 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/cannonlake: make satahotplug user configurable via devicetreeJonas Loeffelholz
Hook up the FSP UPD Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42803 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/common/cpu: Don't set any TCC settings if offset is 0Tim Wawrzynczak
Many previous versions of this function would return early if tcc_offset is 0. This adds that logic back in. Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-07-01soc/intel/skylake: Update ASL syntax in xhci.aslEdward O'Callaghan
Use some defines as well for clarity. Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42898 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4John Zhao
This change adds Platform-Wide _OSC capabilities for native USB4 support. There is Engineering Change Request (ECR) with _OSC addition for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18 as native USB4 support. The OS sets this bit to indicate support for an OSPM-native USB4 Connection Manager which handles USB4 connection events and link management. The OS use the _OSC mechanism and the bit defined in this ECR to obtain configuration and connection management capabilities of USB4 connections. This change also fixs the byte index for the DWord-addressable field CDW3 from the capabilities buffer. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/42821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 11:19:36 +0000