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2013-03-08AMD Inagua: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the inagua mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2607 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08AMD CIMx SB800 boards: platform_cfg.h: Integrate Kconfig SATA Mode choicePaul Menzel
Currently for Advansus A785E-I, ASRock E350M1 and ASUS M5A88-V despite what is chosen in Kconfig »Chipset« menu item, $ more .config […] # CONFIG_ENABLE_IDE_COMBINED_MODE is not set CONFIG_IDE_COMBINED_MODE=0x1 # CONFIG_SB800_SATA_IDE is not set CONFIG_SB800_SATA_AHCI=y # CONFIG_SB800_SATA_RAID is not set CONFIG_SB800_SATA_MODE=0x2 […] the SATA controller is put into IDE mode. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40) Commit »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [1] added the options above to configure the mode using Kconfig and some SB800 boards were adapted already. For example commit »persimmon: sb800 sata mode configure update« (1386fa74) [2] did so for AMD Persimmon. Doing the same by assigning the Kconfig variable to the value in `platform_cfg.h` integrates this with the three remaining boards listed above. The patch is successfully tested with the ASRock E350M1. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40) [1] http://review.coreboot.org/225 [2] http://review.coreboot.org/227 Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08AMD Persimmon: mainboard.c: Make comment generic to reduce differencePaul Menzel
Replace »persimmon« by »board« in comment to keep `diff` output between boards small. Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08AMD Union Station: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the union_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I19d6b0d674b67294519383f80928471b37da1e14 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08AMD South Station: Use SPD read code from F14 wrapperKimarie Hoot
Changes: - Get rid of the south_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08ARMV7 and Google/Snow: Add exception support code to the ramstageRonald G. Minnich
This is previously used exception code from libpayload. On startup it installs and then tests an exception handler. The test is an unaligned memory operation. Yes, we've seen what might be exceptions in the ramstage, and it makes sense to handle them. This code is identical in structure and operation to the previously committed payload exception handler, though we reserve the right to change it as circumstances require. The remaining question is whether we need it in romstage. Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-08AGESA: Fix CR0_PE bit defineKonstantin Aladyshev
AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08Supermicro H8QGI: set up right frequency limits for memory controllerKonstantin Aladyshev
According to BKDG: "Memory controller (MCT) and DRAM controllers (DCTs) additions: • Support for 933 MHz (1866 MT/s) MEMCLK frequency." Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15Konstantin Aladyshev
_RDMSR instruction loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. EDX:EAX = MSR[ECX] So bit 49 will be contained in EDX register. Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis). PfcStrideDis bit disables stride prefetch generation. This leads to memory bandwidth loss. _________ Supermicro H8QGI board After applying this change i observed huge memory bandwidth increase in tests that runs on small amount of cores. But unfortunately it doesn't affect overall bandwidth results on 4P system with 48 cores. So i think that in this system leading limiting factor is AMD HT-ASSIST feature (Probe filter). But right now it is not working. System stucks in Linux boot. I have done some experiments and figured out that stuck happens when system have cores in compute unit (CU) other than CU with BSC (boot strap core). CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...) So with probe filter i can boot Linux with one (BSC) or two (BSC + secondary core in its CU) cores. And with this configuration i can see memory bandwidth on 1 core (or two cores) close to original bios. Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2588 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08FrontRunner/Toucan-AF: lower SPI speed to 22 MHzJens Rottmann
The Hudson-E1's default SPI speed for normal i.e. non-fast reads is 66 MHz, but the SST 25VF032B datasheet allows max. 25. Lower the speed to 22 MHz, otherwise BIOS flashing fails. Change-Id: I22e87d833a3ebd316b6e873595a2480831533ab1 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2605 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07AMD Persimmon: Use SPD read code from F14 wrapperMartin Roth
Changes: - Get rid of the persimmon mainboard specific code which has been moved into the wrapper as a platform generic function in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2500 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07AMD Fam14: Add SPD read functions to wrapper codeMartin Roth
Change: This is the initial step for moving the AMD F14 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Persimmon, and was changed to use the devicetree.cb structures. The ASF setup was also removed from the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed for the SPD access and doesn't make sense to initialize here. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBUS initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2497 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07Remove UTF-8 characters from commentsRonald G. Minnich
I've used an operating system for over 10 years now that makes UTF-8 easy. It's not called Linux or OSX. When UTF-8 is needed, of course, then we can look again. I can't think of a single redeeming feature of placing it in the comment in this manner. It's certainy not needed. The inclusion of UTF-8 characters is inconvenient, especially from a text terminal. I don't really want to start using compose in CROSH shell terminals on chromeos. We might want to incorporate "no UTF-8" as a commit filter. For now, get rid of these characters. Change-Id: If94cc657bae1dbd282bec8de6c5309b1f8da5659 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2604 Reviewed-by: Bernhard Urban <lewurm@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07Revert "ARMv7: Simplify div64"David Hendricks
This reverts commit 1cd616082100f47dc2d6d73669c6aa2e5eb039ad Division bites us again. I don't know how or why, but printk() seems to break (again) with this patch. I'm surprised we didn't encounter problems earlier on... Change-Id: I81cb9f20879f5eb73a76e1af47b96a68d1e81dc8 TODO: Find a better solution for div64. This one is too painful, but seems necessary for now (and sort-of works with our vtxprintf hack). Reviewed-on: http://review.coreboot.org/2600 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07snow: add real values for GPIOs in fill_lb_gpios()David Hendricks
This adds some real GPIO mappings where virtual GPIOs were used before. Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07exynos5: add GPIO port enumsDavid Hendricks
This adds an enum for GPIO ports on the Exynos5. To make them useful, they are assigned the absolute MMIO address where a s5p_gpio_bank struct can point to. Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2602 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07google/snow: fix coding styleStefan Reinauer
cosmetics Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2601 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-07src/arch/x86/boot/acpigen.c: Small coding style and comment fixesPaul Menzel
While reading through the file fix some spotted errors like indentation, locution(?), capitalization and missing full stops. Change-Id: Id435b4750e329b06a9b36c1df2c39d2038a09b18 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07Fix build by adding `cbmem.c` to `COLLECT_TIMESTAMPS`Kyösti Mälkki
A board without HAVE_ACPI_RESUME did not build with COLLECT_TIMESTAMPS enabled as `cbmem.c` was not built. Change-Id: I9c8b575d445ac566a2ec533d73080bcccc3dfbca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2549 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07Intel e7505: provide get_top_of_ramKyösti Mälkki
This is required to enable EARLY_CBMEM_INIT. Change-Id: I6d8caf382aa48eded81c1e94bbbcd3975ea88a1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07Fix socket LGA775Kyösti Mälkki
Models 6ex and 6fx select UDELAY_LAPIC so cannot select contradicting UDELAY_TSC here. Model 1067x requires speedstep. Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-07ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`Paul Menzel
Quoting Jens Rottmann [1]: Nevertheless I still think this whole function is bogus for the E350M1. The function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5 as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3. But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely different layout. They could have chosen GPIO21 to force resets, or 25 - or maybe 50 like on the Persimmon or any other they fancied or - and this is the most probable - none at all. Having BiosGnbPcieSlotReset() toggle some GPIOs without knowing what they do on the E350M1 (if anything at all) is nonsense. In my opinion this whole function should just "return AGESA_UNSUPPORTED" and good riddance. [1] http://review.coreboot.org/#/c/2445/ Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2489 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2013-03-06samsung/exynos5: add display port and framebuffer defines and initializationRonald G. Minnich
These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2570 Tested-by: build bot (Jenkins)
2013-03-06ASRock E350M1: mainboard.c: Add declarations for `set_pcie_{,de}reset`Paul Menzel
Since the merg of the ASRock E350M1 port (a649a96e) the compiler warns about the following [1]. mainboard.c:35, GNU Compiler 4 (gcc), Priorität: Normal no previous prototype for 'set_pcie_reset' [-Wmissing-prototypes] mainboard.c:43, GNU Compiler 4 (gcc), Priorität: Normal no previous prototype for 'set_pcie_dereset' [-Wmissing-prototypes] Adding the function prototypes to the beginning of the file as done in commit »Persimmon updates for AMD F14 rev C0« (d7a696d0) addresses the warning. [1] http://qa.coreboot.org/job/coreboot-gerrit/4975/warnings13Result/package.-139448264/file.-1544928473/ [2] http://review.coreboot.org/137 Change-Id: Iad2e62ec37c3a2f749a264974b61ac7c226e9b83 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-06Google/Snow: enable sound hardware clocksRonald G. Minnich
Set up the clocks used for sound and turn on the sound clock. Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8 Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2587 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06google/snow: Change MMC0 to work in 8 bit mode.Ronald G. Minnich
The MMC0 on google/snow can run in 8 bit mode. To simplify driver development, we thought disabling it (using zero, which runs in 1-bit / 4-bit mode) may help. However, after some experiments in payload drivers, setting pinmux to 8 bit mode can still allow MMC to run in 1-bit / 4-bit mode, so it's pretty safe to enable 8 bit mode by default for better performance. Verified to boot on google/snow, and got MMC0 working. Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2585 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperioJens Rottmann
The power up default for the 14M_25M_48M_OSC switchable clock output ball of the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not configurable for other clock speeds. A wrong SIO clock supply results in funny RS232 output (wrong bit speed) and non-working PS/2. We could switch back to 14 MHz in the mainboard's romstage.c, but then the clock frequency would change twice. The resulting short 48 MHz burst causes a handful of rubbish characters on RS232 on every boot until the SIO clock has stabilized again. This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-04FrontRunner/Toucan-AF: drop unnecessary compile time CPU model selectionJens Rottmann
The first reason for selecting the CPU model at compile time was a multi-second pause if booting a single core Fusion T40R with MAX_CPUS=2. Recent tests show the pause has disappeared, someone must have fixed it. The second reason was me not knowing how to make a single vgabios image work with two different PCI IDs. Many thanks to Martin Roth for educating me! Quote: "The way to make coreboot use the same vbios for different video device IDs is through the map_oprom_vendev function. In family 14 it's in northbridge/amd/agesa/family14/amdfam14_conf.c You would name your video bios 1002,9802 in the config and all the other device/vendor IDs for the family 14h processors will fall through the initial check for the video bios and will get remapped to use that vbios. This only works if you're initializing the vbios inside coreboot. I don't know if you're using SeaBios as a payload, but if you are you can add the vbios to cbfs as vgaroms/vbios.rom and the rom will always be initialized." I'd like to add the vgabios is added as type 'optionrom' when Coreboot make adds it, however to work with SeaBios it has to be added manually with cbfstool and with type 'raw', or it will hang. Change-Id: I8190d0c3202a60dfccb77dde232f9ba7ce5ce318 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2584 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-04ARM: remove code that is IMHO a dangerous designRonald G. Minnich
OK, this is tl;dr. But I need to write this in hopes we make sure we don't put code like this into coreboot. Ever. Our excuse in this case is that it was imported, not obviously wrong, and easily changed. It made sense to get it in, make it work, then do a cleanup pass, because changing everything up front is almost impossible to debug. The exynos code has bunch of base register values, e.g. These are base addresses of things that look like a memory-mapped struct. To get these to a pointer, they created the following macro, which creates an inline function. static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } And then invoke it 31 times in a .h file, e.g.: SAMSUNG_BASE(clock, CLOCK_BASE) to create 31 functions. And then use it: struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing. I have a long list of what's wrong, and I may leave some things out, but here goes: 1. the "function" can return a NULL if we're not on exynos5. Most uses of the code don't check the return value. 2. And why would this function be running, if we're not on an exynos5? Why compile it in? 3. Note the cast everywhere a samsung_get_base_xxx is used. The function returns an untyped variable, requiring the *user* to get two things right: the cast, and the function invocation. One can replace that _clock(); with _power(); in the code above, and they will be referencing the wrong registers, and they'll never get an error! We have a C compiler; use it to type data. 4. You're generating 31 functions using cpp each and every time the file is included. The C compiler has to parse these each time. It's not at all like a simple cpp macro which is only generated on use. 5. You can't tags or etags this code 6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic. That's only a partial list. So what's the right way to do it? Just make typed constants, viz: Or, since I expect people will want the lower case function syntax, I've left it that way: Now we've got something that is efficient, and we don't even need to protect with any more. Hence this change. We've got something that is type checked, does not require users to cast on each use, will catch simple programming errors, can be analyzed with standard tools, and builds faster. So if we make a mistake: struct exynos5_clock *clk = samsung_get_base_adc(); We'll see it: src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk': src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror] which we would not have seen before. As a minor benefit, it shaves most of a second off the compilation. Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2582 Tested-by: build bot (Jenkins)
2013-03-04bump SeaBIOS to 1.7.2.1Idwer Vollering
Update coreboot to use SeaBIOS' tag rel-1.7.2.1 Change-Id: I01969407964a7cf64f7c4800b59c6aed845b24f9 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/2575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-03-03AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in commentPaul Menzel
Commit f154c018 Author: Marc Jones <marcj303@gmail.com> Date: Wed Dec 14 11:24:00 2011 -0700 Persimmon audio codec verb patch. Reviewed-on: http://review.coreboot.org/490 has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As this was copied over to the LiPPERT Fam14 boards, use the following command to fix the typo. $ git grep -l cocec | xargs sed -i s,cocec,codec, Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2576 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-02ASRock E350M1: Remove non-existing PCI devices 12.1 and 13.1Paul Menzel
Looking at the coreboot log […] PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled […] and the `lspci -tnvv` output running the proprietary vendor BIOS attached to the Wiki page of the ASRock E350M1 [1][2] -[0000:00]-+-00.0 1022:1510 +-01.0 1002:9802 +-01.1 1002:1314 +-04.0-[01]-- +-11.0 1002:4391 +-12.0 1002:4397 +-12.2 1002:4396 +-13.0 1002:4397 +-13.2 1002:4396 […] both PCI devices do not exist, so remove them from `devicetree.cb`. Commit 48918f7 [3] Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does did the same for AMD Inagua and AMD Persimmon. [1] http://www.coreboot.org/ASRock_E350M1 [2] http://www.coreboot.org/File:ASRock_E350M1_info_dump.tar.bz2 [3] http://review.coreboot.org/2463 Change-Id: Ief6de1bda093d1f29d5925985e5c3839cdded537 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2536 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-02FrontRunner/Toucan-AF: work around AGESA RAM init crashing on rebootJens Rottmann
If you try to reset the system with outb(3,0x92), outb(4,0xcf9) or a triple-fault it will instead crash with a messy screen. As the more common outb(0xFE, 0x64) doesn't work with our setup, Linux will crash whenever you ask it to reboot. Closer inspection shows that on a warm boot of Coreboot agesawrapper_amdinitpost() always fails with error code 7. Looks like DDR3 re-init goes wrong somehow. I tried find the reason for this but was unable to. I am convinced this is not board specific but a bug in AGESA. In the end I had to settle for a workaround: if amdinitpost returns 7 this patch resets the system harder with outb(0x06, 0x0cf9), after that RAM init will succeed. As amdinitpost is early in POST this automatic reset is quick enough not to be noticable. I'd perfer a real fix, but that's all I have. Change-Id: I4763254b489f42a135232e45328ecf0d5c4d961a Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2573 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT Toucan-AF [2/2]: actually implement mainboard supportJens Rottmann
Step 2: change the Persimmon code to adapt it to the new board's hardware. The Toucan-AF is a COM Express Compact Type 6 form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU - 1-4 GB DDR3 memory down - 1x VGA, 2x DisplayPort (1 switchable to LVDS) - AMD A55E (Hudson-E1) southbridge - 8x USB 2.0 - 4x SATA - HD Audio (with codec on baseboard) - NEC uPD78F0532 microcontroller on I2C ("SEMA") - 7x PCIe2.0 x1 (1 on PEG) - Intel I210 GbE (on APU PCIe x1, can be disabled for additional PCIe) - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS) The Toucan-AF has no SIO on board. This patch includes basic support for a Winbond W83627DHG (PS/2, 2x RS232), because the ADLINK ExpressBase-6 used for evaluation happens to have one. The code may have to be adapted to the actual baseboard of the application. http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 Change-Id: I9041b905bad45852ac9b402fcbd5decbc98b377b Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT Toucan-AF [1/2]: create board by forking AMD PersimmonJens Rottmann
Step 1: copy all files unmodified from Persimmon. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Git's copy detection is imperfect (and slow). Change-Id: I1ff02913479c07679f8c3ae5e6dd7876e6000b55 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2571 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT FrontRunner-AF [2/2]: actually implement mainboard supportJens Rottmann
Step 2: change the Persimmon code to adapt it to the new board's hardware. The FrontRunner-AF is a PC/104+ form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU - DDR3 SO-DIMM socket (1.5 or 1.35V) - VGA and LVDS (via Analogix ANX3110) - AMD A55E (Hudson-E1) southbridge - 6x USB 2.0 - 1x SATA, 1x CFast socket - HD Audio (via Realtek ALC886) - PCI and ISA (via ITE IT8888) - NEC uPD78F0532 microcontroller on I2C ("SEMA") - Intel I210 GbE (on APU PCIe x1) - SMSC SCH3112 SIO - PS/2 - 2x RS232/485 - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS) http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131 Change-Id: Id55f89d224ad669b351c36128b12299802b721ba Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-02LiPPERT FrontRunner-AF [1/2]: create board by forking AMD PersimmonJens Rottmann
Step 1: copy all files unmodified from Persimmon. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Git's copy detection is imperfect (and slow). Change-Id: I2fd1bf8428fc8a1e7becee888b6182b9bd8166a0 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2552 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01armv7/snow: Add S5P MSHC initialization in ROM stage.Hung-Te Lin
The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and pinmux settings before it can be detected and used in ramstage / payload. Verified on armv7/snow and successfully boot into ramstage. Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2561 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28Revert "ARMv7: drop special handling for stages.c"Ronald G. Minnich
This breaks booting, and in fact stages.c is always going to be special: for it to work it has to be compiled for arm only, no thumb allowed. It's probably better to leave the stages.o target in explicitly so it's clear that it has to be compiled with a particular set of flags, rather than try to remember that we must always have the default rules no break stages.c compilation. That would be a mess. I will be pushing a CL to get rid of the assembly dump, but will be a trivial fix. This reverts commit 8f4647a24bf19a96531af9905b23ae8a2fc2675a Change-Id: I5e3d8e5b991f6ccf4d49078378cd4615fb230ca0 Reviewed-on: http://review.coreboot.org/2554 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28CBMEM: always initialize early if the board supports itStefan Reinauer
This allows to drop some special cases in romstage.c Change-Id: I53fdfcd1bb6ec21a5280afa07a40e3f0cba11c5d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2551 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28Drop SRC_ROOT from mainboard Makefile.incsStefan Reinauer
It's not used, and not needed. Change-Id: Ifca92f3606ac58fc26e09676488c3add5d84ae79 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28Use defines for some i82801ex/gx registersKyösti Mälkki
Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-28ARMv7: drop special handling for stages.cStefan Reinauer
This is a leftover from when we were debugging this code. Let's make it easier to understand. Change-Id: Ia3d0ab1504ff9dd9634d5f393d3c59fe1e43a0c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2543 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27Fix microcode selection codeStefan Reinauer
The ARM CPUs we know of don't have CPU microcode updates, so don't show the selection in Kconfig. Also simplify (and fix) the microcode selection in the Makefile that would try to include microcode even though none is available. Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2540 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-27Google/snow: update the GPIO emulation.Ronald G. Minnich
Add two more GPIOs (total 6) as needed by the Google Snow laptop. These are faking out settings for now. This code is tested and working. Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2538 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-02-27Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cbJens Rottmann
Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.) turned off the device in AGESA. Now remove it from devicetree.cb, too. This prevents the following boot message: PCI: Left over static devices: PCI: 00:01.1 PCI: Check your devicetree.cb. Also clarify the line's comment a bit for the Fam14 boards which still retain this device (to counter the loss of information ;-). Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2537 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-27selfboot: Report correct entry point address in debug message.Hung-Te Lin
Entry point in payload segment header is a 64 bit integer (ntohll). The debug message is currently reading that as a 32 bit integer (which will produce 00000000 for most platforms). Change-Id: I931072bbb82c099ce7fae04f15c8a35afa02e510 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2535 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset. Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed. Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27Mainboard SMI S state handler was using the wrong definesMarc Jones
The PCH register bit definition for sleep type is a little confusing. For example, 7 is S5. To make this simpler for the mainbaord developer, the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2). A couple mainboard SMI handlers were using the PCH define for slp_ty, so S3 code would be run for S5 and S5 code would never be run. Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27IOAPIC: Divide setup_ioapic() in two parts.Kyösti Mälkki
Currently some southbridge codes implement the set_ioapic_id() part locally and do not implement the load_vectors() part at all. This change allows clean-up of those southbridges without introducing changed behaviour. Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/300 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26Unify setting 82801a/b/c/d IOAPIC IDKyösti Mälkki
Remove obscure local copy of writing the ioapic registers. Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26AMD Inagua: buildOpts.c: Adapt whitespace to coding stylePaul Menzel
Mainly replace spaces by tabs and format comments correctly. Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was unfortunately incomplete and also used spaces instead of tabs in some cases. Hopefully fix this once and for all to have a template for the other boards. [1] http://review.coreboot.org/547 Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabledJens Rottmann
Commit »AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'« (22ec9f9a) [1] introduced a check throwing an error if S3_DATA_SIZE isn't big enough. However without CONFIG_HAVE_ACPI_RESUME the variable S3_DATA_SIZE isn't defined at all and compilation will fail if s3_resume.h is included. This patch makes it again possible turn off HAVE_ACPI_RESUME relatively easily in Parmer/Thatcher/Persimmon's Kconfig if you don't care about S3 and don't want flash writes on every boot. [1] http://review.coreboot.org/2383 Change-Id: I999e4b7634bf172d8380fd14cba6f7f03468fee3 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/2528 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-26AMD Fam14 boards: reduce unnecessary differences, 2nd attemptJens Rottmann
This patch reduces unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1. It's only cosmetical, but makes them a little bit easier to compare. This is the remainder of the original http://review.coreboot.org/2464, parts of which somehow got lost in a flurry of refactoring and splitting patches. Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-26Revert "AMD S3: Program the flash in a bigger data packet"Dave Frodin
This reverts commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b. The packet size changes ends up corrupting the flash when booting Persimmon. I did figure out that the maximum number of bytes that can be sent is actually 8 bytes according to the sb800 spec. There must be additional problems beyond that since setting the packet size to 8 still causes problems. Change-Id: Ieb24247cf79e95bb0e548c83601dfddffbf6be59 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2509 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2013-02-25AMD Southbridge: Add RTC init to lpc_initMike Loptien
Adding RTC init code to the Southbridge initialization code in 'lpc_init'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same edit made to the CIMX SB800 titled 'AMD/Persimmon: Add RTC init to CIMX SB800' with commit ID: c4d3d which can be viewed here: http://review.coreboot.org/#/c/2488/ Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2510 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25Supermicro H8SCM & H8QGI: Fix printk warningsMartin Roth
Changes: - Fix printk warnings for these two platforms by getting rid of the l length specifier and casting to unsigned int. This gets rid of a bunch of warnings like this one: agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Notes: - This is the same change that was done for Tyan s8226 in change: ddff32eb - http://review.coreboot.org/#/c/2451/ Tyan S8226: Fix printk warnings - I have not tested this change on either of these platforms, I have just compiled it. Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Southstation: Fix final warningMartin Roth
Changes: - Add #include of delay.h in mainboard.c to pick up declaration of mdelay function. Notes: - This fixes this warning: mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal implicit declaration of function 'mdelay' [-Wimplicit-function-declaration] Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2501 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Fam14 boards: Set P_BLK length to 6 for all processorsPaul Menzel
Currently on for example on AMD Persimmon and ASRock E350M1 Linux complains, that the PBLK length is invalid [1]. ACPI: Invalid PBLK length [0] Consequently, frequency scaling might not work correctly, though for these two boards it seems to work according to PowerTOP. Indeed, according to the ACPI specification [2], setting PBlockLength to 0 is only allowed if there is no PBlockAddress. Otherwise it has to be set to 6. 18.5.93 Processor (Declare Processor) […] PBlockAddress provides the system I/O address for the processors register block. Each processor can supply a different such address. PBlockLength is the length of the processor register block, in bytes and is either 0 (for no P_BLK) or 6. With one exception, all processors are required to have the same PBlockLength. The exception is that the boot processor can have a non-zero PBlockLength when all other processors have a zero PBlockLength. It is valid for every processor to have a PBlockLength of 0. And that is exactly what Linux is checking in `drivers/acpi/processor_driver.c` [3]. static int acpi_processor_get_info(struct acpi_device *device) { […] /* * On some boxes several processors use the same processor bus id. * But they are located in different scope. For example: * \_SB.SCK0.CPU0 * \_SB.SCK1.CPU0 * Rename the processor device bus id. And the new bus id will be * generated as the following format: * CPU+CPU ID. */ sprintf(acpi_device_bid(device), "CPU%X", pr->id); ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, pr->acpi_id)); if (!object.processor.pblk_address) ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n")); else if (object.processor.pblk_length != 6) printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n", object.processor.pblk_length); else { pr->throttling.address = object.processor.pblk_address; pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset; pr->throttling.duty_width = acpi_gbl_FADT.duty_width; pr->pblk = object.processor.pblk_address; /* * We don't care about error returns - we just try to mark * these reserved so that nobody else is confused into thinking * that this region might be unused.. * * (In particular, allocating the IO range for Cardbus) */ request_region(pr->throttling.address, 6, "ACPI CPU throttle"); } […] } This issue has proliferated to all AMD based boards so fix it for all of them by setting P_BLK length to 6. The DSDT of for example AMD Parmer and AMD Thatcher also set it to 6 everywhere so this solution is taken instead of setting the P_BLK system I/O base to 0 for all but the first processor which is how it is done for earlier AMD based boards. As note having to set this manually should not be needed and this should be autogenerated as done for most of the Intel boards and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`). [1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html [2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf [3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/acpi/processor_driver.c;h=e83311bf1ebdaaaea1adbf2de1351cca907d3465;hb=5da1f88b8b727dc3a66c52d4513e871be6d43d19#l351 Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> • ASRock E350M1: Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> • AMD Persimmon: Tested-by: Martin Roth <martin.roth@se-eng.com> Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2189 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-25Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) doesJens Rottmann
USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1 simply does not exist, so remove it from devicetree.cb. While at it make the comment more detailed. Likewise for all USB ports. USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1. Add it to devicetree.cb. It's used on Inagua (on), but not on Persimmon (off). Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID fieldPaul Menzel
The DSDT header contains the fields OEMID and OEM Table ID. See for example ACPI specification 4.0a [1] 5.2.11.1 Differentiated System Description Table (DSDT) on page 135. There Table 5-16 contains the descriptions. Field Byte Length Byte Offset Description =================================================== OEMID 6 10 OEM ID OEM Table ID 8 16 The manufacture model ID. Currently in coreboot there is no common method what to put in these fields. Mostly Intel based boards populate it with "CORE " ore "COREv4" and AMD based boards populate it with the board vendor and model number, abbreviated appropriately to fit into these fields. On most boards the proprietary vendor BIOS seems to leave these fields – displayed with `sudo dmidecode` under System Information – blank To Be Filled By O.E.M. and fill out the Base Board Information with the board vendor and model name. In [2] Jens Rottmann argues that the this is really just the table ID used for naming it and that »99% of the DSDT code is not board specific«. Both approaches seem to have their advantages, but using the second one, developers often seem to forget to update them (for example AMD Thather). The current situation is at least not optimal. and therefore at least unify the string in the OEM Table ID. If unifying the OEM ID is also a good idea this should be done too. If later on it should be decided that the board vendor and model should be used again, this should be somehow derived from Kconfig. The following command was used for the change [3]. $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/' This patch is split out from [2]. [1] http://www.acpi.info/spec40a.htm [2] http://review.coreboot.org/#/c/2464/ [3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2472 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25google/snow: enable GPIO entries and CHROMEOS in buildingRonald G. Minnich
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25QEMU x86: northbridge.c: Name enabling device function to `northbridge_enable`Paul Menzel
Similar to the discussion on the coreboot list [1] Am Freitag, den 22.02.2013, 02:17 +0100 schrieb Peter Stuge: […] > Function names should try to be descriptive. "enable_dev" is not very > descriptive. I like "mainboard_enable" because it makes output such > as > > printk("%s: foo", __func__); > > useful. rename the function for the northbridge to `northbridge_enable`. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074549.html Change-Id: I262311ec511e394550330214621b8c37780c1d4e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2496 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25Persimmon: Fix warning, enable warnings as errorsMartin Roth
- Fix redefinition warning for SB_GPIO_REG50 introduced in commit fa8702cf - http://review.coreboot.org/#/c/2446/ Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon The warning being fixed is: SB800.h:1491, GNU Compiler 4 (gcc), Priority: Normal "SB_GPIO_REG50" redefined [enabled by default] - Enable warnings as errors so no more warnings will be accidentally committed. Change-Id: Ib443b2bd2067f0b7d5f93f79170899a0f8f61060 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2494 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25mainboard.c: Name enable_dev function uniformly `mainboard_enable`Paul Menzel
To reduce the differences between these file name the enabling device function in the directory `src/mainboard` uniformly `mainboard_enable` [1]. Thanks to the awesome help of gnomon and BlastHardcheese in the IRC channel #sed on <irc.freenode.net>. gnomon came up with the following command to do the actual work. $ cd src/mainboard $ for f in */*/mainboard.c ; \ > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \ > [[ -z $src ]] && continue ; \ > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \ > done `src/mainboard/digitallogic/msm586seg/mainboard.c` and `src/mainboard/technologic/ts5300/mainboard.c` had to be adapted manually as no comma was used separating the struct members. And with the following statement, gnomon is even more likable! My pleasure entirely. Good luck with coreboot; I'm a big fan of the project. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2493 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25Technologic TS5300: mainboard.c: Move { to next linePaul Menzel
This is coreboot’s coding style. Change-Id: I7441f2c1927a49a3b7171112b7798dae6b56cfb5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2492 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25ARMv7: Simplify div64Stefan Reinauer
We don't need the overly complex optimized version, since we're only doing this in very few non-critical places. Also, add the div* files to the bootblock, they're needed if we do printk. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I83bd766d4b03b488326ade1c13b7c364a7119e7b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2508 Tested-by: build bot (Jenkins)
2013-02-24Siemens SITEMP G1P1: mainboard.c: Rename `init` to `mainboard_init`Paul Menzel
This is the common way to name that function, so unify that. Change-Id: I8a01051bd304039662894b89eed53ce14dde98b6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-24AMD f14 vendorcode: Fix warningMartin Roth
Add brackets around initializer in #define for PCIE_DDI_DATA_INITIALIZER to fix the warning: PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal missing braces around initializer [-Wmissing-braces] This warning happens for Inagua and South Station Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2495 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-23Add support for Google's Chromebook PixelStefan Reinauer
Ladies and gentlemen, I'm very happy to announce coreboot support for the latest and greatest Google Chromebook: The Chromebook Pixel. See the link below for more information on the Chromebook Pixel, and its exciting specs: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel The device is running coreboot and open source firmware on the EC (see ChromeEC commit for more information on that exciting topic) Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2482 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-23AMD based boards: platform_cfg.h: Replace `_*BOARDNAME*_CFG_H_` with ↵Jens Rottmann
`_PLATFORM_CFG_H_` Reduce unnecessary differences between AMD based boards only using the file `platform_cfg.h` for configuration making them a little bit easier to compare. Inagua & co. mention the board name in several places which are really not that board specific. Sometimes people even forget to change it: Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_". Funny. Change that to "_PLATFORM_CFG_H_" everywhere. The following command was used. $ find . -name platform_cfg.h | xargs sed -i '/_CFG_H_/s/_.*_/_PLATFORM_CFG_H_/' More boards seem to use that kind of naming (`git grep _CFG_H_`) but it is not certain that this will not break anything as for example the board AMD Dinar also has header files for configuration stuff for the north- and southbridge. $ git grep _CFG_H_ […] src/mainboard/amd/dinar/platform_cfg.h:#ifndef _PLATFORM_CFG_H_ src/mainboard/amd/dinar/platform_cfg.h:#define _PLATFORM_CFG_H_ src/mainboard/amd/dinar/platform_cfg.h:#endif //_PLATFORM_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#ifndef _RD890_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#define _RD890_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#endif //_RD890_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#ifndef _SB700_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#define _SB700_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#endif //_SB700_CFG_H […] Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2464 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-23AMD/Persimmon: Add RTC init to CIMX SB800Mike Loptien
Adding RTC init code to the Southbridge initialization code in 'late.c'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This was tested on a Persimmon but will apply to other mainboards as well. Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2488 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-22Add support for Google ChromeECStefan Reinauer
Google ChromeEC is an EC with completely open source firmware. See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary for the EC firmware source code (aka more information about the ChromeEC) This patch adds support for the ChromeEC on coreboot's side. Great thanks to the ChromeEC team for this amazing work. It's another important milestone towards a free and open firmware stack on modern hardware. Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-22*/acpi_tables.c: Use ALIGN macroPatrick Georgi
At the request of Paul Menzel, I reran an old classic of a coccinelle script: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-22libcbfs: Fix legacy CBFS API, typosHung-Te Lin
Pulling CBFS fix from libpayload: http://review.coreboot.org/#/c/2455/2 get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff) instead of NULL when something is wrong. Also, fix typo. Change-Id: I7f393f7c24f74a3358f7339a3095b0d845bdc02d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2457 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-21AMD Fam14 boards: Unify `acpi_table.c` by mainly using Inagua’s onePaul Menzel
There were just whitespace differences and three boards did not contain printk(BIOS_DEBUG, "alib\n"); dump_mem(ssdt, ((void *)alib) + alib->length); which is enclosed `#if DUMP_ACPI_TABLES == 1` to dump the ACPI tables. Basically the whitespace in the license header in Inagua’s file was fixed and then the file copied over to the other directories. Change-Id: I23f73acad427b5ec14cf51651af67240871f7488 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2470 Tested-by: build bot (Jenkins) Reviewed-by: Alvaro G. <andor@pierdelacabeza.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21AMD boards: Fix typo `@brief` in commentPaul Menzel
The following command was used to correct the typo. $ git grep -l @breif | xargs sed -i 's/@breif/@brief/' Change-Id: If0b579279de3c41571b9cda643836f5748a752a2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21Persimmon: platform_cfg.h: Declare codec arrays as `static const`Jens Rottmann
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2474 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21Persimmon: dimmSpd.c: Use spaces for alignment of if-predicatePaul Menzel
The relational operators in the if-predicate are aligned in all `dimmSpd.c` files so revert part of the change in commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303@gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 to remove the incorrectly introduced tabs and to unify that. It might contradict the current coding style but it is even used in the latest code as seen in the following file. src/northbridge/amd/agesa/family15tn/dimmSpd.c Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2471 Reviewed-by: Alvaro G. <andor@pierdelacabeza.com> Tested-by: build bot (Jenkins)
2013-02-21Persimmon: Indent commentPaul Menzel
This was overlooked in the following commit. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303@gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2468 Tested-by: build bot (Jenkins) Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
2013-02-21AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead ↵Jens Rottmann
of `0xB00` For AMD Inagua, the following two commits commit 01f7ab93359ae0fee5784d35effbcbe0b596df18 Author: Kerry Sheh <shekairui@gmail.com> Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: Synchronize AMD/inagua mainboard. Reviewed-on: http://review.coreboot.org/542 and commit d91c9b7e3cb9fdaeb9399a21907996130f3120bb Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 10:59:55 2011 -0600 AMD Inagua platform updates Reviewed-on: http://review.coreboot.org/136 replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`. Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1. Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2453 Tested-by: build bot (Jenkins)
2013-02-21AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'Zheng Bao
Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-21ARMV7: create a correct LB_SERIAL table entryRonald G. Minnich
If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2466 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20Persimmon: Replace tab with space in address in license headerPaul Menzel
The following commit was too eager replacing spaces with tabs. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303@gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Fix that with the following command. $ git grep -l 'Floor, Boston, MA'$'\t''02110-1301 USA' | xargs sed -i 's/Boston, MA[ ]*02110-1301 USA/Boston, MA 02110-1301 USA/' Change-Id: Ia118a8c19d94ce1f1048280a0f1d49d447cfa2a7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2461 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20armv7: Don't let users set ram parameters that are fixed in hardware.Ronald G. Minnich
The SDRAM base is fixed in hardware. It makes no sense to make it configurable. The TEXT start is a magic number that should also be fixed, not settable. Change-Id: Ie44cc5c8da1dc38fc00eb602c4a295b045ca5364 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2465 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-20ARMV7: minor tweaks to inter-stage calling and payload handling.Ronald G. Minnich
Payloads, by design, can return. There's lots of mechanism in the payload code to support it, and the chooser payload relies on it. Hence, we should not mark the function call in exit_stage as noreturn. Not all ARM have unified caches, and it's not always easy to tell what to do. So we are very paranoid. Before we call between stages, we should carefully flush the dcache to memory and invalidate the icache. This may be more than is necessary on all architectures but it doesn't really hurt for the most part. So compile cache management code into all stages, and call the flush dcache/invalidate icache from all stages. Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19Tyan S8226: Fix incompatible pointer warningMartin Roth
Fix warning: mptable.c:52, GNU Compiler 4 (gcc), Priority: Normal passing argument 3 of 'mptable_write_buses' from incompatible pointer type [enabled by default] mptable_write_buses is expecting a pointer to an int, so I changed the U8 isa_bus to an int to match. A U8 doesn't make sense if the value could be greater than 255 - certainly unlikely, but possible since the value of isa_bus gets set to the maximum PCI bus number + 1. Change-Id: I7ea416f48285922d6cf341382109993fd3f6405c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2450 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19Tyan S8226: Fix integer truncated warningMartin Roth
Fix Warning: sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal large integer implicitly truncated to unsigned type [-Woverflow] The issue here was that an 8 bit value was being placed into a 2-bit bitfield. $ more src/vendorcode/amd/cimx/sb700/SBTYPE.h […] UINT32 AzaliaSdin0 :2; //6 UINT32 AzaliaSdin1 :2; //8 UINT32 AzaliaSdin2 :2; //10 UINT32 AzaliaSdin3 :2; //12 $ more src/mainboard/tyan/s8226/sb700_cfg.h […] * SDIN0 is define at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin * SDIN1 is define at BIT2 & BIT3 * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN 0x2A #endif […] $ more src/mainboard/tyan/s8226/sb700_cfg.c […] sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; […] The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly – I believe the original intent of this value was to enable the SDIN pins 0, 1, & 2. Because it was getting truncated as it was put into AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled. I am leaving only SDIN0 enabled at this point to as not change the actual behavior on the platform. Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2452 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19Tyan S8226: Fix printk warningsMartin Roth
Fix 84 warnings all like this one: agesawrapper.c:289, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Fixed by getting rid of the l length specifier and casting to unsigned int. Change-Id: Ic143c1034f760fa5efb2220aa33861e399ddd708 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2451 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-19Inagua+children: fix simple copy & paste error in code to reset PCIe slotsJens Rottmann
Looking at AssertSlotReset, the comments and all other case's it's obvious this is a simple copy & paste error where someone just forgot to change one occurrance of the GPIO nr. Also the AMD Inagua schematics show that GPIO02 is what they really meant. Also forward the fix to boards copied from Inagua (AMD South Station, Union Station, Asrock E350M1). Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2445 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-19exynos5250: add uartmem_getbaseaddr() in uart driverDavid Hendricks
Change-Id: I76545ad3fca3cc0997050253be77ea83b5d74cb2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2423 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19move uartmem_getbaseaddr() to generic uart headerDavid Hendricks
This moves uartmem_getbaseaddr() from an 8250-specific header to the generic uart header. This is to accomodate non-8250 memory-mapped UARTs. Change-Id: Id25e7dab12b33bdd928f2aa4611d720aa79f3dee Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19armv7/snow: add CPU and RAM resources via allocatorDavid Hendricks
This adds necessary device operations to add CPU and RAM resources. Change-Id: Ief8f66627ef37f4fa786bfc3f7899529d3e5b037 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2419 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19snow: add cpu_cluster and domain resources via devicetree.cbDavid Hendricks
This patch will cause the resource allocator to actually set aside the memory resources using methods in the previous patch. The coreboot table output will include "RAM" entries (there were none before): coreboot memory table: 0. 0000000040400000-00000000bff001ff: RAM 1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES 2. 00000000bff01000-00000000bfffffff: RAM Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2420 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-19build system: Retire REQUIRES_BLOBPatrick Georgi
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19AMD S3: Change S3_VOLATILE_POS to S3_DATA_POSZheng Bao
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19RTC: Use the correct index when setting the default monthDave Frodin
Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2442 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 07:22:09 +0000