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2018-07-30sb/intel/bd82x6x/finalize: Use new PMBASE APIPatrick Rudolph
Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/parrot/smihandler: Use new PMBASE APIPatrick Rudolph
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFFRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mb/google/poppy/variants/atlas: Add new Nanya memory optionTim Chen
- add Nanya NT6CL256T32CM-H1 to memory strapping table BUG=b:111906760 BRANCH=none TEST=none Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30mainboard/google/nocturne: simplify camera power referencesMatt Delco
This change primarily moves the PowerResource up to a more common scope so that the _PRx references are simpler. The ^ scope modifier isn't well supported everywhere amongst OSes and drivers. Windows 10 will BSOD early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could not find the object referenced by a _PRx) with the way things are currently laid out). I've also not seen a firmware outside of coreboot that tries to reference count _ON and _OFF. Isn't it up to the OS to deference count, and whatever it tells ACPI is what should happen (i.e., on means on and off means off)? Some of the _UIDs are also duplicated. This change makes them unique. A few cosmetic changes are made so that diffing cam0.asl against cam1.asl has fewer extraneous differences. Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30google/caroline: Change debounce time for jack insertion and ejectionMatt DeVillier
Adapted from chromium commit 7633daa [caroline: Change debounce time for jack insertion and ejection] We are using max debounce time. During this time line, MICBIAS will be zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE) We need to reduce this time to below 100ms for caroline device. BUG=b:79559096 TEST=see there is no more irq before jack insertion/ejection irq complete Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1143109 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com> Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27659 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30google/kukui: Enable eMMC in bootblock.Hung-Te Lin
On kukui board, the eMMC is routed to EC for boot ROM emulation when loading bootblock, and should be set back to real eMMC as early as possible after bootblock is loaded. BUG=b:80501386 TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled. BRANCH=None Change-Id: Ifefb2e26ed048c38595907cc0875757410129828 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30cpu/intel/microcode: Add helper functions to get microcode infoRizwan Qureshi
Add 4 helper functions to get microcode info. * get_current_microcode_rev return the the version of the currently running microcode. * get_microcode_rev extract microcode revision from the given patch. * get_microcode_size extract microcode size from the given patch. * get_microcode_checksum extract checksum from the given patch. The simpler thing would be to just move the struct microcode to microcode.h so that the structure members can be dereferenced. To encapsulate the structure details added the helper functions. This information will be used in future to compare microcodes for update. Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27365 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30soc/intel/common: Add support to configure top swap featureAamir Bohra
RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30mb/google/poppy/variants/nocturne: enable FPMCU powerNick Vaccaro
Enable power to FPMCU by default on power-on and deassert the PCH_FPMCU_RST_ODL reset line. BUG=b:111880258 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel prompt, wait a few seconds, press power button to wake, then execute "cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes up empty. Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable ec host event wakeNick Vaccaro
Enable nocturne to wake from lid attach/detach events. BUG=b:111803637 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne wakes from suspend on a lid attach/detach event. Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27649 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/nautilus: Remove obsolete fieldsAlan Chiang
Some fields were only required during early stages of IPU3. Remove some fields that aren't used for the current version of IPU3. BUG:None TEST=Launch camera app and check if it works properly. Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d Signed-off-by: Alan Chiang <alanx.chiang@intel.com> Reviewed-on: https://review.coreboot.org/27617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30mb/cavium/cn8100_sff_evb: Compile devicetree for LinuxPatrick Rudolph
Compile the linux devicetree using dtc and add it to CBFS. Change-Id: I8a98ed7b128f65a6e0109963dbabca91563a315c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/bootblock: Get rid of register X1Patrick Rudolph
The register X1 isn't used. Document it and remove it. Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30mb/google/octopusi/variants/bip: Fix unused pins and those with external ↵Furquan Shaikh
terminations For unused pins, configure them as GPIO input and use the default termination. For the pins where board has an external termination, remove SOC's internal termintation. BUG=b:110654510 TEST=On Bip, flashed image and verified that it boots to OS. Also executed a few suspend resume cycles. Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/27634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30drivers/i2c/da7219: Allow disabling micbias-pulse featureDaniel Kurtz
These two da7219_aad properties are optional: - dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV). [<2800>, <2900>] - dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms) When the Mic Bias Higher Voltage feature is not required, firmware should just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time properties. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:111700809 TEST=On grunt: No "Invalid micbias pulse level" in dmesg Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9 Reviewed-on: https://review.coreboot.org/27613 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30security/tpm: Use unique CBMEM names for TCPA logsPhilipp Deppenwiese
Fix regression introduced in commit f18dc5c7 "Add TCPA logging functionality": Introduced TCPA log got overwritten in acpi.c of x86/arch, due to CBMEM name collision. Use a different cbmem name to have two independent TCPA logs. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30security/vboot: Enable TCPA log extensionPhilipp Deppenwiese
* Implement TCPA log for tspi extend function. * Hook tcpa_log_init into vboot tpm_setup function. * Add TCPA log output for vboot GBB flags and HWID Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30soc/intel/fsp_baytrail: Add VBOOT supportPhilipp Deppenwiese
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
The newly added macros are used for cleaning up the RAM initializatiion code. Change-Id: I3d3782ee1fa524cf69b63ccc7eb73e9a2ace84ec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30northbridge/nehalem: clean up header fileFelix Held
* remove duplicate macro definitions * add brackets to macros Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mainboard/opencellular/rotundu: Add FMAP supportzaolin
* Add 8M and 16M fmap configurations. * Fix kconfig selects. * Add vboot options and fixes Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/25084 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nautilus: Set GPP_D21 to high as defaultSeunghwan Kim
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means LTE tx power is backoff mode as default. We would set GPP_D21 to high to change LTE tx power to normal mode as default. BUG=None BRANCH=poppy TEST=Verified default LTE tx power mode is normal mode as default Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nami: Fix fan is always ONJohn Su
Add the new setting for fan performance state. BUG=b:111860513, b:11865138 TEST=Fan do not run below trip point Change-Id: I894460b8b418217e2477608094c37018437cbb78 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-30mainboard/google/kahlee: Pad SPD serial Number with spacesMartin Roth
All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29pnp_device: don't treat missing PNP_MSC devicetree entry as errorFelix Held
Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29device/pnp_device: rewrite pnp_get_ioresourceFelix Held
The rewrite simplifies the code and fixes the limit on the case of IO resources with the length of 1 byte. This patch is inspired by the comment of Nico Huber on Ia99b785dcd9cf56fb236ad7ade54656851f88a5e If the ones in the mask aren't a continuous block, now a warning message gets printed. Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29soc/intel: Remove legacy static TPM asl codePhilipp Deppenwiese
Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27715 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27712 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29mb/google/octopus: Perform EC init before bootblock gpio configurationFurquan Shaikh
A variant might talk to the EC to get board id in order to identify the right GPIO configuration. Thus it is important to ensure that the LPC IO windows are configured before this. This change moves the call to perform EC init before configuring bootblock GPIOs. BUG=b:111933657 TEST=Verified that reading board id does not fail on phaser. Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27671 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28mainboard/opencellular/rotundu: Enable TPM 1.2 supportPhilipp Deppenwiese
* Enable support for all variants. Change-Id: Ibdd43d8cff23d3fa1154e2b72aa6095682783fe5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28mainboard/opencellular/rotundu: Add supabrck EMMC supportPhilipp Deppenwiese
Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28sb/intel/bd82x6x: Fix watchdogPatrick Rudolph
* Fix comments * Use defines instead of magic values * Use new PMBASE API to modify registers Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28opencellular/rotundu: Introduce variants for OCPhilipp Deppenwiese
* Add Supabrck v1 variant * Modify rotundu base board Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28util/cbmem: Add cbmem TCPA log supportPhilipp Deppenwiese
* Read and print the TCPA ACPI log. Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/26244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28security/tpm: Add TCPA logging functionalityPhilipp Deppenwiese
* TCG spec only applies to BIOS or UEFI. * Therefore implement coreboot TCPA compliant log in CBMEM. * Write CBMEM log into the coreboot table for CBMEM tool access Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
* Add a function to return CPU platform ID bits * Add a function to return platform type ** Platform id is 4 on Lenovo T430 (mobile) ** Platform id is 1 on HP8200 (desktop) * Use introduced method to handle platform specific code * Use enum for platform type * Report platform ID Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28sb/intel/gpio: Cache gpiobase in ramstage and romstagePatrick Rudolph
Implement caching like it's done with pmbase. Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27664 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC errorKevin Chiu
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking: ERROR Event: 04011200 Data: 0, 0, 0, 0 BUG=b:111901461 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27657 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27soc/amd/stoneyridge: Add IGFX device ACPI ASL entryMarc Jones
Add internal graphics device 00.01.00 to the ACPI tables so that the ACPI PCI option ROM save functions have a proper scope to save the ROM to. BUG=b:111697181 TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope" and check _ROM method is added in the SSDT1. Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-27chromeec: Read EC uptime info on bootJonathan Brandmeyer
Additional diagnostic information about the EC and the most recent reasons why it has reset the AP are read out and logged via printk. This may aid in debugging spurious hangs and/or resets on the AP by providing traceability to the EC when it triggered the reset. Merely knowing that the EC was also recently reset may provide valuable intelligence. See also https://crrev.com/c/1139028. Change-Id: Ie6abe645d5acefb570b9f6a3c4a4b60d5bcd63cd Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27621 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27chromeec: Sync ec_commands.h with CrOS upstreamJonathan Brandmeyer
Update ec_commands.h to be a verbatim copy of upstream, except retain the complete copyright notice found in coreboot's copy. Upstream refers to a file not present in coreboot. Change-Id: Ic3daa09ffd83c089b6874e0ea9aab8aa60016775 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-27sb/intel/common/pmutil: Use new PMBASE APIPatrick Rudolph
Change-Id: I0f37f0c49fd58adafd8a508e806e0f30759a6963 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27287 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27sb/intel/common/smi*: Use new PMBASE APIPatrick Rudolph
Use new PMBASE API functions in common SMI handler. Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-27sb/intel/common: Add functions to manipulate PMBASEPatrick Rudolph
Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27mb/lenovo/*/devicetree: Add support for WWAN detectionPatrick Rudolph
Add support for WWAN detection on SNB/IVB boards that have schematics or are available for testing. Tested on Lenovo T430. Change-Id: Ie96b2593971d49703eb747ab19f512be890d9c12 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20984 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27google/kukui: Add SPI NOR supportTristan Shieh
This patch sets SPI flash related configs and inits SPI bus 1 to support SPI NOR flash. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek/mt8183: Add SPI supportmengqi.zhang
This patch implements SOC-specific code of mt8183 and link the common code to support SPI bus. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Signed-off-by: mengqi.zhang <mengqi.zhang@mediatek.com> Change-Id: I544e850299c74861313c2425721479fe5b91639e Reviewed-on: https://review.coreboot.org/27498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek: Refactor SPI code among similar SOCsTristan Shieh
Refactor SPI code which will be reused amon similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: If5a6c554dc8361e729cf5c464325b97b2bfb7098 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek/mt8183: Remove unused MMU stuff from bootblockTristan Shieh
Since we move mtk_mmu_init() from bootblock to decompressor, we don't need to build mmu_opertations.c in bootblock and we don't need to include <soc/mmu_operations.h> in bootblock.c. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I58f97ac1705e4dfde5e2d497d9bec33a1d8d17c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-07-26ec/roda: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: Ic35a232a9867936d3d84aa275ae50e3e3dd9bf97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27396 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26ec/quanta: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: I59eb60efeefcdbe8b2dc08e17453cf95bdfd39b1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27395 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26ec/compal: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: I10e2c6da0043eb291a8c6266b251054dbe599653 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27393 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26google/caroline: Add missing audio codec infoMatt DeVillier
Add audio codec definitions in devicetree, which were accidentally dropped when upstreaming Test: build/boot Caroline with GalliumOS 3.0a2, verify working audio. Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27626 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26google/caroline: Fix I2C2 ACPI device definitionMatt DeVillier
Remove duplicate FMCN package for I2C2, since already generated by the devicetree-linked generic i2c driver. This fixes an ACPI parsing error which resulted in the touchpad and touchscreen being non-functional. Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad and touchscreen functioning properly, no ACPI errors in dmesg. Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26mb/google/octopus/variants/phaser: Provide override GPIO configFurquan Shaikh
This change provides override GPIO table for variant phaser depending upon the board id. Additionally, early_gpio_table is also provided for phaser since EN_PP3300_WLAN needs to be handled differently based on board id. BUG=b:111743717 TEST=Verified that GPIO configuration for the override GPIOs is different than before with this change. Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-26mb/google/octopus: Use newly added gpio_configure_pads_with_overrideFurquan Shaikh
This change updates mainboard_init to call gpio_configure_pads_with_override instead of gpio_configure_pads to allow variants to provide overrides for the GPIO config table provided by the baseboard. BUG=b:111743717 TEST=Verified on phaser that GPIO config with and without this change is the same. Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_overrideFurquan Shaikh
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. This is done to allow sharing of GPIO tables across baseboard-variants for various boards i.e. Each board can have a base config table which is provided by the baseboard and an optional override config table that can be provided by a variant to configure certain GPIOs differently. It is helpful when the variant GPIO diff list is not very huge compared to the baseboard. BUG=b:111743717 TEST=Verified that the GPIO config for phaser is same with and without this change. Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mb/google/octopus: update phaser touchscreen enable gpioAaron Durbin
The next build for phaser swapped the gpio for the touchscreen enable. In order to support previous builds the devicetree needs to be updated at runtime based on board revision id. BUG=b:111808427,b:111743717 TEST=built Change-Id: I45ef05ea0b991d04d5bf410cd7a175913bf0bf5d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27638 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mb/google/octopus: add variant devicetree update callbackAaron Durbin
The variants of the octopus family have their own schedule and needs for modifying settings based on the phase of the build schedule while also needing to maintain support for previous builds. Therefore, utilize the SoC callback, mainboard_devtree_update(), but just callback into the newly introduced variant_update_devtree(). The indirection allows for the ability to move the call around earlier than the mainboard_devtree_update() if needed while maintaining consistency in the naming of the variant API. BUG=b:111808427,b:111743717 TEST=built Change-Id: If1c2f60cabe65b5f1c6a04dd60e056e50c4993df Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-26device: add child traversal helper functionAaron Durbin
Add a function, dev_bus_each_child(), which walks through all the children for a given bus of a device. This helper allows one to walk through all the children of a given device's bus. BUG=b:111808427,b:111743717 TEST=built Change-Id: Iedceb0d19c05b7abd5a48f8dc30f85461bef5ec6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-26mb/google/octopus: remove unused variant_board_id()Aaron Durbin
The variant_board_id() API was never used on octopus because all boards in the octopus family used the EC to get board id, i.e. they all use EC_GOOGLE_CHROMEEC_BOARDID. Therefore, remove the code and declarations so as not to cause confusion. BUG=b:111808427,b:111743717 TEST=built Change-Id: I4f9a24b46dd4262120075d3d42daf22015a3dd50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops structFelix Held
This patch makes it possible to enter the config mode of the super IO chip, so that changes can be made to the configuration registers. Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2018-07-26ec/google: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: Id09c6cffb9a0cbbd9189c18801121449c9504422 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27394 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph
The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph
On desktop boards the PPD bit of MRS register MR0 is set and thus DLL_Off mode shouldn't be used, as enforced by datasheet 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1. Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26asrock/g41c-gs: make serial console setup depend on selected super IOFelix Held
The used super IO is selected in Kconfig depending on the board variant, so use the selected super IO instead of the board variant directly. Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26nb/intel/nehalem: Remove the C native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-26mb/packardbell/ms2290: Allow use of libgfxinitArthur Heymans
Untested but expected to work. Change-Id: I5a77b7a4343f108f46cf1f97a94e61e88eecb417 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27514 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mediatek/mt8183: Enable bootblock self-decompressionHung-Te Lin
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. A fully functional bootblock (that can boot into verstage or romstage) is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK) is enabled, only 25088 (66%) bytes are needed. Inspired from crosreview.com/1070018. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-26nocturne: configure VR per Intel recommendationPratik Prajapati
These values are Intel recommended. IccMax = 28A DC and AC LL = 4mOhms Pl2 = 18w BUG=b:79666828 BRANCH=none TEST=Enabled p-states with patch Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then "emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi image onto nocturne, boot to kernel and verify device stays alive and responsive for several minutes without locking up. Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27175 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mb/google/poppy/variants/nocturne: enable p-statesPratik Prajapati
This patch enables p-states for nocturne which was disabled by commit de31587a (mb/google/poppy/variants/nocturne: disable p-states). p-states feature was disabled as a temporary work-around as system was getting hung while booting up. Now with IMVP7 firmwware turning and hardware rework the issue is not seen, so its safe to enable p-states. BUG=b:79666828 BRANCH=none TEST=cherry picked Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d patch and then "emerge-nocturne depthcharge coreboot chromeos-bootimage" , flash spi image onto nocturne, boot to kernel and verify device stays alive and responsive for several minutes without locking up. Change-Id: I82d1516998cc26b789faa5d4e897feb06dc06020 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27257 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26arch/arm64: Add Kconfig to include BL31 as blobPatrick Rudolph
Add Kconfig options to not build the Arm Trusted Firmware, but use a precompiled binary instead. To be used on platforms that do not have upstream Arm Trusted Firmware support and useful for development purposes. It is recommended to use upstream Arm Trusted Firmware where possible. Change-Id: I17954247029df627a3f4db8b73993bd549e55967 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-25mb/google/octopus: Fix unused pins and those with external terminationsFurquan Shaikh
For unused pins in octopus baseboard, configure them as GPIO input and use the default termination. For the pins where board has an external termination, remove SOC's internal termintation. BUG=b:110654510 Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/27183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25soc/intel/apollolake: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from APL and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works as expected on octopus. Change-Id: I86259465c6cfaf579dd7dc3560b4c9e676b80b55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25mb/google/x86-boards: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from all google mainboards and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works correctly on nautilus. Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5John Zhao
Update FSP header files to match FSP Reference Code Release v2.0.5 for Geminilake BUG=b:111683980 CQ-DEPEND=CL:*653835 Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph
Change-Id: I3f0869dc0b72bef7da8313c69da4fe2a63761ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27633 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph
Set tREFIx9 to 8.9*tREFI/1024 as suggested in xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1. Use the minimum value of REFI*8.9 and tRASmax as suggested by 3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9. Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25superio/winbond: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/via: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/renesas: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I42469c844074db57071d0191d12d8fd64f462672 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/intel: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I5bd525532c01b3b9f7ddbc8eab42caa8b7f30795 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/fintek: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: Ic6387032e043b6ad9e9ceefd2fcc1cdf843e2989 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-24mb/google/poppy/variant/nami: Add custom VBT for panel T8/T10T.H. Lin
Fix VBT SSF setting for panel T8/T10 as Akali/Akali360 panel has T8 minimum 33.3 ms and T10 minimum of 100 ms. BUG=b:111530392 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test & measure T8/T10 waveform Change-Id: I642a1aa0b2d13b33e6113f94e73dfc77834766d4 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-24cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-24google/glados: use level trigger for touchpad interruptMatt DeVillier
Coolstar's custom touchpad drivers for Windows require level triggering, and the Linux drivers don't care/perform identically either way. Set touchpad interrupt to level trigger, matching change made to other Chromebooks. Test: boot Windows 10 on google/chell, verify touchpad functional Change-Id: Id5f145b8b24c04f9c6661710a0cda95f135293e9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24google/glados: enable VMX for all variantsMatt DeVillier
Explicitly enable VMX, as some OSes (eg, Windows) need VMX feature enabled and locked in order to fully support virtualization Test: boot Windows 10 on google/chell, verify OS reports virtualization enabled Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24google/asuka: Add as a variant of gladosMatt DeVillier
Add google/asuka (Dell Chromebook 13 3380) as a variant of glados Skylake reference board: - add asuka-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/asuka, verify correct functionality Change-Id: I591578fea2514a28c75177835807c3f250904577 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27421 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24google/cave: Add as a variant of gladosMatt DeVillier
Add google/cave (Asus Chromebook Flip C302SA) as a variant of glados Skylake reference board: - add cave-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/cave, verify correct functionality Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24google/caroline: Add as a variant of gladosMatt DeVillier
Add google/caroline (Samsung Chromebook Pro) as a variant of glados Skylake reference board: - add caroline-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add caroline-specific memory-init param to romstage - adjust mainboard EC SCI events for boards with tablet function Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/caroline, verify correct functionality Change-Id: I611a4e76581ba2e5b42e1bc48b0a5b8c70f3598e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24google/sentry: Add as a variant of gladosMatt DeVillier
Add google/sentry (Lenovo Thinkpad 13 Chromebook) as a variant of glados Skylake reference board: - add sentry-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add sentry-specific GPIO determination of which audio codec is present Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/sentry, verify correct functionality Change-Id: I783422aedac8b7fc52098eebd05b2061a1011b60 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27418 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>