Age | Commit message (Collapse) | Author |
|
Having folders for bootblock and romstage is no longer necessary.
Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46794
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Instead of relying on mainboards to call it, do like Lynx Point.
Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It is identical for all Broadwell mainboards, thus deduplicate it.
Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46792
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Haswell Low Power variants do not have PEG at all.
Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46791
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change is just to align with Broadwell.
Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46790
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested with BUILD_TIMELESS=1, Google Wolf remains identical.
Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These are not used anywhere and are not present on Broadwell.
Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46788
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no need to perform manual shifting and masking when ACPI allows
one to painlessly describe bitfields of a register. The now-unused DVEN
definition will be dropped in a follow-up, alongside other definitions.
Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rename it to `hostbridge.asl`, which is what Haswell uses.
Change-Id: I6f97fc5c9459fe6b66dcfcf51900c751beda0ebe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46786
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These Function Disable definitions have been copied from Cougar Point,
are not used by any mainboard, and may be incorrect. So, remove them.
Change-Id: I36f732bce22ec33aab42beababe54c4d88e0205b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46784
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no need to dynamically differentiate between traditional and Low
Power platforms at runtime, and doing so makes code reuse more complex.
Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Commit 576b7c7 (broadwell: gpio.asl: Make GWAK method serialized) made
GWAK serialized for Broadwell. This commit follows suit on Lynx Point.
The reason to serialize this method is because it creates named objects
which depend on input parameters, and thus cannot be created elsewhere.
Change-Id: I892700df3bba079e3280008f619017e3954d5a06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46783
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same
GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some
unneeded logic from `_CRS` and declare the GPIOBASE resource statically.
The preprocessor allows later ACPI deduplication to remain reproducible.
Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order for ACPI deduplication to be reproducible, the `ISLP` method
needs to disappear. Replace the _PRW methods with a name and a macro.
Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46780
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is merely to ease diffing Lynx Point and Broadwell ASL code.
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46779
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use ASL 2.0 syntax where possible and uniformize code style to match the
IASL disassembly. Some `Store` in gpio.asl change the binary if touched.
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use ASL 2.0 syntax where possible and uniformize code style to match the
IASL disassembly. Some `Store` in gpio.asl change the binary if touched.
Also remove outdated comment and remove `LynxPoint` from `serialio.asl`.
Tested with BUILD_TIMELESS=1, Google Panther does not change.
Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46777
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ifc6dd5f6549e7501f350afe8456a9a8096edcc25
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ida1b1d05b39e67a9eba3bfaecca37f38821a438b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ib2f203b5f5eea5c25cfd4543f5ed9f15101b1735
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ic334816712370da63471135da8dd598ab02d54ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Iff00667377eecedcf0b83bcfc0bf50bd4c3411eb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I1773973f64bcc5ef6bd1856c5d8eb998bb6a4888
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I320198d56131cf54e0f73227479f69968719b2a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=emerge-dedede coreboot
Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Enable USB2 port 5 for user facing camera.
Enable USB2 port 6 for world facing camera.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Disable I2C port 3 for metaknight
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ic4a056d53a8c8abd04a9b786428da0986a255276
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add a helper function to print out debug info and add the MADT entry.
Change-Id: I1a00f87c6edef530c5352929ee9279782be4b112
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
The existing help text wasn't updated for Mandolin after it was copied
from an older reference board and contained some information that
doesn't apply to Mandolin.
Change-Id: Ib34abb2ee8b289df5f7085957042fe00ad506ca9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Change-Id: If8d3ebdb9a41330312c26fb5796c07de1b87b3eb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47480
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add CMOS layout and defaults files and enable CMOS options in Kconfig.
Test: changed loglevel setting, rebooted and checked the log.
Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46311
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TESTED ocp/deltalake still boots.
Change-Id: I69f336c1ff348b8e820340b84494929f2c58ce72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The defines for RX6110SA_SLAVE_ADR and RX6110SA_I2C_CONTROLLER are not
used anymore and can be deleted.
Change-Id: I3cddf7a9e2f757a22c729ae0f0ff767d55909b9c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
This patch adds basic ACPI support for the RTC so that the OS is able to
use this RTC via the ACPI interface.
If the Linux kernel is able to find the RTC in ACPI scope, you should
see the following lines in dmesg, where [n] is an enumerated number:
rx6110 i2c-RX6110SA:00: rtc core: registered RX6110SA:00 as rtc[n]
rtc rtc[n]: Update timer was detected
Change-Id: I9b319e3088e6511592075b055f8fa3e2aedaa209
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
It’s common to annotate the closing endif, so do it for these four
files.
Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
List of changes:
1. Add new PCH ID 0x5181 into device/pci_ids.h
2. Update new PCH ID into common lpc.c
3. Add new PCH ID description into report_platform.c
TEST=Able to build and boot ADLRVP with new PCH ID.
Change-Id: I4343b7343876eb40c2955f6f4dd99d6446852dc0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Work on this SoC was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.
Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change switches the selection of CAR mode so that
INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard
selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by
mainboards using older silicon (ES1 or ES2) that did not
support NEM enhanced mode.
This enables NEM Enhanced Mode for TGL-U/Y RVPs.
Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Introduce the `sir_unset_and_set_mask` helper and update the one PCI
read-modify-write operation that is somehow not reproducible.
Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Commit 8084b38568 (sb/intel/lynxpoint/sata: Always use AHCI mode)
dropped the devtree option, but missed this recently-added mainboard.
Change-Id: I6ab3a763c0bcd7431193c48e473639589b1a1e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
The Asus F2A85-M, F2A85-M LE and F2A85-M PRO all have a Super I/O, and
therefore have legacy devices like a serial console.
Selecting `HUDSON_LEGACY_FREE` currently disable the serial console
during bootup in romstage, which is undesired.
So, deselect the symbol by default.
TEST=Boot Asus F2A85-M PRO and verify serial console is *not* disabled
during romstage.
Change-Id: Ia6588c0d4b2c24c7cb9da04805d13274c8ae295e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47363
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support to check for the Power Management (PM) Status bit for
various internal devices like USB, CNVi etc. and log them into the event
log for debugging purposes.
BUG=b:172279037
BRANCH=volteer
Change-Id: Ib3d0bf33d780444f8240f749a3319212c985950d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add support to check for the Power Management (PM) Status bit for
various internal devices like USB, CNVi etc. and log them into the event
log for debugging purposes.
BUG=b:172279037
TEST=Build and boot to OS in Drawlat. Ensure that the wake up event is
logged into the event log for one of the internal devices eg. USB
bluetooth.
8 | 2020-11-05 15:04:16 | S0ix Enter
9 | 2020-11-05 15:04:29 | S0ix Exit
10 | 2020-11-05 15:04:29 | Wake Source | PME - XHCI (USB 2.0 port) | 8
11 | 2020-11-05 15:04:29 | Wake Source | GPE # | 109
12 | 2020-11-05 15:05:08 | S0ix Enter
13 | 2020-11-05 15:05:14 | S0ix Exit
14 | 2020-11-05 15:05:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8
15 | 2020-11-05 15:05:14 | Wake Source | GPE # | 109
Change-Id: I9f43675b698bf310f6b98b5e775d1259607abbcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47226
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It is too easy to confuse those with IA32_SMRR_PHYS_x registers.
Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Actual support CBnT will be added later on.
Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the shuboz variant of the zork reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172021093
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The code is based on autoport, with necessary modifications.
This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.
Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.
Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
CB:46865 ("mb, soc/intel: Reorganize CNVi device entries in
devicetree") reorganized the devicetree entries to make the
representation of CNVi device consistent with other internal PCI
devices. Since a dummy generic device is added for the CNVi device,
`emit_sar_acpi_structures()` needs to first check if the device is PCI
before checking the vendor ID. This ensures that SAR table generation
is skipped only for PCIe devices with non-Intel vendor IDs and not for
the dummy generic device.
BUG=b:165105210
Change-Id: I3c8d18538b94ed1072cfcc108552f3a1ac320395
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Adds ACPI properties for WDT8762A device.
Per spec v0.8
HID name WDHT2002
T14=100ms
BUG=b:163561649
BRANCH=puff
TEST=emerge-puff coreboot and check system dmesg and evtest can get device.
Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Hook up PCH thermal subsystem configuration to devicetree.
Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I0c606fd129c200446744f7a67ae63fec6d8e1684
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Calculate the frequencies based on the appropriate MSRs and pass them to
SMBIOS tables generator. Ivybridge microarchitecture does not yet
implement CPUID 16H leaf used to obtain the required frequencies.
TEST=Intel Core i7-3770, TianoCore UEFI payload displays the CPU
frequency correctly equal 3.4GHz in Boot Manager Menu, dmidecode shows
correct frequencies according to Intel ARK, 3.4GHz base and 3.9GHz turbo
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
We already have RFI UPD settings to mitigate RFI noise issues in
platform. These UPDs were not getting filled via devicetree but
needed to be filled from fsp_params.c
Exporting these UPDs to chip.h will allow OEM/ODMs to fill it
directly from devicetree and also allow us to control it based
on boards instead of keeping it common across SoCs.
BUG=b:171683785
BRANCH=None
TEST=Compilation works and we're able to fill UPD from devicetree.Value
gets reflected in FSP UPDs.
Change-Id: I495cd2294368e6b3035c48b9556a83418d5632de
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47286
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The X86 Qemu targets use the AMD64 SMM save state, but unlike
most AMD CPU's the PM ACPI SMI port is not configurable and uses
the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This prototype will be used outside of soc/amd.
Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently coreboot has limited use for the SMM save state. Typically
the only thing needed is to get or set a few registers and to know
which CPU triggered the SMI (typically via an IO write). Abstracting
away different SMM save states would allow to put some SMM
functionality like the SMMSTORE entry in common places.
To save place platforms can select different SMM save sate ops that
should be implemented. For instance AMD platforms don't need Intel SMM
save state handling.
Some platforms can encounter CPUs with different save states, which
the code then handles at runtime by comparing the SMM save state
revision which is located at the same offset for all SMM save state
types.
Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44323
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The SMM_ASEG code only supports up to 4 CPUs, so assert this at
buildtime.
Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The ASEG smihandler bails out if an unsupported SMM save state
revision is detected. Now we have code to find the SMM save state
depending on the SMM save state revision so reuse this to do the same.
This also increases the loglevel when bailing out of SMM due to
unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING,
given that the system likely still boots but won't have a functioning
smihandler.
Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The patch replaces if-else-if ladder with switch case for readability
purpose.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47054
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the genesis variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172620124
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_GENESIS
Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
This patch adds the PMC MUX and CONx devices for adlrvp. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
The resource function is called for each device VID/DID. Only add
the memory resource map from the boot CPU (bus 0) and not for each
socket/CPU. This is a NUMA architecture and has a shared memory map.
All the resources must match across the sockets/CPUs, so they should
only be added to the map once.
Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Move set_bios_init_completion() and helper functions from skx
and cpx soc_util.c to xeon common util.c. There are some slight
differences between skx and cpx, so used the more correct cpx
functions. Both cpx and skx platforms boot as expected.
Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47172
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.
Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Correct USB over-current mappings in devicetree now that the
GPIO config has been fixed per schematics.
Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
The LAN NIC is onboard, not installed in a slot.
Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add strings for M.2 keying and number of PCIe lanes.
Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.
Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
- set pads GPP_B6/B8 for PCIe CLK_REQ lines
- set pad GPP_B14 to speaker output
- adjust comment for GPP_C22 / USB3_P1_PWREN
- set pad GPP_E4 to NF1 / SATA_DEVSLP0
- set pads GPP_E9/E10 to USB2_OC0#/USB2_OC1#
Change-Id: I8bf8af620370ec2d4c864e513db5d710a9c65d27
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47220
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new CONFIG_OVERRIDE_UART_FOR_CONSOLE token to override the index
of uart port, platform use a get_uart_for_console routine to decide what
index value should be used for console.
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
|
|
The HOB does not move, place its location in .bss.
Change-Id: I2c6dbe4d64138e45fa1dfe7580ffa70d0441bd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47294
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The cpu/car code only applies to pre-family-17h CPUs that still use
cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor
code blob binaryPI interface.
Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)
Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).
Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.
Align pad group as per EDS and pin-ctrl driver in linux kernel.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.
Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Multiple GPIOs were defined as a reserved GPIO in JasperLake. Correcting
this GPIOs with proper name to align with EDS volume 2
Also removing unused GPIOs at the end of community 4 (group E).
Since those reserved GPIOs are at the end of the community, it won't
affect the offset calculations within community. This change will also
help us aligning pad numbering with kernel pin-ctrl drivers too.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=Platform boots fine and basic functionality such as SD, Wifi works.
Change-Id: I8326b7181d47a177261656f51602638d8ce80fbb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add information regarding the privacy pin on the overridetree and the
gpio.
BUG=b:171888751
Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:169840271
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Some devices, such as cameras, can implement a physical switch to
disable the input on demand. Think of it like the typical privacy
sticker on the notebooks, but more elegant.
In order to notify the system about the status this feature, a GPIO is
typically used.
The map between a GPIO and the feature is done via ACPI, the same way as
the reset_gpio works.
This patch implements an extra field for the described privacy gpio.
This gpio does not require any extra handling from the power management.
BUG=b:169840271
Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Update Power Limit2 (PL2) minimum value to the same as maximum value
for magolor board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.
BUG=b:168353037
BRANCH=None
TEST=Build and test on magolor board
Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.
BUG=b:172279061
BRANCH=volteer
Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.
BUG=b:172279061
BRANCH=volteer
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Move this function to pci_ops.c, which is already included in the smm
build. This is required to use this function in elog functionality,
which is called from SMM.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
LTE module used in boten has a specific power on/off sequence.
GPIOs related to power sequnce are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: Power off -> 500ms -> Power on
Configure the GPIOs based on these requirements.
BUG=b:163100335
TEST=Build and boot Boten to OS. Ensure that the LTE module power
sequence requirements are met.
Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This support is required to power off certain components that exist only
in certain variants.
BUG=None
TEST=Build and boot Boten to OS.
Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Allow a USB device to define PowerResource in its SSDT AML code.
PowerResouce ACPI generation expects SoC to define the callbacks for
generating AML code for GPIO manipulation.
Device requiring PowerResource needs to define following parameters:
* Reset GPIO - Optional, GPIO to put device into reset or take it out
of reset.
* Reset delay - Delay after reset GPIO is asserted (default 0).
* Reset off delay - Delay after reset GPIO is de-asserted (default 0).
* Enable GPIO - Optional, GPIO to enable device.
* Enable delay - Delay after enable GPIO is asserted (default 0).
* Enable off delay - Delay after enable GPIO is de-asserted (default 0).
BUG=b:163100335
TEST=Ensure that the Power Resource ACPI object is added under the
concerned USB device.
Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46713
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Copy lpit.asl to pep.asl to have a clean patch series without moving
files and to be able to keep the replace-patch CB:46471 as small as
possible to avoid confusion.
Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change adds memory parts used by variant voema to
mem_parts_used.txt and generates DRAM IDs allocated to these parts.
Added memory
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:171755775
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
This patch makes Atlas resume from S0ix by AC plug and unplug.
BUG=b:165328935
BRANCH=atlas
TEST=Put Atlas in suspend. Wake it up by AC plug.
TEST=Put Atlas in suspend. Wake it up by AC unplug.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
This change adds two functions that provide an IPC mailbox method via
ACPI for runtime clock configuration.
pmc_acpi_fill_ssdt_ipc_write_method() will provide a method in the SSDT
that can be called by other ACPI devices to send an IPC mailbox command.
This function is exported because some SOCs override the default PMC
device and need to call this function to write the method into the SSDT.
pmc_acpi_set_pci_clock() will call the method defined by the previous
function to enable or disable the PCIe SRCCLK for a specified root port
and clock pin. It can be called by the PCIe root port after turning off
power to the attached device.
BUG=b:160996445
TEST=boot on volteer device and disassemble the SSDT to ensure that this
method exists.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46259
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Commit cf5d58328fe004d967466be42de62d6bab4c3133 had changed
the size from 8 to 9 Kib in drivers/gma. This change makes use of
Kconfig option to pick the size for tigerlake.
BUG=b:171401992
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I21a0bba9ae01bac326f0f931641c98e8d308310f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Commit cf5d58328fe004d967466be42de62d6bab4c3133 had changed
the size from 8 to 9 Kib. This change adds Kconfig option to choose
vbt data size based on platform.
BUG=b:171401992
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia294fc94ce759666fb664dfdb910ecd403e6a2e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47151
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
acpigen_write_debug_namestr() - Debug = NAME
acpigen_write_return_namestr() - Return (NAME)
acpigen_set_package_op_element_int() - Set package pointer element
DeRefOf (PKG[ELEM]) = INT
acpigen_get_package_element() - Get package (not pointer) element
dest_op = PKG[ELEM]
acpigen_set_package_element_int() - Set package element to integer
PKG[ELEM] = INT
acpigen_set_package_element_namestr() - Set package element to namestr
PKG[ELEM] = NAME
acpigen_write_delay_until_namestr_int() - Delay while waiting for
register to equal expected value.
BUG=b:160996445
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I9b20a23872b7d4a50f03761032426ffbb722b9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47196
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
EEPROM in the camera module does not require any specific power
resources. This will ensure that no unnecessary resources are turned on
while accessing the camera EEPROM.
BUG=b:167938257
TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is
listed in the output of i2cdetect.
Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Handle AC connect and disconnect notifications from Embedded Controller
(EC) and wake from S3/S0ix.
BUG=b:172266344
TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up
from suspend on AC connect and disconnect on both the TypeC ports.
276 | 2020-11-04 12:21:29 | S0ix Enter
277 | 2020-11-04 12:21:40 | S0ix Exit
278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected
279 | 2020-11-04 12:21:57 | S0ix Enter
280 | 2020-11-04 12:22:03 | S0ix Exit
281 | 2020-11-04 12:22:03 | EC Event | AC Connected
282 | 2020-11-04 12:22:35 | S0ix Enter
283 | 2020-11-04 12:22:47 | S0ix Exit
284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected
285 | 2020-11-04 12:23:08 | S0ix Enter
286 | 2020-11-04 12:23:16 | S0ix Exit
287 | 2020-11-04 12:23:16 | EC Event | AC Connected
Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|