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2017-03-08mainboard/asus: Move F2A85-M_LE variant to F2A85-M.Kyösti Mälkki
Note that M and M_PRO had same DefaultPlatformMemoryConfiguration defined, use one for both. Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson/acpi: Only declare S3 if it is supportedMarc Jones
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add early SPI setupMarshall Dawson
Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18442 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add SPI definitions to headerMarshall Dawson
Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18441 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Consolidate BITn definitionsMarshall Dawson
Remove unused definitions from a .c file and use the BIT(n) macro found in types.h instead. Convert existing definitions to BIT(n). Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18440 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07mainboard/intel/galileo: Remove space before opening bracketLee Leahy
Fix the error detected by checkpatch and update the copyright date. TEST=Build and run on Galileo Gen2 Change-Id: Idc55169913e7b7b0aca684c26f6ed3b349fc6c09 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07soc/intel/quark: Fix errors detected by checkpatchLee Leahy
Fix the errors detected by checkpatch and update the copyright dates. TEST=Build and run on Galileo Gen2 Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18591 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/gru: add MAX_SDRAM_FREQ config to choose max ddr freqShunqian Zheng
Gru/Kevin use 933 MHz (actually 928 MHz for better jitter) as max sdram frequency, while bob uses 800 MHz. It's normal some variants can't meet 928 MHz SI requirement and hence have to use a lower freq as spec. BUG=chrome-os-partner:61001 BRANCH=gru TEST=check dpll is 800 MHz on bob Change-Id: I6d19a351f25d1f48547715ce57c3a87d9505f6f1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8176bfea52422c713f144ffec419752aeca66db2 Original-Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/420208 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com> Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55) Original-Reviewed-on: https://chromium-review.googlesource.com/448277 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/18581 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/veyron: add K4B4G1646E-BYK0 ddr with ramid 000ZShunqian Zheng
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0. For clarity, sdram-ddr3-samsung-2GB now is used by - K4B4G1646D-BYK0 - K4B4G1646E-BYK0 - K4B4G1646Q-HYK0 BUG=chrome-os-partner:62131 BRANCH=veyron TEST=emerge Change-Id: Ie43f23bf8f5f5b1acbb74c85cac17fe181c841c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46d62d87101e0ee1050b00db02b3ecaa4587e9f4 Original-Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/446197 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405) Original-Reviewed-on: https://chromium-review.googlesource.com/446300 Reviewed-on: https://review.coreboot.org/18519 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/veyron_*: Add new Micron and Hynix modulesDavid Hendricks
This adds SDRAM entries for the following modules: - Micron: DDMT52L256M64D2PP-107 - Hynix: H9CCNNNBKTALBR-NUD They are compatible with Samsung K4E8E324EB-EGCF, so this just copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used in the comment near the top. Notes on our "special snowflake" boards: - veyron_danger's RAM ID is hard-coded to zero, so I skipped changes involving the binary first numbering scheme. - Rialto's SDRAM mapping is different, so I padded its SDRAM entries to 24 to match other boards. - veyron_mickey requires different MR3 and ODT settings than other boards due to its unique PCB (chrome-os-partner:43626). BUG=chrome-os-partner:59997 BRANCH=none TEST=Booted new modules on Mickey (see BUG) Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3 Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412328 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com> Original-Tested-by: Jiazi Yang <Tomato_Yang@asus.com> Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6) Original-Reviewed-on: https://chromium-review.googlesource.com/446299 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18518 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07soc/intel/quark: Fix I2C driverLee Leahy
Fix the following issues: * A raw read is described by a single read segment, don't assert. * Support reads longer than the FIFO size. * Support writes longer than the FIFO size. * Use the 400 KHz clock by default. * Remove the error displays since vboot device polling generates errors. TEST=Build and run on Galileo Gen2 Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18029 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/poppy: fix finger print sensor interrupt gpio configurationRizwan Qureshi
Configure the right GPIOs for finger print sensor interrupt and reset lines. As per the schematics GPP_C8 is for sensor interrupt and GPP_C9 is for sensor reset. Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18389 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07nb/amd/amdht: Use variable for function namePaul Menzel
One very long line has to be wrapped to be shorter than 80 characters to satisfy the lint scripts. Note, that this gets rid of the brackets (). Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-07mainboard/asus: Add F2A85-M PRO variant to F2A85-M.Denis 'GNUtoo' Carikli
Status: - The primary PCIe 16x slot works: It was tested with a GPU compatible with nouveau - USB and audio are not very reliable - The ethernet card is not seen with lspci - The secondary pcie16x slot isn't working: When plugging a GPU inside, it's not seen with lspci - SATA works: The board fully boots GNU/Linux - Serial doesn't work - Populating the RAM slots might have to follow the recommended memory configuration that is described in the mainboard manual in order to be able to boot. Note that when running the shutdown command, the default boot firmware will rewrite part of the boot flash before powering off the machine. Flashing coreboot internally from the default boot fimrware can still work, if the power plug is removed after running flashrom. Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/16931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07AGESA: Add agesa_helper.h headerKyösti Mälkki
These definitions do not require AGESA.h include, and we will eventually remove agesawrapper.h files. Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07AGESA: Remove redundant and invalid IRQ routingKyösti Mälkki
The size of the array did not match that of the actual allocation. Furthermore, the tables are written as part of set_pci_irqs() in hudson/pci.c. Also the removed code was never reached runtime, as it is only executed on ACPI S3 resume path that is currently disabled. Change-Id: If1c47d53a7656bdff40d93fc132c8c057184ae46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18587 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07AGESA: Remove leftover s3resume includeKyösti Mälkki
Change-Id: I7a1574259f73a52b66d03c686ae8ab70345c36ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07AGESA fam14: Sanitize headerfileKyösti Mälkki
This file is only static defines. Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-03-07AGESA: Remove leftover agesawrapper includeKyösti Mälkki
Change-Id: Ib37989ee7535e59b1903537995f8383d8b04387c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07console: Enable printk for ENV_LIBAGESAKyösti Mälkki
Messages from AGESA proper are additionally controlled by various IDS parameters in board/OptionsIds.h file. Change-Id: I83e975d37ad2bdecb09c483ecae71c0ed6877731 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18545 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07Stage rules.h: Add ENV_LIBAGESAKyösti Mälkki
Definition is required to enable use of printk() from AGESA proper. Change-Id: I6666a003c91794490f670802d496321ffb965cd3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07elog: Fix duplicate event typeDuncan Laurie
The current elog implementation has two event types defined for 0xa7, apparently the result of divergent coreboot trees on chromium where some events were added to ARM systems but not upstreamed until later. Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7. BUG=b:35977516 TEST=check for proper "CPU Thermal Trip" event when investigating a device that is unexpectedly powering down. Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Clean up CPU codeSubrata Banik
Use header (soc/intel/common/block/include/intelblocks/msr.h) for MSR macros Change-Id: I401b92cda54b6140f2fe23a6447dad89879a5ef0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Use intel/common/xhci driverSubrata Banik
Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06intelblocks/msr: Move intel x86 MSR definition into common locationSubrata Banik
Move all common MSRs as per IA SDM into a common location to avoid duplication. Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18509 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/common/block: Add Intel XHCI driver supportSubrata Banik
Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18221 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/common: Make infrastructure ready for Intel common codeSubrata Banik
Select all Kconfig belongs into Intel SoC Family block/ips common code model and include required header.h file. Change-Id: Idbce59a57533dbeb9ccfadca966c3d7560537fa0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18377 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Clean up XHCI codeSubrata Banik
Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/apollolake: Move XDCI in its own fileAndrey Petrov
Split out dual-port switching functionality into dedicated xdci.c. Change-Id: Ia58fc3fb6d017dd0c19cc450d1caba307fc89a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18226 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06ec/lenovo/h8: Use older syntax for bit shiftPaul Menzel
Currently, when using `iasl` 20140926-32 [Oct 1 2014] from Debian 8 (Jessie/stable), the build of the Lenovo X60 fails due to syntax errors. ASL 2.0 supports `<<`. For consistency, right now, coreboot still uses the old syntax. So use `ShiftLeft` instead, which also fixes the build issue with older ASL compilers. Change-Id: Id7e309c31612387da3920cf7d846b358ac2bdc71 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18520 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-04soc/intel/skylake: indicate voltage margining enabled/disabledRizwan Qureshi
Support for voltage margining is dependent on the platform. Enabling voltage margining puts additional constraints for the SLP_S0# to be asserted and hence moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction, voltage marigining can be enabled. Use the UPD provided by FSP to enable/disable voltage margining. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-03mb/getac/p470: Do not select EARLY_CBMEM_INITArthur Heymans
This is selected by default and not overwritten anywhere else for this board. Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18541 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2017-03-02mainboard/google/poppy: Disable deep S3 on poppyFurquan Shaikh
BUG=chrome-os-partner:62963 BRANCH=None TEST=Compiles successfully Change-Id: Icb929262fd67362b8e5c5cf31dce04ab1f496695 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18467 Tested-by: build bot (Jenkins) Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-02nb/i945: Clean "Programming DLL Timings" functionElyes HAOUAS
As we drive both channels with the same speed, chan0dll and chan1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18472 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-03-02agesawrapper: Fix endless loop on bettongRicardo Ribalda Delgado
AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patch forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17924 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"Daniel Kulesz
This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6. The commit introduced a regression which is causing MC4 failures when 8 RDIMMs are populated in a configuration with a single CPU package. Using just 4 RDIMMs, the failure does not occur. After reverting the commit, I tested configurations with 1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an Opteron 6276. The MC4 failures did not occur anymore. Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65 Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com> Reviewed-on: https://review.coreboot.org/18369 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-03-02acpi: Update the ACPI ID for corebootDuncan Laurie
The newly assigned ACPI ID for coreboot is 'BOOT' http://www.uefi.org/acpi_id_list Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific ACPI objects instead of the placeholder range of "GOOGCBxx". Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02intel/broadwell: Use the correct SATA port config for setting IOBP registerYouness Alaoui
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.) [1]. Setting one of the SATA port 3 IOBP setting was using the value from the port 2 register. On the purism/librem13 (on which SATA port 3 is tested), this change doesn't seem to affect anything, as that typo wasn't exhibiting any visible problems anyways. [1] https://review.coreboot.org/18408 Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18514 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-01mb/apple/macbook21: Remove PCI reset code from romstageMono
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from romstage). The PCI reset was copied from code specific for Roda RK886EX and Kontron 986LCD-M. It is not needed on the MacBook. Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de> Reviewed-on: https://review.coreboot.org/18502 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-01nb/intel/i945: Fix sdram_enhanced_addressing_mode for channel1Elyes HAOUAS
Change-Id: I304467353bb9989f0d7e0ad7d1b632081f66b1af Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18482 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2017-03-01src/include: Include stdint.h since struct dimm_info uses itBarnali Sarkar
struct dimm_info has all the parameter types defined in stdint.h file. So including it. BUG=none BRANCH=none TEST=Build and boot KBLRVP Change-Id: I707523749ecf415e993b460f9613eae7be859c34 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18471 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01soc/intel/common: Save Memory DIMM Information in SMBIOS tableBarnali Sarkar
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM. Add function dimm_info_fill() which populates SMBIOS memory information from FSP MEM_INFO_DATA_HOB data. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS table from Kernel command "dmidecode". Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18418 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01src/vendorcode: Add Memory Info Data HOB HeaderBarnali Sarkar
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the MEM_INFO_DATA_HOB. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-28ec/lenovo/h8: Fix mute LEDsNicola Corna
thinkpad_acpi expects a SSMS method to turn on/off the mute LED and a MMTS method to turn on/off the microphone mute LED. With these methods implemented the driver can correctly sync the LEDs with the corresponding statuses. There seems to be two different bits to mute the audio in the Lenovo H8 EC: * AMUT, used internally (for example to disable the audio before entering S3). * ALMT, controllable by the OS, which also toggles the mute LED (if present). Tested on a X220T and on a X201. Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18329 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins)
2017-02-28mainboard/lenovo: Power off USB and mute audio before entering S3Nicola Corna
Currently, the USB ports are still powered during S3, so turning them off may reduce the power consumption. Note that, when the USB Always on feature is enabled, the USB ports are always powered, regardless of the USBP state. This patch also disables the audio, as it might consume some power or generate some noise. Both the USB power and the audio are reenabled by coreboot during the poweron. Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18464 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28ec/lenovo/h8: Pulse the power LED during S3, if supportedNicola Corna
On the models that support it (like the X220) the LED pulses, on the others (like the X201) the LED powers off. Change-Id: I2ac7dbc30609179e4ca5fc0a7b06763431fe3344 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18325 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28ec/lenovo/h8: Add tablet mode switch methodNicola Corna
thinkpad_acpi expects a MHKG method which returns the current state of the tablet mode switch shifted left by 3. If such method is not found, subsequent laptop/tablet mode events are ignored. Tested on a X220T. Change-Id: Ic9ffea2ffe507b3692d1dd7411c52b813ec32146 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18328 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28Select a default SeaBIOS PS2 timeout in H8 KconfigArthur Heymans
This timeout is probably needed on all devices with Lenovo H8 embedded controllers so set the default there. Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18274 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-25mainboard/google/reef: keep LPSS_UART2_TXD high in suspend stateAaron Durbin
The cr50 part on reef is connected to the SoC's UART lines. However, when the tx signal is low it causes an interrupt to fire on cr50. Therefore, keep the tx signal high in suspend state so that it doesn't cause an interrupt storm on cr50 which prevents cr50 from sleeping. BUG=chrome-os-partner:63283 BRANCH=reef TEST=s0ix no longer causes interrupt storm on cr50. Power consumption normal. Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18491 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-25google/eve: Add rise/fall times for I2C busesDuncan Laurie
Apply tuning for the PCH I2C buses on Eve based on rise/fall time measurements that were done with a scope. BUG=chrome-os-partner:59686 BRANCH=none TEST=Manual testing on Eve P1 to verify that all devices on I2C buses are still functional. Post-tuning measurement will be done once a new firmware is released. Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18487 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-25mainboard/intel/leafhill: Clean upAndrey Petrov
This patch tries to clean the code by: o removing duplication of LPC GPIO pads o removing incorrect definitions from devicetree o removing irrelevant entries from FMD file Also adds vital defaults in Kconfig so it is possible to build an image. Change-Id: Id9913f3b053189166392271152ce5300d82a7de8 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18479 Tested-by: build bot (Jenkins)
2017-02-25nb/amd/amdmct: Remove another currently unused tableJonathan Neuschäfer
This fixes a warning that the new toolchain generates. Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18485 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24mainboard/google/poppy: Change touchscreen IRQ to level-triggeredFurquan Shaikh
BUG=chrome-os-partner:62967 BRANCH=None TEST=Verified that touchscreen works on power-on and after suspend-resume as well. Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-24src/arch/x86: Remove non-ascii charactersMartin Roth
Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18376 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24ec/lenovo/h8: Guard against EC bugs in the battery status logic.Tobias Diedrich
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when the battery is nearly full and we switch from battery to AC by plugging in the cable, the current rate will not drop to 0 immediately, but the discharging state is cleared immediately. This leads to the code trying to process an invalid rate value >0x8000, leading to a displayed rate of >1000W. This patch changes the logic to deal with these corner cases. Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18349 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-24arm-trusted-firmware: Disable a couple of warnings for GCC 6.2Martin Roth
- Remove warnings about code using deprecated declarations such as: plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup': plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning: 'arm_gic_setup' is deprecated [-Wdeprecated-declarations] include/drivers/arm/arm_gic.h:44:6: note: declared here: void arm_gic_setup(void) __deprecated; - Disable pedantic warnings to get rid of these warnings: In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0: plat/mediatek/mt8173/include/mcucfg.h:134:21: error: enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant expression [-Werror=pedantic] MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17995 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-24nb/amd/amdmct: Remove two currently unused tablesJonathan Neuschäfer
This fixes warnings that the new toolchain generates. Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23mb/emulation/*-riscv: Don't select ARCH_BOOTBLOCK_RISCVJonathan Neuschäfer
It's already selected by SOC_UCB_RISCV. Change-Id: Ic8a14300cdea2a4ab763b2746434891b72843604 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18390 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23google/gru: whitespace fixPatrick Georgi
Follow up to https://review.coreboot.org/#/c/18460/ Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18475 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection thresholdWilliam wu
According to USB 2.0 Spec Table 7-7, the High-speed squelch detection threshold Min 100mV and Max 150mV, and we set USB 2.0 PHY0 and PHY1 squelch detection threshold to 150mV by default, so if the amplitude of differential voltage envelope is < 150 mV, the USB 2.0 PHYs envelope detector will indicate it as squelch. On Kevin board, if we connect usb device with Samsung U2 cable, we can see that the impedance of U2 cable is too big according to the eye-diagram test report, and this cause serious signal attenuation at the end of receiver, the amplitude of differential voltage falls below 150mV. This patch aims to reduce the PHY0 and PHY1 otg-ports squelch detection threshold to 125mV (host-ports still use 150mV by default), this is helpful to increase USB 2.0 PHY compatibility. BRANCH=gru BUG=chrome-os-partner:62320 TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into Type-C port, check if the USB device can be detected. Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8 Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/431015 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Inno Park <ih.yoo.park@samsung.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18462 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-02-23google/gru: update the pwm regulatorCaesar Wang
As David commented the "Bob and other follow-ons match Gru, Kevin should be the special case here", and update the calculations value for gru/bob board. From the actual tests, some regulator voltage than the actual set of less than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the {min, max} regulator voltage for Bob board. Make sure we get the accurate voltage. BUG=chrome-os-partner:61497 BRANCH=none TEST=boot up Bob, measure the voltage for little cpu and C-logic. Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4 Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4 Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/424523 Original-Reviewed-by: David Schneider <dnschneid@chromium.org> Original-Reviewed-by: Brian Norris <briannorris@chromium.org> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430403 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18460 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23mb/google/poppy: Enable support for DPTFSumeet Pawnikar
This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for poppy. It enables the DPTF flag in the device tree for poppy. It also includes the DPTF specific ASL file in the main DSDT definition. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17926 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-23lynxpoint bd82x6x: Enable PCI-to-PCI bridgeKyösti Mälkki
Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. It was previously argumented this is copy-paste and never known to be required for these more recent platforms: https://review.coreboot.org/#/c/2706/ Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18330 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-23intel/minnow3: follow up with recent changes in masterPatrick Georgi
minnow3 doesn't build right now due to API divergence on master branch. Follow up with recent changes. Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18476 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-02-23google/oak: Add initial support for RowanYidi Lin
Update GPIO controls and mainboard configurations for Rowan. [pg: use the opportunity to clean-up the gerrit-rebase task list with the entirely unrelated Ignore-CL-Reviewed-on lines] BUG=chrome-os-partner:62672 BRANCH=none TEST=emerge-rowan coreboot Change-Id: I110fb368b3d9fa9dfb2bf091342dfb511ff7c09c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4252cbe94a7456108aaa522e170bca5dcb1fdd1 Original-Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430557 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/341513 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/327003 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/355221 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/354670 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361360 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361361 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361362 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361363 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/382320 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405110 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405130 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/419795 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/424139 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430293 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430294 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430295 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427820 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427821 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427822 Reviewed-on: https://review.coreboot.org/18463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23google/gru: improve eye diagram for passing the testCaesar Wang
The children of Gru should share the benefits. In the real world, Bob can't pass the eye diagram tests. BUG=chrome-os-partner:62714 BRANCH=firmware-gru-8785.B TEST=build coreboot Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3 Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/440745 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/441468 Reviewed-on: https://review.coreboot.org/18461 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23soc/intel/skylake: Enable Systemagent IMGURizwan Qureshi
Camera and Imaging device should be enabled for camera usecase, FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit) expose the same as a config option in devicetree.cb Also remove a redundant assignment for PchCio2Enable. BUG=None BRANCH=None TEST=lspci should list 00:05:00 Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18365 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23mt8173: Enable Kconfig options for ChromeOSPaul Kocialkowski
This enables some required Kconfig options when CONFIG_CHROMEOS is set. Change-Id: I290902746c1ea19c8bcb69540e34fde09abb9adf Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/18448 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-02-23mb/apple/macbook21: Remove unused cmos parametersArthur Heymans
These parameters are probably the result of copying from the Thinkpad X60 code. Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-22intel/minnow3: Implement and configure GPIO tablesBrenton Dong
Copy GPIO table implementation from the google/reef board except with board variant features removed. Also exlcude CrOS GPIO functions. Remove previous romstage GPIO implementation in brd_gpio.h and romstage.c. Configure GPIO settings for MinnowBoard 3. Change-Id: Id2817dcf2f8f196ecd13c810f7f0010a115db566 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18375 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22intel/minnow3: Configure memory properlyBrenton Dong
Set the proper memory configuration for the MinnowBoard 3. The current values are copied from intel/leafhill. Set the proper values for MinnowBoard 3. Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18374 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-22mainboard/intel: Add MinnowBoard 3Brenton Dong
This commit adds the initial scaffolding for the MinnowBoard 3 with Apollo Lake silicon. This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with name changes. Special adaptations for MinnowBoard 3 mainboard will follow in separate commits. Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22commonlib/fsp.h: include sys/types.h for ssize_tJonathan Neuschäfer
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4: [...] > HOSTCC cbfstool/fsp_relocate.o > In file included from coreboot/src/commonlib/fsp_relocate.c:18: > coreboot/src/commonlib/include/commonlib/fsp.h:26: error: > expected '=', ',', ';', 'asm' or '__attribute__' before > 'fsp_component_relocate' [...] According to POSIX-2008[1], sys/types.h defines ssize_t, so include it. This should not break coreboot code (as opposed to utils code), as we have a sys/types.h in src/include. [1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18417 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22intel/i945: Fix up whitespace and indentationPaul Menzel
Fix up the whitespace issues introduced in commit 39bfc6cb (nb/i945/raminit.c: Fix dll timings on 945GC). Change-Id: I3a4152866226401bc51c7fb1752aab541a4c72b0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18465 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2017-02-22nehalem/Kconfig: Rename TRAINING_CACHE_SIZE to MRC_CACHE_SIZEArthur Heymans
This is more consistent with newer Intel targets. Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18371 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-02-22nb/intel/nehalem: Clean nehalem.hArthur Heymans
Remove unused definitions, prototypes and macros moslty copied from gm45. Change-Id: I076e204885baec3d40f165785cf4ae4adc9154c5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18370 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22purism/librem13: Set system type to laptopYouness Alaoui
Change-Id: I3ae80f5727e83a1c9210f0d13fa7fc32c5c79085 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18412 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-02-22purism/librem13: Fix HDA codec verbs. Use correct codec vendor idYouness Alaoui
There was a 'typo' where the subsystem id was set instead of the codec vendor id. This caused the lynxpoint HDA codecs init to fail to find the proper codecid verbs so codecs were never initialized. That caused the headphones jack to not work. Change-Id: I975031643fc42937ecaea2300639b90632543f67 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18411 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-02-22purism/librem13: Enable PCIe ports 1 and 2Youness Alaoui
Change-Id: I1fa72e59866ee4aad34d4b60e499f6e37acc367f Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18410 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-22purism/librem13: Fix M.2 issues.Youness Alaoui
The M.2 SSD is on the SATA port 3, which also required the DTLE setting to be set. This fixes issues with the M.2 SSD not being detected/stable. Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18409 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-22Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.Youness Alaoui
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but Browell supports up to 4 ports, so we need to support setting IOBP for ports 2 and 3 as well. The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only guessed by looking at ports 0 and 1 and extrapolating from there. Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work so we can assume that port 2 and 3 magic numbers are valid, but having someone confirm them (through non-public documents?) would be great. Change-Id: I59911cfa677749ceea9a544a99b444722392e72d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18408 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-22src/mainboard/digitallogic: Add license headers to all filesMartin Roth
Change-Id: I6a1810360b5c3210038670aea6e80312798a63cd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18406 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-02-22src/cpu/x86: Update/Add license headers to all filesMartin Roth
Change-Id: I436bf0e7db008ea78e29eaeef10bea101e6c8922 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18405 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-02-22src/cpu/intel: Add license headers to all filesMartin Roth
Change-Id: I5ba8b186972fb59686dcbe11358cd26408cbaf05 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18404 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-02-22src/cpu/amd: Update/Add license headers to all filesMartin Roth
Change-Id: I1e0b2b9086db6b3c2f716d9400a83eb60b2ce222 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18403 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-02-22arch/x86/acpigen: Provide helper functions for enabling/disabling GPIOFurquan Shaikh
In order to allow GPIOs to be set/clear according to their polarity, provide helper functions that check for polarity and call set/clear SoC functions for generating ACPI code. BUG=None BRANCH=None TEST=Verified that the ACPI code generated remains the same as before for reef. Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22google/gru: Fix whitespacePatrick Georgi
Change-Id: I538c28fb1bc412947ef9df947fa3f6a3312aeb4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18322 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22qualcomm/ipq40xx: add vector operation method to SPIYuji Sasaki
Adding spi_xfer_two_vectors as .xfer_vector for ipq40xx spi_ctrlr. Commit c2973d196d1 ("UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING") has added a new driver method xfer_vector to support combined write-read operation within a single CS cycle. The method is wrapped in the spi_xfer_vector() API. When spi_ctrlr structure does not have xfer_vector method, API calls write and read operations sequentially. However the QCA40xx SPI driver has "forced" CS activation-inactivation in xfer method, so individual operation will break CS after write operation, making combined write-read cycle broken. Adding xfer_vector method to spi_ctrlr is a simple fix to prevent this. BUG=None BRANCH=none TEST=built and run on Gale Change-Id: I2258e563d0793bcacd626f78b8e96b3649a8e4a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88a8824951cef4fe293dfa6e3a1a837ae07b6156 Original-Change-Id: I031e85ce5b847353cb1084f6f68b2af8c6f702e1 Original-Signed-off-by: Yuji Sasaki <sasakiy@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/433439 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/18297 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22southbridge/amd: Add LPC bridge acpi path for Family14 and SB800Tobias Diedrich
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family14 northbridge with an SB800 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge (_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c (_SB.PCI0.LPCB). Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18402 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-02-22soc/intel/skylake: Fix broken suspend-resumeFurquan Shaikh
With recent change (a4b11e5c90: soc/intel/skylake: Perform CPU MP Init before FSP-S Init) to perform CPU MP init before FSP-S init, suspend resume is currently broken for all skylake/kabylake boards. All the skylake/kabylake boards store external stage cache in TSEG, which is relocated post MP-init. Thus, if FSP loading and initialization is done after MP-init, then ramstage is not able to: 1. Save FSP component in external stage cache during normal boot, and 2. Load FSP component from external stage cache during resume In order to fix this, ensure that FSP loading happens separately from FSP initialization. Add fsp_load callback for pre_mp_init which ensures that the required FSP component is loaded/saved from/to external stage cache. BUG=chrome-os-partner:63114 BRANCH=None TEST=Verified that 100 cycles of suspend/resume worked fine on poppy. Change-Id: I5b4deaf936a05b9bccf2f30b949674e2ba993488 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18414 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp loadFurquan Shaikh
Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed. BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully. Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18413 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22nb/i945/raminit.c: Fix dll timings on 945GCElyes HAOUAS
Values based on vendor bios. TESTED on ga-945gcm-s2l with 667MHz ddr2. Change-Id: I2160f0ac73776b20e2cc1ff5bf77ebe98d2c2672 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17197 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-02-21mainboard/google/poppy: Enable Realtek 5663 supportRizwan Qureshi
Enable Realtek RT5663 codec i2c device and add required SSDT parameters. BUG=chrome-os-partner:62051 BRANCH=None TEST=With required driver support in kernel verify audio on headset Change-Id: I9b9eb1e7edca56870f5be0e4fd603c9b0dc7f9de Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18216 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-21mainboard/google/poppy: Enable Maxim MAX98927 codecRizwan Qureshi
Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=chrome-os-partner:62051 BRANCH=None TEST=with required driver support in kernel verify audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://review.coreboot.org/18215 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-21mainboard/google/poppy: Generate required nhlt tableRizwan Qureshi
poppy board uses Maxim 98927 speaker codec and Realtek RT5663 for headset. Select the apropriate NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for codec and the supported topology in poppy. BUG=chrome-os-partner:62051 BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-board mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18214 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20google/eve: Set touchscreen I2C bus speed to 1MHzDuncan Laurie
Enable Fast-Plus speed for the touchscreen device so it can be used at 1MHz instead of 400KHz. BUG=chrome-os-partner:61277 TEST=manual testing on Eve P1, needs backported kernel patches to actually make use of any I2C speed other than 400KHz Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18397 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-20google/eve: Add audio devicesDuncan Laurie
Add the audio devices to Eve mainboard: - Describe Maxim 98927 speaker amps and RT5663 headphone codec in ACPI so they can be enumerated by the OS. - Supply NHLT binaries for MAX98927, RT5663, and DMIC_4CH. BUG=chrome-os-partner:61009 TEST=manual testing on Eve P1 with updated kernel to ensure that both speakers and headset are functional. DMIC support is is still being worked on and is not yet functional. Change-Id: I5243e35d159a0ed15c6004e94ba5a50b28cff0a9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18398 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:46:20 +0000