Age | Commit message (Collapse) | Author |
|
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Prepare for products that can use any DRAM for TSEG.
Include an ID for data pointed to by an ACPI BERT table. This region's
only requirement is it is marked reserved.
Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36115
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clarify names as I2C2, etc. Use iomap.h defines for base addresses.
Update IRQs.
Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33991
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a function to uart.c to ensure the right IOMux settings are
programmed for the console UART. Update Kconfig to reflect the
new addresses.
Give the user the ability to downclock the UARTs' refclock to
1.8342MHz.
Add the abiltiy to use an APU UART at a legacy I/O address.
Update the AOAC register configuration for the two additional
UARTs.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add Picasso's Device ID and default filename.
Only a single Device ID is documented for Picasso so remove the oprom
remapper function.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34422
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Picasso's SATA controller operates only in AHCI mode. Remove the
Kconfig symbols previously used to select between other possibilities.
Change-Id: Iaeb8b4a2540e976d2e7361faf8c6d261e60398fd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
SATA is no longer defined in AOAC so remove its definitions.
Change-Id: Ief0ab6b5f69f2d17c11d8e2ee40941ac56c077f6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary. The most notable changes are:
* Update the index values for the C00/C01 interrupt routing
* FORCE_STPCLK_RETRY is not present
* PCIB is not defined
* FCH MISC Registers 0xfed80e00 numbering has changed
* C-state base moves from PM register to MSR
* Add option to determine the intended MUX settion for LPC vs. eMMC
* Remove the LEGACY_FREE option
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I69dfc4a875006639aa330385680d150331840e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The standard PCI register space for D14F0 is accessible at 0xfed80000.
Add functions for use as helpers.
Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The LPC-ISA bridge supports two ranges for SuperIO control registers.
Add a generic function to allow a mainboard to enable the appropriate
range. Provide #define values that are more descriptive than the
register's field names.
Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change to the appropriate device IDs. Remove the ehci resource
call. Remove overcurrent settings, as this will be passed to
AGESA in later change.
Remove unused USB2 ACPI name assignment.
Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add Kconfig options and Makefile command line options to generate
the amdfw.rom image. A new intermediate image is introduced, which
is the initial BIOS image the PSP places into DRAM prior to
releasing the x86 reset. The amd_biospsp.img is a compressed
version of the romstage.elf program pieces.
Additional details of the PSP items are not public information. See
NDA document PID #55758.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Ic8a28493c386c0097dbf3478e6d046fdfbf28724
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Fix compiler warning by adding an additional check for the fastpath
memset.
Change-Id: I9a80438995bafe7e436f3fe2180b8c9574eeff23
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It is similar to X200s, with U-series CPU, slightly different gpio
setup, no docking support, and no superio chip.
Tested:
- CPU Core 2 Duo U9400
- Slotted DIMM 4GiB*2 from samsung
- Camera
- pci-e slots
- sata and usb2
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
Linux payload (Heads) and Seabios.
TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in
CB:4294 ) for h8-using devices without a dock.
Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36128
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
This commit creates a dood variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.
BUG=b:141960652
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Add cbfsoption --ibb to mark files as IBB
* Will be used by "Legacy FIT TXT" boot
Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
* Mark files in CBFS as IBB (Initial BootBlock)
* Will be used to identify the IBB by any TEE
Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance
with doc#332691-003EN and doc#334819-001.
Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
FBG-1701 revision 1.3 will use Kingston onboard memory.
Add Kingston SPD file.
When Samsung memory configuration is disabled use
cpld_read_pcb_version() for using correct SPD data.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701 revision 1.3
Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792
Reviewed-by: Wim Vervoorn
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change d3a1a417 "src/superio: Remove unused superio chips" removed
all unused devices except for ones used on mainboards still under
review. The SMSC 1036 was inadvertenly also removed as well. This
device is used in debug cards that may be connected to AMD CRBs.
This patch restores the smsc1036 directory as-is and then corrects
the following lint messages.
* WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
* ERROR: else should follow close brace '}'
* WARNING: braces {} are not necessary for single statement blocks
Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move all code involving the cpld to a single file.
Rename mainboard_read_pcb_version() to cpld_read_pcb_version().
BUG=N/A
TEST=tested on fbg1701 board
Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The change applies the DPTF parameters.
BUG=b:142849037
TEST=build and verified by thermal team
Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The DRAM calibration blob can be compressed using pre-RAM algorithm
(currently LZ4), which will save ~12ms in boot time.
On Kodama, boot time difference:
Before: 1,082,711
After: 1,070,309
BUG=b:139099592,b:117953502
TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed)
BRANCH=kukui
Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Chrome OS firmware images have moved bitmap resources from GBB into CBFS
for a long time, so the GBB should only hold firmware keys and HWID,
that is usually less than 10k.
ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but
many recent x86 simply copy from old settings and may run out of space
when we want to add more resources, for example EC RO software sync.
Note, changing the GBB section (inside RO) implies RO update,
so this change *must not* be cherry-picked back to old firmware
branches if some devices were already shipped.
BRANCH=none
BUG=None
TEST=make # board=darllion,hatch,kahlee,octopus,sarien
Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The two GPIO functions variant_gpio_table() and
variant_early_gpio_table() provide the pointer to the variants GPIO
table for late and early GPIO init. As these functions are variant
dependent the keyword __weak must not be used as otherwise the linker
might choose the tables from the baseboard.
This patch removes the __weak definition making these functions
overriding the general ones in baseboard/gpio.c.
Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36094
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To make data flow more explicit, global variable 'impedance' is replaced
with a local variable, which is passed as a function argument.
BUG=none
BRANCH=kukui
TEST=Krane boots correctly
Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with
multiple frequencies to support DVFS switch.
BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
This patch supports voltage adjustment for each DRAM frequency, which is
neccesary to support DVFS switch.
BUG=b:80501386,b:142358843
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
DRAM DVFS needs to be calibrated with different vddq voltages to get
correct parameters.
A new API is added to allow changing vddq voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vddq voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
DRAM DVFS needs to be calibrated with different vdram1 voltages to get
correct parameters.
A new API is added to allow changing vdram1 voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vdram1 voltage with multimeter
Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33186
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Most coreboot debug messages are sent to UART and cbmem console, and we
also want to collect DRAM calibration module output, especially for
cbmem console (so we can see the logs after kernel is up).
Instead of sharing whole cbmem/cbtable/cbmemconsole implementations, we
want to simplify that by a simple function pointer so output can be
preserved by do_putchar, which internally sends data to all registered
consoles (usually cbmem console and UART).
BUG=b:139099592
TEST=make; boots properly for full-k, with and without serial console.
BRANCH=kukui
Change-Id: I1cf16711caf3831e99e17b522b86694524425116
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36056
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the
romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol.
Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between
RW_A and recovery, which works quite well as a developer mode to test
RW_A with the COREBOOT slot as a fallback.
Change-Id: I9d524988e991457032f63a947606d1b3581de5e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
During the raminit the CPU gets reset but the platform does not. To
deal with TPM init failure (a TPM can only be started up once) ignore
the invalid POSTINIT return code.
Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36055
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are use cases where TPM has already been set up in a previous
stage, e.g. TXT or when a CPU reset without a platform reset happens.
If this is the case the TPM startup will return a
INVALID_POSTINIT (return code 0x26). This adds a Kconfig to allow
platforms to disregard that return code.
Change-Id: I238b30866f78608c414de877b05a73cf8fdb9bbd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
The checksum is stored in the header of calibration data and saved to
SPI flash. After reading the data from flash, checksum is used to verify
the integrity of the calibration parameters.
BUG=b:139099592
BRANCH=kukui
TEST=Calibration data successfully loaded from flash
Change-Id: Ie4a0688ed6e560d4c0c6b316f44e52fd10d71a9d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
In broadcast mode we only need to set registers for channel 0
instead of all channels.
BUG=none
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Some typos are fixed to make DVFS switch work.
BUG=b:142358843
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and
other bit field helpers.
Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch contains some minor changes including:
- Use lowercase hex literals
- Combine short lines
- Remove unnecessary curly braces
- Simplify struct initialization
- Leverage macro _SELPH_DQS_BITS
- Ensure whitespaces around binary operators
- Remove extra whitespaces after commas
- Change log level and remove unnecessary debug logs
BUG=none
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
If DRAM calibration fails or mem test fails using the cached calibration
results stored in flash, rerun DRAM full calibration. If partial
calibration fails or the mem test following it fails, hang forever.
Partial calibration acts as a fallback approach in case of full
calibration failure. Therefore, if it fails, there would be no other
ways to initialize DRAM. Instead of falling into reboot loop and
draining out of battery, it is better to just hang so that the end user
may notice that and send to RMA.
BUG=b:80501386,b:139099592
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35481
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is already done in nb/intel/nehalem/romstage.c.
Change-Id: I2dc34af874ac96af31ca9ebe6a43b2805da32d18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
During the raminit the CPU gets reset, so reprogram those bits in
PM1_CNT such that the CPU remains aware that this is a S3 resume path
after the reset.
Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This decreases the output verbosity of RAM_DEBUG to be useful.
Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tune I2C bus 1 clock and insure it meets I2C spec.
BUG=b:142683257
TEST==flash coreboot to the DUT and measure I2C bus 1 clock
frequency less than 400KHz
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add enable pin for elan touchscreen
BUG=b:142710871
TEST=touchscreen work
Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Update power sequence to meet spec.
BUG=b:142710867
TEST=touchscreen work, and make sure power sequence to meet
spec with vendor.
Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36060
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the SPD data for MT40A1G16KD-062E:E
BUG=b:139397313
TEST=Compile successfully.
Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Disable DRRS on Blooguard SKU - 49, 50, 51, 52
BUG=b:142632381
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is blooguard.
Cq-Depend: chrome-internal:1983227
Change-Id: I36a313fd2beacb878da7383f733e206067c1c0fb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
I tested the SPI through the SD card and fixed sd card communication problem.
Added two functions (claim_bus and release_bus). Setting CS signal is invalid by
default.
Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.
TEST=the patch was ran on affected HW and success was reported
Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Corrected clang issues in fbg1701 directory.
BUG=N/A
TEST=build
Change-Id: I968bf8418aa457a7ebd28096bd92a64211bf86dd
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.
Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
As VGA_ROM_RUN and libgfxinit are mutually exclusive in Kconfig,
we don't have to guard all the VGA BIOS if's and can assume
gfx_get_init_done() returns 0 until all the quirks are handled.
Then, we can run libgfxinit.
Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point:
The CPU has no PWM pin and sends the PWM duty-cycle setting
to the PCH. The PCH can choose to ignore that and use its own
setting (BLM_PCH_OVERRIDE_ENABLE).
We use the CPU setting on these platforms.
o Lynx Point + Haswell:
The CPU has an additional PWM pin but can be set up to send
its setting to the PCH as before. The PCH can still choose
to ignore that.
We use the CPU setting with Haswell.
o Lynx Point + Broadwell:
The CPU can't send its setting to the PCH anymore. BLM_PCH_
OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
used (it virtually always is).
We have to use the PCH setting in this case.
o After Lynx Point:
Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
implied and the bit not implemented anymore.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
On some configuration coreboot boots too fast and the EC reports the
max temperature, resulting in Linux shutting down immediately.
Change-Id: I610c7c9fbf2130566d3c2c758f1796314d3a0973
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: I03461cb9e87b4ddd599e5601637a75b012694e7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Link files to provide snprintf used by VBOOT code.
Change-Id: I040c3952c22893da5aae11b20a618aa4006c6c58
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I14843c1944f2c1e0a26870b576bac549c0cac7f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Required for new VB2_ASSERT and VB2_DIE macros in vboot code.
(See chromium:972956.)
BUG=b:124141368, chromium:1005700
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I61a1036ccab80862d6eb12f9f72286f29e8478cf
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to
the DPTF.
BRANCH=None
BUG=b:142266102
TEST=`emerge-hatch coreboot`
Verify that Helios builds correctly.
Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Enable wifi sar feature and set wifi sar name for dragonair sku.
BUG=b:142109545
TEST=emerge-hatch coreboot chromeos-bootimage
1. Check wifi_sar-dragonair.hex in /cbfs-rw-raw/dratini
2. Add iwlwifi.debug into kernel params.
3. check SAR value from dmesg only when sku id is 21/22
Change-Id: I0e08610b7c7d2d8da5a749d278bcde26af590e31
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
FPMCU_PCH_BOOT1 pin is connected to GPP_C12. So, config GPP_C12.
BUG=b:142188003
TEST=emerge-hatch coreboot
Change-Id: I73a5c3529330ef3e72f4c7d5fcbbd2f6693494d8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35845
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
APL unhides the P2SB device in coreboot already. Do the same on SKL/KBL.
As the coreboot PCI allocator needs to be able to find the device,
unhide it after FSP-S.
The device is hidden in the SoC finalize function already and not visible
in the OS, as more P2SB device IDs have been added.
Other SoCs aren't updated, because they are too broken.
Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Tested on Supermicro X11SSH-TF.
Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner
|
|
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written
when already locked by the sibling thread. In addition it loads microcode
updates on all threads.
To prevent such race conditions only call the code on one thread, such
that the MSRs are only written once per core and the microcode is only
loaded once for each core.
Also add comments that describe the scope of the MSR that is being
written to and mention the Intel documents used for reference.
Fixes crash in SGX MP init.
Tested on Supermicro X11SSH-TF.
Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The port is based on the x201 / t410s.
2537-vg5 / i5, no discrete gpu
Tested and working:
* Native raminit
* Native gfxinit
* Booting Seabios 1.12.1
* Booting from EHCI
* Running GNU/Linux 5.0.0
* No errors in dmesg
* EHCI debug on the devices left side, bottom-right
* Keyboard
* Fn keys (Mute, Volume, Mic)
* Touchpad
* TPM
* Wifi
* Sound
* USB
* Ethernet
* S3 resume
* VBOOT
Testing in progress.
Untested:
* VGA
* Displayport
* Docking station
Bugs:
* AC adapter can't be read from ACPI
* TPM not working with VBOOT and C_ENV BB
Details for flashing externally:
1. Disconnect all power
2. Connect the external flasher
3. Connect the power cord (This fixes internal power control)
4. Remove the power cord
Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This assumes ACPI aware OS also have a driver for this particular
hardware, which is the case for at least Linux. This saves ~60ms on S3
resume.
Change-Id: I2dcd399fee8e2d1cd1b70e60e1669a49c7aa8cb4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
somehow a board needs to override this behavior it can happen in the
mb_setup_superio() hook (that will be renamed when moving to
C_ENVIRONMENT_BOOTBLOCK).
Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
These SIOs are not being used or tested by abuild, so remove them from the
tree. The only 3 currently unused SIOs that don't get removed here have board
ports in review.
src/superio/fintek/f71805f
src/superio/fintek/f71872
src/superio/intel/i8900
src/superio/ite/it8671f
src/superio/ite/it8716f
src/superio/nsc/pc87309
src/superio/nsc/pc87360
src/superio/nsc/pc87366
src/superio/nsc/pc97317
src/superio/smsc/dme1737
src/superio/smsc/lpc47b272
src/superio/smsc/lpc47b397
src/superio/smsc/sch4037
src/superio/smsc/sio1036
src/superio/via/vt1211
src/superio/winbond/w83697hf
src/superio/winbond/wpcd376i
Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I2d0b3d73d646fc43f2562aa5af2358398eaf28b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Id8e25caf2868c37c9d7c7717dd908152dfc583a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Tested on Lenovo Thinkpad X201, selects slot or recovery just fine.
Change-Id: Ia2b2f2b95510388599266264eaed0d64ce9b6ec5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
existing bootblock_mainboard_early_init().
Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Some of the initialization isn't necessary before console INIT is
done.
EHCI debug still works fine on the Lenovo Thinkpad X201.
Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35949
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This allows to read and set bits in the EC ram in the bootblock or
verstage. This can be useful if one needs to read a keyboard key as an
input for get_recovery_mode_switch in vboot.
Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: I0b1356420c9ae419b2a0a247b9dc6c8e92b7689a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Ic56367d64b9304b36f5ba5a4b7d5237574eb73ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Iaf9a4608f1b7d25cf5d8dbe2c1489b3d2d00f25a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The NO_POST option covers more than classical port 80 output, hence
selecting it seems wrong in any case. The default is still rather
user patronizing, but let's keep it.
As a side effect, this fixes the ability to override the default
for NO_POST which Kconfig rejected while these boards selected it.
(Seems like a bug in Kconfig, though.)
Change-Id: I896b08812b1aa6ce249d7acc8073ebcc0f72eace
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
The vendorcode/eltan mboot and verified boot options only build if a
few other Kconfig options are defined.
Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35954
Reviewed-by: Wim Vervoorn
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is only one subdir in vendorcode/siemens and it does not feature
a Kconfig file.
Change-Id: I136743344465cea9c769234aa84d9ebe874ef0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
The next board rev will have a new option for an Elan touchscreen. Add
support for this in the devicetree, as well as use the 'probed' property
on both touchscreen options.
BUG=b:141957731
BRANCH=none
TEST=compiles (next board rev not available yet)
Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846
BRANCH=octopus
TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This is unused since C_ENVIRONMENT_BOOTBLOCK is used.
Change-Id: Id5af41e455d211eba89cfeb625f4c728b4145da7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Rework SGX enable status in a clean way without using a global variable.
Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: If30a17d053da8f0758085fc36469b564d46049cd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This is done by default in the main Makefile.inc.
TEST: With BUILD_TIMELESS=1 the resulting binary is identical before
and after the change.
Change-Id: Ie85e023df1f1c2b0f115e4f92719a511f60019c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Since struct dramc_param has been defined, we can pass the struct
directly from mt_mem_init().
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|