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2019-11-07mainboard/google: Allow Hatch variants to read SPD data over SMBusEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. V.2: Dispence with memcpy(). V.3: Revert back to previous patch with memcpy(). V.4: Rewrite again to avoid memcpy(). BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07mb/google/hatch/variants/helios: Modify touchscreen power on sequenceKane Chen
The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix. from b/142368161: 1. Modify GPP_D: The specification define T1 >= 10ms. We change it to 12ms for a safety and low impact value in our mind. Enable pin as GPP_D9 is define to be AVDD in specification. Set it to 10ms to make it to be the final one to pull low during power off sequence . 2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be 500us . So we change it to 5 to be a low impact value in our mind according to the true T4 value we got . BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage ./util/abuild/abuild -p none -t google/hatch -x -a Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06arch/x86: Create preprocessed __ROMCC__ bootblock sourceKyösti Mälkki
Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIPArthur Heymans
This is a property of the FSP, not something the user can decide. Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-06soc/intel/common: Make native and FSP-T CAR init mutually exclusiveArthur Heymans
postcar stage does not consume cpulib.c, so don't include it there. Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06drivers/intel/fsp2_0: Move Debug options to "Debugging"Arthur Heymans
Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-06Kconfig: Organize debugging options per file extensionsArthur Heymans
Change-Id: Ia4553fb4cd95d2f1fa86eecbf382e6e6dec52b92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36616 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06lib: add calculate crc byte by byteXiang Wang
Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-06mb/g/drallion: Override smbios enclosure type for drallionMathew King
Drallion can be either a clamshell or convertible depending on the presence of the 360 sensor board. Set the smbios type 3 enclosure type to either CONVERTIBLE or LAPTOP accordingly. BUG=b:143701965 TEST='dmidecode -t 3' Type = Convertible with sensor board connected Type = Laptop with sensor board disconnected Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36512 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06mb/g/drallion: Consolidate 360 sensor board detectionMathew King
Create a single function to determine if the 360 sensor board is present on a device. BUG=b:143701965 TEST='emerge-drallion coreboot' Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-11-06arch/riscv: Use FDT from calling argument when using FITArthur Heymans
Only FIT payloads provide their own FDT. Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36599 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06arch/riscv: Rename `stages.c` to `romstage.c`Nico Huber
It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06security/vboot/Kconfig: Remove unused symbolsArthur Heymans
Change-Id: I417a2ff45b4a8f5bc800459a64f1c5a861fcd3d5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-06mb/emulation/qemu: Add VBOOT supportPatrick Rudolph
Add VBOOT support for testing purposes. Add a 16 MiB FMAP containing RO + RW_A. Tested on qemu. Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06mainboard/google: Rework Hatch so that SPD in CBFS is optionalEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-06soc/intel/icelake: Set FSP_TEMP_RAM_STACK unconditionallySubrata Banik
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other guard to assign FSP_TEMP_RAM_SIZE. Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05mb/google/hatch/variants/helios: Update TSR3 sensor thresholdsSumeet Pawnikar
Update thermal threshold settings for TSR3 sensor. There is an issue fan is always running, even during system idle state. This change fixes this issue and fan starts only when it breaches the temperature threshold. BRANCH=None BUG=b:143861559 TEST=Built and tested on Helios system Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05superio/*/*/acpi: Improve the readability of the IndexFieldElyes HAOUAS
Change-Id: I64fdcbcbbd54334c1c551bc1346c6000ea82c97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-05arch/riscv: Don't link `stages.c` into ramstageNico Huber
It's superseded by `ramstage.S`. Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/common: Include Tigerlake device IDsRavi Sarawadi
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-05drivers/intel/fsp2_0: Use strip_quotes for cbfs filenamesWim Vervoorn
The quotes were not stripped for the cbfs filenames of the FSP components. This is causing problems when the regions-for-file macro is executed (when VBOOT is enabled and the files should be filtered). BUG=N/A TEST=build Change-Id: I14267502cfab5308d3874a0c0fd18a71b08bb9f8 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36548 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05security/vboot: Removed vboot_prepare from vboot_locatorWim Vervoorn
When prog_locate() is called in the stage VBOOT is starting from and the image to be loaded is not the target image vboot_prepare() may be called too early. To prevent this vboot_prepare() is removed from the vboot_locator structure. This allows more control over the start of the vboot logic. To clarify the change the vboot_prepare() has been renamed to vboot_run_logic() and calls to initialize vboot have been added at the following places: postcar_loader: when VBOOT starts in ROMSTAGE romstage_loader: when VBOOT starts in BOOTBLOCK ramstage_loader: when VBOOT starts in ROMSTAGE BUG=N/A TEST=tested on facebook fbg1701 Change-Id: Id5e8fd78458c09dd3896bfd142bd49c2c3d686df Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36543 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05vendorcode/eltan/security: Align mboot with coreboot tpmWim Vervoorn
Align the eltan mboot support with coreboot tpm support to limit the amount of custom code. We now only support SHA256 pcrs, only single a single digest will be handled in a call. The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is selected. BUG=N/A TEST=tested on fbg1701 Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-05commonlib: Use __builtin_offsetof with supported compilersAlex James
Use __builtin_offsetof (which is treated as a constant expression) with Clang & GCC. This also allows check_member to work with Clang 9. Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/fsp_broadwell_de: Add CONFIG_IED_SIZE, drop CONFIG_SMM_TSEG_SIZEAndrey Petrov
Fix regression introduced in recent SMM region handling overhaul. Previously IED region size was hardcoded in the code. However when chip code was modified to use smm_region() and friends, IED_SIZE define was not added and build system quetly substituted it with 0. Also, drop CONFIG_SMM_TSEG_SIZE which is now obsolete. TEST=tested on watson platform; without the patch tg3 NIC driver doesn't work properly and that gets solved with this patch Change-Id: Id6fb258e555bb507851886b0e75f1f53c3762276 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36417 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefinedArthur Heymans
if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if CONFIG_MMCONF_BASE_ADDRESS is not defined. Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35883 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05src/Kconfig: Drop unused DEBUG_ACPIElyes HAOUAS
Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36498 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05mb/supermicro/x11ssh-tf: Disable i8042 supportPatrick Rudolph
Even though the vendor firmware enables the i8042 I/O port, it doesn't feed valid data to those, but instead uses USB HID devices. Disable the KBC port in SuperI/O and report no KCS port using FADT. Fixes: * Fixes error message in Linux that i8042 keyboard couldn't be enabled. Tested on Supermicro X11SSH-TF: The virtual remote managment console still works. Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-05drivers/pc80: Remove UDELAY_TIMER2Kyösti Mälkki
Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36534 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05drivers/pc80: Remove UDELAY_IOKyösti Mälkki
Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-05intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMERKyösti Mälkki
Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu. Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05bootblock: Add TS_START_BOOTBLOCK and TS_END_BOOTBLOCKKyösti Mälkki
Change-Id: I5617e5d9b7238ad7a894934910a3eae742d2d22d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36594 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05cpu/ti/am335x: Extend monotonic timer to early stagesKyösti Mälkki
It is actually all completely broken, dmtimer.c is not really implemented. Change-Id: Ifb3f624930c9ef663fae30cd5ddcb1d3d46f06b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05drivers/intel/fsp2_0: Hide CONFIG_FSP_CARArthur Heymans
CONFIG_FSP_CAR should not be a user visible option, but depends on the choice presented in the soc Kconfig. This also removes the dependencies on ADD_FSP_BINARIES. You need to included those for other stages too so there is no need to make this requirement explicit for FSP-T. Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-05soc/intel/common: Don't link CAR teardown in romstageArthur Heymans
This is done in postcar stage. This also assumes CAR tear down will always be done in postcar stage. Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05mb/google/kahlee/treeya: Update STAPM parameters for TreeyaPeichao Wang
Tune stapm percentage from 80 to 68 and time from 250 second to 90 second make them meet Lenovo temperature spec. BUG=b:143859022 TEST=build firmware and install it to DUT and run fishbowl 1000, check temperature whether meets spec. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-04mb/asrock/h110m/devicetree: fix VR config infoMaxim Polyakov
Removes unnecessary information about the Ring Sliced VR configuration from another board with FSP1.1 (which is no longer supported). Change-Id: Ia2b90d9ede782852c2127da972333bada378b217 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04superio/nuvoton/nct5539d: use SuperIO ACPI generatorMaxim Polyakov
Adds SuperIO SSDT ACPI generator[1] support. Not tested on real hardware. [1] https://review.coreboot.org/c/coreboot/+/33033 Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04mb/asrock/h110m: use SSDT generator for SuperIOMaxim Polyakov
Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D SuperIO, dropping the need to include code from the superio.asl, which was inherited from another chip (NCT6776) and required fixes. SSDT gen support for Nuvoton NCT6791D chip was added in the previous patch [2]. [1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36379 Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04superio/nuvoton/nct6791d: use SuperIO ACPI generatorMaxim Polyakov
Adds SuperIO SSDT ACPI generator[1] support. It has been tested on Asrock H110M DVS motherboard [2]. [1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36381 Change-Id: Idad66546168bbd26f0a4241deb66e5bfd83367af Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04google/auron: hook up libgfxinitMatt DeVillier
Internal/external displays functional on all variants other than Samus. Unable to verify external outputs on Samus (USB-C using DP/HDMI adapter). Test: build/boot lulu variant with libgfxinit, verify internal/ external displays functional prior to OS display driver loaded. Both linear framebuffer and scaled VGA text modes functional. Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel: skl,cnl,icl: consolidate ebda and memmapMichael Niewöhner
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code. Tested successfully on X11SSM-F Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSPMichael Niewöhner
Instead of doing our own calculations, rely on TOLUM returned by FSP for cbmem_top. This (hopefully) saves us from making mistakes in weird calculations of offsets and alignments. Further this makes it easier to implement e.g. SGX PRMRR size selection via Kconfig as we do not have to make any assumptions about alignments but can simply pass (valid) values to FSP. Tested successfully on X11SSM-F Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04sb/intel: Use defined CONFIG_HPET_ADDRESSElyes HAOUAS
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04nb/intel: Use defined DEFAULT_RCBAElyes HAOUAS
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel: Remove unused codePatrick Rudolph
Delete acpi_create_intel_hpet() which has been replaced by acpi_write_hpet() in the corresponding soc folders some time ago. Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph
Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04nb/intel/nehalem: Fix 'dead assignment'Elyes HAOUAS
Dead increment spotted out using clang-tools. Value stored to 'some_delay_3_halfcycles' is never read. Change-Id: I8133f9e8786006bd278d281a132b6a2bd863a967 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04cbfs: read header offset as explicitly LEMarty E. Plummer
le32_to_cpu spits out uint32_t on BE targets, cast it. Change-Id: Idc99b0c133faa2aa15d06f998e7371d332ffa490 Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-04mb/google/hatch: update DLL values for KindredJamie Chen
Update emmc DLL values for Kindred BUG=b:131401116 BRANCH=none TEST=Boot to OS 100 times on Kindred EVT Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-11-04soc/intel/broadwell: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: I6d8d04289254317af8d7cc55c89431d408414384 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/*/*/others: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: Iabfd680fdb50534e6b9f6cfdecda9f8de0f8a610 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04soc/intel/{braswell,baytrail}: Use sb/common/intel/platform.aslArthur Heymans
Change-Id: I64a27cb080838c986a12a40c80d0c91824b9d04c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04sb/intel/lynxpoint: Use sb/intel/common/platform.aslArthur Heymans
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: Ifc0799d26394a525d764fb4ffc096b48060ee22f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-04include: Remove EC_EVENT_* from elog.hYu-Ping Wu
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_* macros defined in ec_commands.h, which is synchronized from Chromium OS ec repository. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I12c7101866d8365b87a6483a160187cc9526010a Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-04mb/supermicro/x11-lga1151-series: drop console guard in bootblockMichael Niewöhner
To make debugging possible in a fallback setup, the serial console must be set up in bootblock, thus drop the guard. Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36602 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04mb/supermicro/x11-lga1151-series: use new console delay Kconfig optionMichael Niewöhner
This replaces the hardcoded delay by the new Kconfig option. Change-Id: I8bf4ef7ad9beea7b3dc22e1567623a423597eff9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04superio/aspeed/common: add workaround for serial routing delay quirkMichael Niewöhner
Some mainboards with an ASPEED BMC do the serial routing setup in the BMC boot phase on cold boot. This results in scrambled console output when this is not finished fast enough. This adds a delay of 500ms as workaround in the BMCs uart setup that can be selected at mainboard level. A user may disable the workaround when using another BMC firmware like OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup. Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04arch/mips: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This allows to use a common cbmem_top implementation. Change-Id: I85efe3899607854c36d0ec594868f690eb724a7f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/nvidia/tegra210: Populate _cbmem_top_ptrArthur Heymans
On this platform the ramstage is run on a different core so passing cbmem_top via calling arguments is not an option. To work around this populate _cbmem_top_ptr with cbmem_top_chipset which is also used in romstage. Change-Id: I8799c12705e944162c05fb7225ae21d32a2a882b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36557 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04arch/ppc64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This avoids the need for a platform specific implementation of cbmem_top. HOW TO TEST? There is no serial console for the qemu target... Change-Id: I68aa09a46786eba37c009c5f08642445805b08eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04cpu/intel/car/p4-netburst: Remove delay loopsKyösti Mälkki
While commented as 10 ms + 250 us, those delay loops actually accounted for a total of 840 ms. And they seem unnecessary as followup code has potentially infinite retries when polling for status changes. Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x. Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04cpu/intel/em64t101: Add Nehalem to compatibility listArthur Heymans
Change-Id: I15a1c824b92e18f9963c60659ead92c988d1239b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04cpu/intel/smm/gen1: Deal with SMM save state compatibilityArthur Heymans
Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/*/*{i82801ix}: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: I9150db163131d4c3f99a4e0b6922a61c96a6d6e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/*/*{bd82x6x/ibexpreak}: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: I36095422559e6c160aa57f8907944faa4c192dee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04sb/intel/common/platform.asl: Remove setting unused GNVSArthur Heymans
Change-Id: I842af0a0e6435d33759649065b2b5a6f6d35071d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04sb/intel/i82801jx/nvs.h: include required headerArthur Heymans
u8, u16, ... are defined in stdint.h. Change-Id: I045438a7e754d4da936cf2ded411d055f2f69b45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36556 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04nb/intel/x4x/x4x.h: Include iomap.hArthur Heymans
This is needed for the definition of the MCHBARx() macros. Change-Id: I654344451c0568f306f39365fd07371b2d6cff04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36555 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04sb/intel: Move 'smbus.asl' to common placeElyes HAOUAS
Change-Id: Ia5b148c54224269bda98afe7c8a2c22c10a3bf56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04mb/lenovo/{x200,t400}: Add VBOOT supportArthur Heymans
Tested on thinkpad X200 with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW selected, the RW_A slot is properly selected unless the FN button is pressed. 600+ms are spend waiting for the EC to be ready. Change-Id: I689fe310e5b828f2e68fcbe9afd582f35738ed1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35998 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04mb/google/drallion: Update GPIO tableEric Lai
Follow latest GPIO table to change gpio. BUG=b:143728355 BRANCH=N/A TEST=build pass Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-04mb/google/drallion: Correct GPP_E7 as stop pinEric Lai
Current design reset pin is connected to PLTRST. GPP_E7 is stop pin for touch. Reserve reset pin for next stage implement. BUG=b:143733039 BRANCH=N/A TEST=check touch screen can work properly Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-04mb/google/drallion: fix GPP_E16 glitch when enter S5Eric Lai
Set GPP_E16 reset to DEEP. BUG=b:143057255 BRANCH=N/A TEST=Measure GPP_E16 from S0 to S5 has no glitch Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04vendorcode/eltan/security: Correct debug outputWim Vervoorn
Correct debug ouput in tpm2_get_capability_pcrs. BUG=N/A TEST=build Change-Id: Ibd12c9dc22980f21ecba204729c5da0d11618e12 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36484 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04vendorcode/eltan/security: Address layout issuesWim Vervoorn
Corrected several layout issues in the mboot.c file. BUG=N/A TEST=build Change-Id: I1599c7be075130345f018a08bede3eb849129a1c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-04smbios: Create a type for smbios_enclosure_typeMathew King
Add a name to the SMBIOS enclosure type enum and use it as the return type for smbios_mainboard_enclosure_type. BUG=b:143701965 TEST=compiles Change-Id: I816e17f0de2b0c119ddab638e57b0652f53f5b61 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36516 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04arch/x86/Kconfig: drop unused BOOTBLOCK_SAVE_BIST_AND_TIMESTAMPElyes HAOUAS
Change-Id: I199a4b7771192abf7e7489e84db43b04776dd7b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36509 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04vendorcode/eltan/security: Use custom hash for little endian onlyWim Vervoorn
Only use the custom hash routine when we need little endian. Rename the function as well as it is little endian only now. BUG=N/A TEST=tested on fbg1701 board. Change-Id: I037fa38c5961dab7a81e752c1685da2dc6b33d12 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-04mb/facebook/fbg1701: Add logo to the menuWim Vervoorn
Allow the user to enable and disable the logo from make menuconfig. The file can be selected as well. BUG=N/A TEST=build Change-Id: I630a9d14308131c180adaaa9e1fa5e6e11c3c61c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-04vendorcode/eltan: Cleanup Kconfig filesWim Vervoorn
The vendorcode/eltan and vendorcode/eltan/security directories were both adding the mboot and verified_boot Kconfigs. BUG=N/A TEST=build Change-Id: I6b5f19b4660d60345391b7320ce42466fd2cc769 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36479 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Make use of "all-y"Subrata Banik
This patch makes use of "all-y" in order to replace all common stage (bootblock, verstage, romstage, postcar, ramstage) files inclusion in Makefile.inc Change-Id: I11001d0d381ec9c1df41bc331da845f51e666a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36546 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Add alignment check for TSEG base and sizeSubrata Banik
This patch ensures to not set SMRR if TSEG base is not align with TSEG size Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Set DCACHE_BSP_STACK_SIZE default ~129KiB unconditionallySubrata Banik
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other default value than 129KiB (128KiB for FSP and 1KiB for coreboot) Change-Id: I856f7e48a4a1e86eb082b9e772e0776664edca51 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36538 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Remove unused headersSubrata Banik
This patch removes inclusion of unused headers from soc/intel/icelake Change-Id: Icb653dee7992538aadf98d84adadd081f816fd01 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36536 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOPSubrata Banik
This patch replaces BIOS OpRpm execution checks from CONFIG_INTEL_GMA_ADD_VBT to CONFIG_RUN_FSP_GOP as adding VBT files doesn't mean GFX PEIM is going to execute to initialize IGD. Change-Id: Ic76529ba11f621f644d4472be6cbbc34682f00bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04soc/intel/icelake: Clean up report_cpu_info() functionSubrata Banik
This patch makes below clean up for report_cpu_info() function 1. Replace cpu_string with cpu_not_found 2. Assign default string "Platform info not available" to cpu_not_found string 3. Add array out of bound check while skiping leading white space in cpu brand string name Change-Id: I41c76eb93f0c5229c4a49aa041339b8ad51ad34a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36531 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03cpu/x86/mtrr/xip_cache.c: Fix inconsistent messageAngel Pons
Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03mb/intel/{i82801gx,x4x}: Don't select ASPM optionsArthur Heymans
These are likely not properly set up and L1 is not even supported on the desktop variant of the southbridge. This fixes observed instability on some PCIe GPUs. Change-Id: I70d3536984342614a6ef04a45bc6591e358e3abe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36576 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03arch/arm: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03arch/x86: Use the stage argument to implement cbmem_topArthur Heymans
Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and a pointer to the top of lower memory if often passed via lower memory (e.g. EBDA) or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A very generic solution is to pass cbmem_top via the program argument. It should be possible to implement this solution on every architecture. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. TESTED on qemu-x86. Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-03boot_state: Reduce precision of reported timesKyösti Mälkki
When diffing boot logs, lines reporting times spent in each boot_state always get highlighed due the little fluctuation in microsecond-scale. Reduce the logged precision to milliseconds to avoid that. Change-Id: I7a27d6c250d8432131f30e9a4869cb45ad75d9fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-03intel/quark: Switch to TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I5ea899863c5b9ed516a55ba2e7524dd33a6f651d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36554 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03intel/broadwell: Switch to TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I01b73e20c8af1b00175dc6d9ee56e6b33ac5768d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36537 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-02nb/intel/gm45: Add VBOOT supportArthur Heymans
Change-Id: I943723da7167a47f514eda19fb9b71b8f56c2d32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35997 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-02cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.Arthur Heymans
Tested on Thinkpad X200: the romstage execution speeds are back to pre-C_ENVIRONMENT_BOOTBLOCK levels. Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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