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2018-03-07soc/amd/stoneyridge/Kconfig: Create a power restore optionRichard Spiegel
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL that's not used at all and has no control. It's also not used in the build process. Remove the define from sm.c, create a true Kconfig definition and use it to define if power should be restored after a power failure/recovery. BUG=b:72873003 TEST=Build kahlee. Use serial output to check what is being programmed to RTC shadow. Build with and without selecting the Kconfig parameter. Then remove serial output and leave the parameter unselected (always S5 at power recovery). Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07soc/intel/braswell: add LPEA resources to southcluster.aslMatt DeVillier
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources per Inte'sl CHT Tianocore reference code. Test: boot Windows on google/edgar, observe LPEA device working properly. Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wakeSeunghwan Kim
As per the latest schematics, this change configures GPP_B0 as wake source for WLAN. BUG=NONE BRANCH=master TEST=emerge-nautilus coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b Reviewed-on: https://review.coreboot.org/23526 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07mb/scaleway/tagada: populate smbios informationJulien Viard de Galbert
This is done by overriding the weak functions from smbios.c Some values are hardcoded as they are characteristics of the Tagada system. Other are retrieved from the BMC through the bmcinfo interface. Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23843 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07smbios: Extend Baseboard (or Module) Information (type2)Julien Viard de Galbert
Add more information on baseboard as described in SMBIOS Reference Specification 3.1.1. Change-Id: I9fe1c4fe70c66f8a7fcc75b93672421ae808bf1b Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Override baudrate with bmcInfoJulien Viard de Galbert
Change-Id: Idd93b64ef91a569127a0713fdb499dff2a1f11db Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Implement console loglevel override using bmcInfoJulien Viard de Galbert
Change-Id: I0093cfafe7eaa4a4381e67c9b871fdf28abc470d Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Add bmcInfo interfaceJulien Viard de Galbert
This interface gives access to configuration information stored in flash by the Tagada BMC before booting the SoC. Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/google/poppy/variants/nami: Add memory detection logicShelley Chen
Alkali will use LPDDR3, so need to have Nami support both DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO. BUG=b:73514687 BRANCH=None TEST=None Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add spd filesShelley Chen
Add spd files for LPDDR3 based on info received from factory team. BUG=b:73287172 BRANCH=None TEST=None Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07soc/amd/stoneyridge: clean up southbridge.cGarrett Kirkendall
* Limit dependency on vendorcode header files and use defines from iomap.h and southbridge.h * Factor out to functions, device power-on code for AMBA and UART. BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnbGarrett Kirkendall
Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h and southbridge.h BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07soc/amd/stoneyridge: Add southbridge definitionsGarrett Kirkendall
* Add definitions to iomap.h for AMD ACPI MMIO base addresses. * Add FCH AOAC registers for enabling FCH devices. * From: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h, Models 70h-7Fh Processors Rev 3.04 BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07ec/google/chromeec: Fix typo preventing PD EC firmware inclusionBen Pye
Change-Id: I12ae0d556c43d3d6537cac5d8f640e6a960101ae Signed-off-by: Ben Pye <ben@curlybracket.co.uk> Reviewed-on: https://review.coreboot.org/25017 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06soc/intel/braswell: increase LPEA fw allocation to 2MiBMatt DeVillier
Increase memory allocated for the LPEA firmware from 1MiB to 2MiB to match Intel CHT reference code and fix Windows functionality. Test: boot Windows on google/edgar, observe no error in Device Manager for LPEA audio device due to BAR2 resource allocation. Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06soc/intel/braswell: fix PCI resource PMAX/PLEN valuesMatt DeVillier
Without PMAX correctly set, the calculation for PLEN is incorrect, leading to a Windows BSOD on boot. Correct PMAX using code from Baytrail SoC, setting PMAX to (CONFIG_MMCONF_BASE_ADDRESS - 1). Test: Boot Windows 10 on google/edgar without BSOD. Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24985 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06google/snappy: enhance CCD type-A USB 2.0 phy strengthKevin Chiu
Alan(11")/BigDaddy(14") right type-A(port#2), CCD(port#4) are occasionally undetectable. USB 2.0 phy needs an override to enhance drive strength. right type-A port#2 PERPORTPETXISET: 4 PERPORTTXISET: 4 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 CCD port#4 PERPORTPETXISET: 7 PERPORTTXISET: 7 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I2b18c11709280d00ec3a6ef10f93a416acb4fb45 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/24969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06soc/intel/skylake: Remove MCFG constantsDuncan Laurie
The MMCONF base address and length are set in Kconfig so it does not need to be redefined by the SOC as the code can just use the Kconfig variable directly. Tested on a fizz board to ensure MCFG is still created properly. Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24975 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06soc/intel: Fix MCFG end bus numberDuncan Laurie
The ACPI MCFG table is generated with a static end bus number of 255, which expects that the reserved range in E820 is 256MB. However the actual MCFG range is configurable with Kconfig, so these two values may not match when the OS tries to determine the range: PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!) acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Instead of forcing the end bus number to be 255 use the Kconfig value to set it based on the current configuration. Tested on a fizz device to ensure that the kernel no longer complains: PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24974 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06mb/google/fizz: Skip FSP init for UART 0Duncan Laurie
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. coreboot is setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device. The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots. Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06soc/amd/stoneyridge: Add ST/CZ SMBus device idMartin Roth
The SMBus PCI device ID for Stoney wasn't updated when the code was pulled over from hudson. This means that the IOAPIC wasn't being initialized in coreboot. BUG=b:74070580 TEST=Boot Grunt, see IOAPIC init messages in console. Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/24930 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06Revert "mainboard/google/meowth: enable PCH iSCLK"Lijian Zhao
This reverts commit 2e81f394cffc6f1993a5f004356ed35f6064fe48, as it will have side effect that will make system shutdown failure. System will not enter S5 sleep state, instead a global reset will be generated. Once camera driver ACPI framework ready, isclk programing will be moved into APCI method, in _PS3, isclk will be turned off to save power. BUG=b.72532565 BRANH=master TEST=Apply the changes and flash coreboot, on meowth devices, issue "halt" in OS stage, system can shutdown successfully. Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25006 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05ec/chromeec: Fix check for UHEPI supportMatt DeVillier
Commit 1dfc2c3 [google/chromeec: Enable unified host event programming interface] added support for UHEPI, but google_chromeec_is_uhepi_supported() incorrectly treats negative error return codes from google_chromeec_check_feature() as supported. Fix this check to only treat positive return values as supported, as per the original intent. Test: boot google/lulu, verify cbmem console reports UHEPI not supported even if feature check returns error code, verify lid/kb wake events correctly wakes the device from S3/sleep. Change-Id: I7846efb340bc1546b074e8502daf906c444bd146 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05mb/google/poppy: Allow use of optional secondary SPDFurquan Shaikh
This change adds support for variants to use secondary SPD if required. This enables a variant to have different types of memory supported using the same image. BUG=b:73514687 Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05mb/google/poppy/variants: Set pch_trip_temp to 75CFurquan Shaikh
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-05cpu/x86/mp_init: Increase AP check-in time-out to 1secondFurquan Shaikh
Currently, the AP check-in time-out in bsp_do_flight_plan is set to 100ms. However, as the number of APs increases, contention could increase especially for resource like UART. This led to MP record time-out issues on KBL platform with 7 APs and serial-console enabled BIOS image. This change increases the time-out value to 1 second to be on the safer side and let APs check-in before continuing boot. BUG=b:74085891 TEST=Verified that MP record time-out is not observed anymore on Nami. Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05soc/intel/common/block/smm: Add configurable delay before entering S5Furquan Shaikh
This change adds a configurable delay in milliseconds before SLP_EN is set in SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power button SMIs. On some platforms (Nami, Nautilus), it was observed that power button SMI triggered by EC was competing with the SLP SMI triggered by keyboard driver. Keyboard driver indicated power button press which resulted in depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power button press also causes the EC to send a pulse on PWRBTN# line, which is debounced for 16ms before an interrupt is triggered. This interrupt was generated after SLP_SMI is processed which resulted in the device waking back up from S5. This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay before SLP_EN is set for S5. This change should only affect CHROMEOS boards as the config option will be 0 in other cases. BUG=b:74083107 TEST=Verified that nami, nautilus do not wake back from S5 on power button press at dev mode screen. Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05lib: Add delay.c to smmFurquan Shaikh
BUG=b:74083107 Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-03nb/intel/i945/gma: Log configured VGA modePaul Menzel
This is useful information, when debugging problems related to graphics. Change-Id: Iacb0ae5f012207192379fd07e91f4687ec32cdfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/23807 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02sb/intel/common: Fix conflicting OIC register definitionNico Huber
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-02console: only allow console messages after initializationAaron Durbin
The console subsystem allows printk() to be called prior to the drivers and/or infrastructure is completely set up. In those situations don't allow messages to be added until the console is completely initialized. BUG=b:73898539 Change-Id: Idc3840132d7f95f8e22045d7484c528d828bb0de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/24917 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02mb/google/zoombini/variants/meowth: Enable NVMeBora Guvendik
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3. BUG=b:72120814 TEST: Boot to OS via NVMe Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/23208 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02mb/hp: Enable additional ports at WWAN slot for ElitebooksIru Cai
2760p: enable PCIe 8470p: enable mSATA 8460p: enable PCIe, also add comments according to circuit diagram 2570p: comment for some USB ports Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-02ec/google/chromeec: Add note before error messageMartin Roth
When clearing events from the EC, an error is returned when we try to clear an event that doesn't exist. This is normal, but can be distracting when trying to track down an error, so add a message saying that the error is expected. BUG=None Test=Build Grunt with SMM debug enabled. See message before "EC returned error result code 1". Change-Id: Ib2e684e357e821c795de4b59658432c91a8d63fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/24914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-02mainboard/google/zoombini/variant/meowth: enable speed shiftNick Vaccaro
BUG=b:73817825,b:69011806 BRANCH=master TEST=Build and flash to meowth, verify cpufreq shows up in kernel for all cores : localhost ~ # find / -name "cpufreq" /sys/devices/system/cpu/cpu3/cpufreq /sys/devices/system/cpu/cpu1/cpufreq /sys/devices/system/cpu/cpufreq /sys/devices/system/cpu/cpu2/cpufreq /sys/devices/system/cpu/cpu0/cpufreq /sys/module/cpufreq /usr/share/laptop-mode-tools/modules/cpufreq Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/24902 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/reef/sand: Override USB2 phy settingsKatherine Hsieh
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-sand coreboot chromeos-bootimage Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/23879 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01soc/intel/broadwell: Generate ACPI DMAR tableMatt DeVillier
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01soc/intel/broadwell: Enable VT-d and X2APICMatt DeVillier
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01mainboard/google/meowth: Turn on DBC over USB3.0Lijian Zhao
Intel DCI (direct connect interface) allows debug Intel target using USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0 only. BUG=None TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot image. Using DAL to halt/run CPU. Change-Id: I39e68dabfcb9e659733019334299e562eee3681d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-03-01mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa settingSeunghwan Kim
If switch to VT2 on nautilus, screen flicker appears. We found if we rollback the change of slew rate setting, then the flicker issue will be gone: https://review.coreboot.org/c/coreboot/+/22588 But nautilus board needs slew rate tuning to reduce EE noise, so we decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of rollback the whole change of the CL:22588. It can remove the flicker on VT2. BUG=b:71397040 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-01mb/google/reef: Override USB2 phy settingsTim Chen
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/23878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/coral: add usb2 phy setting override for some variantsSheng-Liang Pan
Due to there are some chances USB devices can not be detected. USB2 port#1 and #4 PHY register need to be overridden for variants Santa/Lava/Blue/Bruce/Astronaut. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I401905685cc3078df657919b162272c3de320296 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/23881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-01mb/{amd/gardenia,google/kahlee}: Initialize GPIOs earlierJustin TerAvest
The GPIOs for PCIe reset and power enable for WLAN must be set up before amdinitearly for wlan to function. BUG=b:73898539 TEST=Boot, see WLAN controller in lspci Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24916 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01soc/amd/stoneyridge: Remove printk for GPIOJustin TerAvest
The printk() calls in sb_program_gpios() aren't necessary, and incur a 13 second delay if the function is called from bootblock_mainboard_early_init(). This commit removes them so GPIOs can be set up earlier. TEST=call sb_program_gpios from bootblock_mainboard_early_init BUG=b:73898539 Change-Id: I064291decf47d86132e36469e029b3262ec20172 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24915 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/scaleway/tagada: set SMBIOS Enclosure Type in KconfigJulien Viard de Galbert
Change-Id: I7acffcf3fc36742c77ce00b253f5b0a68d435798 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24911 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01smbios: Add option to select the enclosure typeJulien Viard de Galbert
This allows for a mainboard to change the value from its Kconfig. The default value is still SMBIOS_ENCLOSURE_DESKTOP (0x03) or SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set. Change-Id: I35bc913af69565531831746040a0afe0cabe1c58 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-28drivers/intel/fsp2_0: Fix build error while DISPLAY_HOBS is selectedSubrata Banik
This patch fixes brokenness issues in coreboot with CONFIG_DISPLAY_HOBs config selection due to recent UDK2017 package changes. TEST=Build and boot UDK2017 platforms with DISPLAY_HOBS select. Change-Id: I5c779c86870c62253d64c6af456bf017553e269c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mainboard/google/zoombini: consolidate SPD makefilesNick Vaccaro
- consolidate commonality in meowth and zoombini's SPD makefiles into a common zoombini/spd/Makefile.inc - move all SPD hex files into zoombini/spd directory - move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc BUG=b:69011806,b:71776625 BRANCH=master TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot' compile and boot successfully. Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23874 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28skylake: Fix unwanted disablement of ACPI UPWEKane Chen
In PORTSC, Port Enabled/Disabled(PED) is RW1CS. When there is a USB device attached on system, current UPWE method will set 1 to PED, this will cause port disabled as it's RW1CS. This change is inspired by xhci_port_state_to_neutral in linux driver. It will mask all RO and RWS bits and set WDE and WCE. BUG=b:70777816 TEST=System won't be awakend from s3 automatically when usb devices is attached. Also system can be awakend by hotplugging usb devices under S3. Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mb/google/poppy/variants/nami: Enable elan touchscreenCrystal Lin
BUG=b:72062694 BRANCH=master TEST=Verify touchscreen on nami works with this change. Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mb/google/octopus: Add LPDDR4 memory initRavi Sarawadi
Add LPDDR4 initialization support. BUG=b:73136980 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28soc/intel/skylake: Add support to print ME versionFurquan Shaikh
This change adds a boot state callback to print ME version after DEV_ENABLE is complete. Information is printed only if UART_DEBUG is enabled because talking to ME to get the firmware version adds ~1 second to boot time. TEST=Verified on Soraka that ME version printed is correct. Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-26soc/amd/stoneyridge: Refactor northbridge resource allocatorMarc Jones
The resource allocator was overly complicated due to porting from a multi-node resource allocator. It had some assumptions about the UMA memory and where it would be located. The refactored allocations account for UMA being reserved above 4GiB. TEST=Check CBMEM table has correct RAM regions. Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common: Save the UMA settings from AGESAMarc Jones
Save the UMA base and size settings returned by AGESA in amdinitpost(); Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26mainboard/google/zoombini: enable 4 coresNick Vaccaro
BUG=b:70731385 BRANCH=master TEST='emerge-meowth coreboot chromeos-bootimage', flash image.serial.bin to meowth board, boot into kernel, and verify 4 cores are running. Change-Id: Ia233e41acd19b317f82433a5d41d84ea934a66c4 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23839 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26src/arch/x86/smbios.c: Fix type 17 part numberRichard Spiegel
Some DIMMs have invalid strings when it comes to device part number (bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ), all others should be ASCII. Create a test that detects invalid strings and replace invalid characters with *. If a replacement was made the output string then must be <Invalid (replaced string)>. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Use code to examine SMBIOS, while testing different valid and invalid strings. Remove string injection before committing. Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common/block/pi/amd_late_init.c: Fix part numberRichard Spiegel
Kahlee DIMM have invalid string when it comes to part number (bytes 0x149-0x15c). We currently force a NA string, but grunt has the proper strings. Just let the string go through, and a second commit within smbios.c will be responsible for testing the string and taking proper action. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Remove string injection before committing. Change-Id: I427262873f9ec80f459245e5f509e28a68de3074 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26ec/google/chromeec: Remove extra newline characters from printkFurquan Shaikh
This change removes extra newline characters from print statements for wake masks. Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointerWerner Zeh
Coverity scan has found an error where a NULL pointer is dereferenced. The bug would happen if the devicetree does not contain a valid entry for PCA9538. In this case the code * if (dev->path.i2c.device == PCA9538_SLAVE_ADR) would dereference to a NULL pointer. This patch fixes this issue. Thanks coverity! Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL)) Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-23mb/google/fizz: Enable PCIe port 11, 12Zhongze Hu
Our CFM daughter card would like to use individual PCIe lanes for two different devices on the card. dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector on fizz to meet the requirement: https://chrome-internal-review.googlesource.com/571936 We also need to enable the ports on device tree. BUG=b:72523836 TEST=none BRANCH=fizz Change-Id: Icded9850d833752680e0174b6c476e657817b319 Reviewed-on: https://chromium-review.googlesource.com/923867 Commit-Ready: Zhongze Hu <frankhu@google.com> Tested-by: Zhongze Hu <frankhu@google.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924860 Commit-Queue: Shelley Chen <shchen@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/23845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-02-23console: Introduce a way for mainboard to override the loglevelJulien Viard de Galbert
This change adds a config option to allow mainboard to override the console loglevel. When the option is set, the platform has to define the function get_console_loglevel returning a valid loglevel value. This allows a mainboard to sample a GPIO to switch the loglevel value between different environments (qualification vs production) without re-flashing. Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-22mb/google/kahlee/mainboard.c: Fix mainboard_picr_dataRichard Spiegel
While programming interrupts, a message "perhaps this device was defined wrong?" shows up twice. This is caused because some devices have interrupt programmed for APIC mode, but not for non-APIC mode. Fix mainboard_picr_data table by identifying devices programmed with value 0x1F while programmed differently on mainboard_intr_data table. Do so only for devices that are used by kahlee or interrupt required by old OS. BUG=b:70788755 TEST=Build and run kahlee, Verify that message disappears from serial output. Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22mb/google/kahlee: Use GPIO macros for baseboardJustin TerAvest
This commit uses newly defined macros to make it easier to read which iomux function pads are being configured to use. TEST=Booted grunt, confirmed display backlight came on. BUG=b:72875858 Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22soc/amd/stoneyridge: Add readable macros for GPIOJustin TerAvest
This commit defines a set of macros for defining GPIO configuration that are easier to read than the raw iomux function values used today. TEST=None BUG=b:72875858 Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22mb/google/kahlee: Correct bad gpio entryJustin TerAvest
There's no need to set the output enable here; this is already handled by the native function. I'm making this correction in this change to prevent the GPIO pin descriptions from getting confusing. BUG=b:72875858 TEST=Booted, confirmed S5_MUX_CTRL high with and without this change. Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mainboard/google/meowth: enable PCH iSCLKLijian Zhao
Turn on PCH iSCLK for meowth platform. BUG=None TEST=Boot up into OS and check register programming with iotools, the command is iotools mmio_read32 0xfdad8000, returned value is 0x03. Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23368 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22device/ddr2,ddr3: Rename and move a few thingsArthur Heymans
In order for ddr2.h and ddr3.h to be included in the same file it cannot have conflicting definitions, therefore rename a few things and move some things to a common header. Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-02-22mainboard/google: Disable big, pit, and ryu ec buildsMartin Roth
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed from the latest EC codebase, so don't try to build them by default anymore. Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao
Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. BUG=b.71586766 TEST=Install OS into EMMC successfully on meowth P1 platform. Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22soc/intel/cannonlake: Add emmc/sdc port idLijian Zhao
EMMC and SD Controller port id listed here, the port id definition came from Cannonlake BIOS Writer Guide 570374. BUG=None TEST=None Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22mainboard/google/zoombini: Add config for meowth audioSathyanarayana Nujella
Add NHLT and dt support for meowth with max98373 amp. BUG=b:71724897 TEST='emerge-meowth coreboot' compiles correctly TEST=check SSDT and verify entries for max98373 TEST=check NHLT ACPI tables included blobs for max98373 Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-22soc/intel/cannonlake: Add more HDA Audio Link settingsLijian Zhao
Since FSP version 7.x.11.43, more HDA Audio link options are exposed, so included that into coreboot. Users can modify that base on platform implementations. BUG=None TEST=Boot up with debug build version FSP and check the debug print result on meowth platform. Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-22soc/intel/cannonlake: Add provision to make CSME function disable in SMM modeSubrata Banik
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22soc/intel/common/block/smm: Add option to have SOC specific SMI Handler at ↵Subrata Banik
finalize() This patch ensures common code provides an option to register a SOC specific SMI handler before booting to OS (specifically during ramstage). Change-Id: I50fb154cc1ad4b3459bc352d2065f2c582711c20 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tung Lun Loo <tung.lun.loo@intel.com>
2018-02-22soc/intel/common/block/pcr: Add function for executing PCH SBI messageSubrata Banik
This function performs SBI communication Input: * PID: Port ID of the SBI message * Offset: Register offset of the SBI message * Opcode: Opcode * Posted: Posted message * Fast_Byte_Enable: First Byte Enable * BAR: base address * FID: Function ID * Data: Read/Write Data * Response: Response Output: * 0: SBI message is successfully completed * -1: SBI message failure Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23809 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22device: Include devicetree in SMM stageSubrata Banik
Allow bootblock to get access to the entire static device tree as other stages can access independently. TEST=SMM code now can access devicetree.cb variables. Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-22skylake: remove legacy devices from ACPIPatrick Georgi
Once the FADT reports that they don't exist it makes no sense to have them in ACPI's device tree. Change-Id: Ice82f0de592b6ca955148479fecc8506a7cdcddc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: dhaval.v.sharma@intel.com Reviewed-on: https://review.coreboot.org/23835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-22soc/intel/skylake: Do not set ACPI_FADT_LEGACY_DEVICESFurquan Shaikh
SKL/KBL PCH does not support legacy devices. This change removes the setting of ACPI_FADT_LEGACY_DEVICES flag in FADT for SKL/KBL. It helps Linux kernel to disable controllers required to support legacy devices only e.g. i8237 DMA controller. BUG=b:72679357 Change-Id: Ie2a85a719997157f52b0eab7254689f5a56ba05b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21mainboard/google/kahlee: Add tis_plat_irq_statusChris Ching
For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21soc/amd/stoneyridge: Add functions for GPIO interruptsChris Ching
Add a function to configure interrupt settings for a GPIO. This does not currently configure GEVENT signals. The second function returns the GPIO interrupt status and clears the flag if set. BUG=b:72838769 BRANCH=none TEST=Update and test interrupt settings for GPIO_9 on grunt Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-21soc/amd/stoneyridge: Add UMA save functionMarc Jones
Save the UMA values from AGESA to use in resource allocation in ramstage. Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23817 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZEArthur Heymans
Some assumptions are made with respect to CONFIG_ROM_SIZE being the actual size of the boot medium, e.g. when automatically creating an fmap with and RW_MRC_CACHE region. With this patch the user is warned when this is detected. Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20nb/x4x/raminit_ddr2: Refactor clock configuration slightlyJonathan Neuschäfer
The result is shorter and (IMHO) more readable code. Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20mb/google/poopy/variants/nami: Add Pmax settingGaggery Tsai
This patch adds the Pmax setting in device tree. The Pmax is from MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W. BUG=b:72138778 BRANCH=None TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20mb/google/kahlee/OemCustomize.c: Disable bank interleaveRichard Spiegel
AmdInitPost returns AGESA_WARNING. This is because AGESA by default enables bank interleaving, while the HW does not meet the requirements for it. Disable bank interleaving, thus clearing AGESA_WARNING. BUG=b:73118857 TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost() returned AGESA_SUCCESS". Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20mb/compulab: Mark Intense-PC as single board computer in board_info.txtJonathan Neuschäfer
Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/, the Intense PC does not look like a laptop. In its documentation it is described as "mini-PC" or "Single Board Computer". This patches moves the Intense-PC into the correct category on the Supported Motherboards page. Due to thermal considerations, I have not removed the "select SYSTEM_TYPE_LAPTOP" in Kconfig. Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC") Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20arch/riscv: Delegate the page fault exceptionsJonathan Neuschäfer
These exceptions were new in the Privileged Architecture spec 1.10. We need to delegate them to S-mode. Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer
Update encoding.h to the version shipped with spike commit 0185d36 ("Merge pull request #165 from riscv/small_progbuf"), and copy the license header from the LICENSE file. Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer
The RISC-V boot protocol foresees that at every stage boundary (bootrom to boot loader, boot loader -> OS), register a0 contains the Hart ID and a1 contains the physical address of the Flattened Device Tree that the stage shall use. As a first step, pass the bootrom-provided FDT to the payload, unmodified. Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Don't set up virtual memoryJonathan Neuschäfer
Due to changes in the RISC-V Privileged Architecture specification, Linux can now be started in physical memory and it will setup its own page tables. Thus we can delete most of virtual_memory.c. Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Make RVC support configurableJonathan Neuschäfer
In order to support RISC-V processors with and without the RVC extension, configure the architecture variant (-march=...) explicitly. NOTE: Spike does support RVC, but currently doesn't select ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't support RVC. Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Align trap_entry to 4 bytes, as required by specJonathan Neuschäfer
The RISC-V Privileged Architecture spec 1.10 requires that the address part of mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should be zero for now. Add the necessary alignment directive before trap_entry. Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20mb/emu/spike-riscv: Move usage instructions into Kconfig helpJonathan Neuschäfer
... and fix them in the process. The Kconfig help text seems to be a slightly better place for such documentation than a comment in Kconfig. Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20soc/nvidia/tegra210: add missing bl31 params to ATF configAndre Heider
The ATF tegra210 platform supports more than the currently used 'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h in the ATF tree. Add the missing parameters and set them accordingly. The passed UART id is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the same port for console output as coreboot. Successfully tested with UARTB. Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20soc/nvidia/tegra210: set up the clock of the chosen UARTAndre Heider
Don't always set up UARTA, but instead honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the chosen UART. Now the matching clock for the used UART is set up. (The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.) Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-20soc/nvidia/tegra210: add console UART helper functionsAndre Heider
These small helper functions aim at supporting the user setting CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx. Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1 Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>