summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2013-06-13AMD S3 resume: use a function to replace duplicated codeSiyuan Wang
In function OemAgesaSaveMtrr of 'src/cpu/amd/agesa/s3_resume.c', there are many code like this: msr_data = rdmsr(0x258); flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; Add a function write_mtrr to do this. Change-Id: Id6464e637db1758b07ac2d79d3be1375a8d49651 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3410 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. Write 1 to clear as spec says. I have tested on Thatcher The same change was done for AMD Parmer in commit »AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard' (03901124) [1]. [1] http://review.coreboot.org/#/c/3347/ (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1) Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3374 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13AMD: Kconfig cleanupKyösti Mälkki
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-13Add support for Intel Nehalem CPUVladimir Serbinenko
Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3395 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"Stefan Reinauer
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2 Reviewed-on: http://review.coreboot.org/3443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-12Add support for Intel Ibex Peak (Mobile 5) southbridgeStefan Reinauer
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3397 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Avoid tripping overheat alarm on X201 before ME bootsVladimir Serbinenko
Until ME boots (which takes seconds on X201) the reported temperature is 128 °C which triggers Linux overheat alarm which shuts down. Pretend temperature is 40°C until ME boots. Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3404 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Make acpi/ec.c usable in romstageVladimir Serbinenko
On X201 to enable EHCI debug you need to go through EC if USB power is disabled so we need to inclue ec.c. Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Radio and dock support in EC on X60 and X201Vladimir Serbinenko
Enable UMTS on Lenovo X60 and X201. Enable radios if no options are available. Enable dock on Lenovo X201. Based on my X201 branch. Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12am335x: Add struct `am335x_uart` for uart registersDavid Hendricks
Add a struct for referencing UART registers. The layout is quite strange on this chip, as the entire register space can take on three different meanings depending on the line control settings (in the LCR register) And to make things more confusing, some offsets reference different registers depending on if a read or a write operation is used. Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3319 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12usbdebug: Quirk for board aopen/dxplplusuKyösti Mälkki
This ancient board with Intel e7505 invalidates cache while it does HW scrubbing for ECC in romstage. This breaks usbdebug console and prevents system from booting. If both EARLY_CONSOLE and USBDEBUG are selected, skip ECC scrubbing under these rare conditions to boot system. Change-Id: I6cb43bf69af54119f4a582dcaf498dd941d4c62d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3385 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12usbdebug: Drop printk within console_init()Kyösti Mälkki
In case with EARLY_CONSOLE, this printk is called before any other console is configured to transmit data. This outputs garbage on CONSOLE_SERIAL as baudrate is not yet programmed. For case without EARLY_CONSOLE, the order in which different console drivers initialize is obscure. Might sometimes work properly. Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12usbdebug: Improve solving EHCI debug port problemsKyösti Mälkki
Add comment how one can debug the usbdebug hardware init. Do not send printk's to usbdebug console when one is debugging the usbdebug console initialisation itself. Change-Id: I21a285cb31cf64e853bc626f8b6a617bc5a8be19 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3382 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12Fix i82801a/b/c/d IOAPICKyösti Mälkki
Setting IRQ delivery to FSB got lost in the rebase process for commit e6143531. I captured following error on dmesg and this patch fixes it for i82801dx. ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found apic 0 pin 2) ... ....... failed. ...trying to set up timer as Virtual Wire IRQ... ..... works. Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3371 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dumpKonstantin Aladyshev
Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to GPIO0. Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3436 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11intel/bd82x6x/Makefile.inc: Revert duplicate addition of `usb_debug.c`Paul Menzel
Currently in Intel BD82x6x southbridge’s `Makefile.inc` the file `usb_debug.c` is added twice to the build. This was introduced in commit 4063ede3fb571110c3e65c321049cc2687cc54fa Author: Ronald G. Minnich <rminnich@google.com> Date: Mon Feb 4 20:31:51 2013 -0800 bd82x6x: Fix compiling with USB debug port support Reviewed-on: http://review.coreboot.org/2784 but was unneeded because it had been already added in the following commit. commit 4141993536039e0d45caeacb745a89d388f0724b Author: Sven Schnelle <svens@stackframe.org> Date: Sat Jul 28 08:52:44 2012 +0200 bd82x6x: Fix CONFIG_USBDEBUG Reviewed-on: http://review.coreboot.org/1376 Therefore basically revert that hunk. There is no policy on how to order these additions, so leave it to a possible separate commit, unifying this. Kyösti Mälkki suspects that these additions were meant for the Intel Lynx Point [1]. [1] http://review.coreboot.org/#/c/3424/ Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3425 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Fix cycle error in intel southbridges to display GPI statusKonstantin Aladyshev
Fix obvious mistake in cycle that displays GPI status I hope i found all duplicates of it. Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3435 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11am335x: Revert how the header load size is calculated to an earlier method.Gabe Black
The current method will treat hex values as 0 and would calculate the wrong size. This change switches back to an earlier method which used shell syntax to add the offset and size. Change-Id: I9fb2d9b323f113cc56a5ad2e38b47d2d22084f08 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3432 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-11winbond/w83627dhg: Add ACPI supportNico Huber
This is loosely based on Christoph Grenz' ACPI code for the W83627HF and makes use of the PnP super i/o ACPI framework. Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3288 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Start ACPI framework for PnP (super i/o) devicesNico Huber
I'm trying to make writing ACPI code for super i/o devices more comfortable. pnp.asl hosts some general cpp macros. The other four files are to be included in dsdt trees. They are controlled by cpp macros which should be defined/undefined before inclusion. Work was inspired by Christoph Grenz' ACPI code for the W83627HF. Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3286 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11am335x: Make the iROM load only the bootblock and ROM stage.Gabe Black
The bootblock and ROM stages are the only ones that are really required to be loaded in the quite limited on chip RAM during startup. Rather than load the whole image which requires everything to be small, load just the bootblock and the ROM stage, allowing the rest of the image to be arbitrarily large. Loading a minimal amount of stuff should also improve boot performance a little bit. Change-Id: I2fede63b8d3d8f0d880e4a692ae423021f8232b6 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3421 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10beaglebone: Expand "ROM" size to 4MB.Gabe Black
Now that the ROM size is decoupled from the size of the on chip RAM, it's size is now only constrained by the size of the medium it's loaded from and the memory it's being loaded into, probably GBs in both cases. Making it 4MB is a reasonable compromise between giving the payload lots of breathing room and wasting space on the source medium which won't be used. Change-Id: I80932e0d4ce2dad02c3879345382e7d6ba44503a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3422 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10beaglebone: Force on every other user LED to show that coreboot is running.Gabe Black
Until we get serial working, this is a good way to show that coreboot is running. It can be removed once we have better methods. Change-Id: I62d25e52aa88a97aba4c959538d680b67a0bbbb2 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Use MIN/MAX from stdlib.h instead of redefining themAlexandru Gagniuc
Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3431 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-10Add support for VIA EPIA-M850 boardAlexandru Gagniuc
EPIA-M850 can now boot linux. For a list of issues, see: http://www.coreboot.org/VIA_EPIA-M850 That's all folks. Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1228 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VIA VX900: Add minimal ramstage needed to boot linuxAlexandru Gagniuc
This is the minimal code needed to get past ramstage, load SeaBIOS, jump to GRUB2, and boot linux (or load memtest). See individual source files for the status of each individual component. Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3419 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Add DDR3 initializationAlexandru Gagniuc
The VX900 can be connected to either DDR2 or DDR3. On my board, it is DDR3, hence why there is no and will be no DDR2 code from my side. This is the raminit for DDR3 dimms for the VX900. I like the term "raminit" better than "memory training". This is a device, not a dog. What works and what doesn't is documented in the code. It does not make sense to hide that information in a commit message. Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3417 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10ramtest.c: Add silent ram_checkAlexandru Gagniuc
In some cases, we want a ram_check that does not die and does not clobber the terminal with useless output that slows us down a lot. Usage examples include Checking if the RAM is up at the start of raminit, or checking if each rank is accessible as it is being initialized. As with all other ram_checks, this is more of a "Is my DRAM properly configured?" test, which is exactly what we want for something to use during memory initialization. Change-Id: I95d8d9a2ce1e29c74ef97b90aba0773f88ae832c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3416 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10VX900: Add support for early romstageAlexandru Gagniuc
Add support for VX900 early initialization up until, but not including raminit. Add the basic infrastructure, add a romstrap table, and functionality to configure the CPU bus and SMBus. This code is necessary and sufficient to prepare us for raminit. Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3372 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10early_smbus: Add early SMBus implementation for VIA chipsetsAlexandru Gagniuc
Add a common implementation of SMBus functionality for early chipsets. Note however, that existing via chipsets are not ported to this code. Porting will require hardware testing to make sure everything is fine. This code is used in the VIA VX900 branch. Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/144 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10am335x: Build an omap style header and an image with it at the front.Gabe Black
Loading on an OMAP SOC requires that the first sector of the image have a configuration header, and, when not an execute in place image, an additional header which describes how big the image is and where it should be loaded. This change adds some infrastructure to statically build that header using C code, and to paste the header onto the front of coreboot.rom in a new top level target file called MLO. The configuration header we're using is as inert as possible, in line with what U-Boot is doing. I think it could be used to give additional configuration parameters to the built-in ROM on the SOC, but we don't need to do that, and there didn't seem to be any actual documentation how to do that. Because the header is built from C and is defined per CPU, it would be possible to include extra settings in other CPUs if desired. Adding a new top level build target is a bit disruptive, but should be contained to the am335x directory and not interfere with other mainboards. Change-Id: I06d346a4050c20963b3c7c6e8a152070bf2d145a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3332 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10ARM: Put the ROM stage into the image before other bits.Gabe Black
On ARM, there's frequently some firmware built into the SOC which runs first and which loads other firmware like Coreboot from some other media. To prevent the bootblock from having to know how to find and load the ROM stage from what may be a complicated source (sd card, netbooting, etc.), we can put the ROM stage immediately after the bootblock and ensure that they're both loaded at the same time. This change adjusts the Makefile.inc for ARM so that the ROM stage is put into the image before any other files so that we know it comes first. This changes the behavior of the CONFIG_UPDATE_IMAGE config option used by abuild, although it's not entirely clear whether that's still used. Change-Id: I832386243788156db5f5abbc9760a4e2026cf2cd Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3420 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-06-10OT200: bring LEDs into a defined stateChristian Gmeiner
Keep in mind that we can _NOT_ read back the current state of the LEDS as some crazy FPGA designer wanted it that way. Change-Id: I5cd1ac598072318b3234d1ec35a79271655b46ac Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3271 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-09fam15 vendorcode: Change license to BSD from AMD software licenseSiyuan Wang
fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the AMD software license agreement. Change this license to 3-clause BSD. Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-07usbdebug: Fix use without EARLY_CONSOLEKyösti Mälkki
If EARLY_CONSOLE is not selected, the PCI function for EHCI host controller must be configured in ramstage instead. Change-Id: I20f7569f79484c744bc413450bfa139052f3580f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-07Lenovo X60: Add int15 handlerDenis 'GNUtoo' Carikli
Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL, The VGA option rom doesn't init the right display: it initializes the external display, where we have a black scren(with backlight on). This commit is based on the code of mainboard.c in src/mainboard/roda/rk886ex. Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3265 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-06-07i945: Add Display defines for int15h handler.Denis 'GNUtoo' Carikli
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3306 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-06qemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpiGerd Hoffmann
First copy over from SeaBIOS git repo, then adapt for coreboot: Disable cpu/pci hotplug bits. Disable dynamic pci window. Both depend on stuff in the SSDT tables created by SeaBIOS. Bits are left in, but deactivated via #if 0, so it's easier to see the differences when diffing the coreboot tables with the SeaBIOS tables. Adapt dsdt DefinitionBlock. Enable acpi table generation in acpi_tables.c. With this patch linux boots successfully with ACPI enabled. It's not bug-free though. Missing cpu detection leads to funky messages like this one: weird, boot CPU (#0) not listed by the BIOS. and SMP most likely wouldn't work either. Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3342 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-06-06ec/acpi: Add ACPI methods for generic EC accessNico Huber
Port most of the functions found in ec/acpi/ec.c to ACPI Source Language (ASL). These functions are used to control embedded controllers with the standard ACPI interface (mostly through i/o ports 0x62 / 0x66). The following methods are implemented and tested against the power managements channels of a ITE IT8516E embedded controller: * WAIT_EC_SC Wait for a bit in the EC_SC register * SEND_EC_COMMAND Send one command byte to the EC_SC register * SEND_EC_DATA Send one data byte to the EC_DATA register * RECV_EC_DATA Read one byte of data from the EC_DATA register * EC_READ Read one byte from ec memory (through cmd 0x80) * EC_WRITE Write one byte to ec memory (through cmd 0x81) To use the provided methods, one should include `ec/acpi/ec.asl` in the EC device code. Prior doing so, two macros should be defined to identify the used i/o ports: * EC_SC_IO I/o address of the EC_SC register * EC_DATA_IO I/o address of the EC_DATA register Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3285 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-06-06AMD Trinity: Remove unnecessary lookup table copyBruce Griffith
The DDI connector table and the PCIe Port List lookup table are copied onto HEAP. This copy is not needed since these are lookup tables used to define the platform configuration. Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06AGESA: Add "const" modifier to function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06qemu: wind up new cpu chipGerd Hoffmann
Add boot cpu to the device tree. Figure the number of CPUs installed (using the qemu firmware config interface) and add cpu devices for them, so they show up in all generated BIOS tables correctly. This gets SMP going. Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06qemu: add x86 cpuGerd Hoffmann
This patch adds a qemu x86 cpu chip. It has no initialization function as this isn't needed on virtual hardware. A virtual machine can have pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu -cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu which is (almost) identical to the one on the host machine. So I've added X86_VENDOR_ANY as wildcard match for the cpu_table. Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3344 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06ec/kontron/it8516e: Add it8516e EC driverNico Huber
This driver communicates with the IT8516e on the Kontron KTQM77. Since we don't know if the firmware and protocol are standard for the chip or customized to the board, call it kontron/it8516e. Change-Id: I7382172c6d865d60106c929124444821a07a5184 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06intel/bd82x6x: Add option to include ethernet firmwareNico Huber
Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06intel/bd82x6x: fix building usb debug on SNB/IVBPatrick Georgi
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3389 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06(Trivial) early_smbus: fix printsmbus macroAlexandru Gagniuc
When I've first written this macro in 2011, the correct define for verbose SMBus message was CONFIG_DEBUG_SMBUS_SETUP. This has since been changed to CONFIG_DEBUG_SMBUS. I didn't catch that, and this made the printsmbus macro always evaluate to an empty statement. Use the proper CONFIG_DEBUG_SMBUS define. This makes printsmbus functional again. Change-Id: Iaf03354b179cc4a061e0b65f5b746af10f5d2b88 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3379 Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-06-05qemu: add power management function to device treeGerd Hoffmann
Needed to make 'register "gpo" = ...' work. While being at it add comments saying which device is which. Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3346 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05console: log qemu debugcon detection resultGerd Hoffmann
Change-Id: Ie0507475f33d029d6e8ce59f138e0e7da5156d4f Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3339 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05console: add qemu debugcon detectionGerd Hoffmann
The qemu debugcon port returns 0xe9 on reads in case the device is present. Use that for detection and write console output to the port only in case the device is actually present. Change-Id: I41aabcf11845d24004e4f795dfd799822fd14646 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05console: add qemu prefix to debugconGerd Hoffmann
Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05qemu: Initial support for the qemu firmware config interface.Gerd Hoffmann
qemu has a special device to pass configuration information from qemu to the firmware. This patch adds initial support the interface, namely some infrastructure, detection code and a function to query the number of CPUs. Change-Id: I43ff5f4fbf12334a91422aa38f514a82a1d5219e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3343 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-05Revert "Asus F2A85-M: Activate IOMMU support"Paul Menzel
This reverts commit eed28f97b375a9469a2872996c19eb102647052e. For whatever reason, the dependencies were lost in Gerrit and the commit [1] was submitted without its dependencies. As a result buidling the ASUS F2A85-M fails now [2] and therefore commits based on this commit fail to pass the buid tests by Jenkins. […] Created CBFS image (capacity = 8387656 bytes) LINK cbfs/fallback/romstage_null.debug CC cbfs/fallback/coreboot_ram.debug coreboot-builds/asus_f2a85-m/generated/coreboot_ram.o:(.data+0x16b9c): undefined reference to `GnbIommuScratchMemoryRangeInterface' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/coreboot_ram.debug] Error 1 make: *** Waiting for unfinished jobs.... coreboot-builds/asus_f2a85-m/mainboard/asus/f2a85-m/buildOpts.romstage.o:(.data+0x3d8): undefined reference to `GnbIommuScratchMemoryRangeInterface' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 […] Therefore revert the commit to get the tree working again and submit this patch with its dependencies again. [1] http://review.coreboot.org/#/c/3317/ [2] http://qa.coreboot.org/job/coreboot-gerrit/6618/testReport/junit/(root)/board/i386_asus_f2a85_m/ Change-Id: I911755884da09eb0a0651b8db07ee2a32e6eaaaa Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05qemu: fix IRQ routing setupGerd Hoffmann
Do the setup for all PCI slots, not only the third. Also remove the bogus message, as slot 3 may carry any device, not only NICs. This makes IRQ setup simliar to SeaBIOS. SeaBIOS assignments (with patch for logging added, and a bunch of pci devices for testing purposes): PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10 PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11 PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11 PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10 PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10 PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10 PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10 PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11 PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11 Coreboot assignments without this patch: Assigning IRQ 11 to 0:3.0 Coreboot assignments with this patch: Assigning IRQ 10 to 0:1.3 Assigning IRQ 11 to 0:3.0 Assigning IRQ 11 to 0:4.0 Assigning IRQ 10 to 0:5.0 Assigning IRQ 10 to 0:6.0 Assigning IRQ 10 to 0:1d.0 Assigning IRQ 10 to 0:1d.1 Assigning IRQ 11 to 0:1d.2 Assigning IRQ 11 to 0:1d.7 Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3334 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGSDenis 'GNUtoo' Carikli
X86EMU_DEBUG_TIMING is needed for producing i915tool compatible output. So add its dependencies to the i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS, which depends on HAVE_MONOTONIC_TIMER which LAPIC_MONOTONIC_TIMER provides/selects. Note that UDELAY_LAPIC is already selected by the Intel CPU. Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3356 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04Asus F2A85-M: Activate IOMMU supportRudolf Marek
Activate the IOMMU support for the Asus F2A85-M. Add the device to `devicetree.cb`. $ pci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] [ 0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS […] [ 0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000 [ 0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600 [ 0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000 […] [ 0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT] [ 0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT] [ 0.598073] pci0000:00: >Requesting ACPI _OSC control (0x1d) [ 0.603808] pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM [ 0.620508] Freeing initrd memory: 14876k freed […] [ 0.882674] pci 0000:00:01.0: >Boot video device [ 0.882876] PCI: CLS 64 bytes, default 64 [ 0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features: PreF PPR GT IA [ 0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X [ 0.917457] AMD-Vi: Lazy IO/TLB flushing enabled [ 0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff] [ 0.938535] LVT offset 0 assigned for vector 0x400 [ 0.943338] perf: AMD IBS detected (0x000000ff) [ 0.948037] audit: initializing netlink socket (disabled) [ 0.953432] type=2000 audit(1369659616.800:1): initialized [ 0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages […] [ 7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used) [ 7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF […] [ 7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X [ 7.885525] radeon 0000:00:01.0: >radeon: using MSI. […] [ 8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010] [ 8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010] [ 8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010] [ 8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010] [ 8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010] [ 8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010] [ 8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010] [ 8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010] [ 8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010] [ 8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010] [ 8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010] [ 8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010] [ 8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010] [ 8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010] [ 8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010] [ 8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010] [ 8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010] [ 8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010] [ 8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010] [ 8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010] [ 8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010] [ 8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010] [ 8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010] [ 8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010] [ 8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010] [ 8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010] [ 8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010] [ 8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010] [ 8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010] [ 8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010] [ 8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010] […] [ 8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010] [ 8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010] [ 8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010] [ 8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010] [ 8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010] [ 8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010] [ 8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010] [ 8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010] [ 8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010] [ 8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010] [ 8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010] [ 8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010] [ 8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010] [ 8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010] [ 8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010] [ 8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010] [ 8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010] [ 8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010] [ 8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010] [ 8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010] [ 8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010] [ 8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010] [ 8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010] [ 8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010] [ 8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010] [ 8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010] [ 8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010] [ 8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010] [ 8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010] [ 8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010] [ 8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010] [ 8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010] [ 8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010] [ 8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 8.963165] radeon 0000:00:01.0: >WB enabled […] It is not known, what the implications of the `IO_PAGE_FAULT` are. Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3317 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04Yabel : Add tracing option needed by i915tool.Denis 'GNUtoo' Carikli
This patch was made by listenning to what Ron Minnich told me to do on #coreboot IRC channel on Freenode with my adaptations on top. i915tool is at https://code.google.com/p/i915tool/ , the one in coreboot is outdated. Change-Id: I13cd684f4c290114836fbd7babd461153e8d6124 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architectureRonald G. Minnich
The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer since it was defined in sandybridge. It is really more of an x86 thing however, and we now have three systems that can use it. I considered making this more general, since it technically can apply to PTE-based systems like ARM, and maybe we should. But the 'WRCOMB' moniker is usually closely tied to the x86. Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3349 Tested-by: build bot (Jenkins)
2013-06-04Lenovo X60: Add CMOS defaults.Denis 'GNUtoo' Carikli
After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback baud_rate = 115200 debug_level = Spew hyper_threading = Enable nmi = Enable boot_devices = '' boot_default = 0x40 cmos_defaults_loaded = Yes lpt = Enable volume = 0xff tft_brightness = 0xbf first_battery = Primary bluetooth = Enable The code for handling the invalid CMOS space in mainboard.c is now useless and so it was removed. Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3335 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04Asus M4A785T-M: Add CMOS defaults.Denis 'GNUtoo' Carikli
After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04PC Engines ALIX.1C: Add CMOS defaults.Denis 'GNUtoo' Carikli
After Booting the BIOS, flashing coreboot and booting coreboot with that patch we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3323 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04pci_ids.h: Add PCI IDs for VIA VX900 chipsetAlexandru Gagniuc
Change-Id: I4a75326fef0a10a6290cdd4b1b93d9af8e3ab23d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3268 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-04coreboot: Add generic early SMBus APIAlexandru Gagniuc
Early SMBUS code with similar functionality is duplicated for all southbridges. Add a generic SMBus API (function declarations) designed to unify the early SMBus structure. This patch only adds the API. It does not implement any hardware-specific bits. Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/143 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04DDR3: Add utilities for creating MRS commandsAlexandru Gagniuc
MRS commands are used to tell the DRAM chip what timing and what termination and drive strength to use, along with other parameters. The MRS commands are defined by the DDR3 specification [1]. This makes MRS commands hardware-independent. MRS command creation is duplicated in various shapes and forms in any chipset that does DDR3. This is an effort to create a generic MRS API that can be used with any chipset. This is used in the VX900 branch. [1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3354 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04VIA Nano: Add microcode updates filesAlexandru Gagniuc
While we had support for updating microcode on the VIA Nano CPUs for a while now, we never included the actual microcode. Unlike, Intel and AMD CPUs, VIA microcode is not available for download, and was extracted from the vendor BIOS. It was not included in coreboot since we never had explicit permission to do so. I have just received confirmation from VIA that we can distribute the microcode. Change-Id: I4c15b090cd2713cfe5dc6b50db777ff89dbc0f19 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3357 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-06-04AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"Christian Gmeiner
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: convert spd_read_byte() to non-static versionChristian Gmeiner
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"Christian Gmeiner
Move the include before static inline int spd_read_byte(). Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: rename get_systop() to get_top_of_ram()Christian Gmeiner
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3367 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: include northbridge.h in raminit.cChristian Gmeiner
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3365 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-staticChristian Gmeiner
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3364 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: add some missing includesChristian Gmeiner
This commit fixes problems if we build raminit.c for romstage. Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3363 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make sdram_* function prototypes non-staticChristian Gmeiner
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c" line we need to do some prepartion steps. This commit is one of them. Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3362 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Fam 15tn: Use all memory on systems with more than 4 GBSiyuan Wang
Take a Parmer board with 4G memory as an example. Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'. Parmer uses 512M as video memory when it has 4G. 3327540+512*1024 = 3851828(kB), so some memory is lost. When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is 0x00000001. But in e820 table or coreboot table, the last item is 6: 0000000100000000 - 0000000118000000 = 1 RAM This is not correct, it should be 6: 0000000100000000 - 000000011f000000 = 1 RAM This patch changes the memory layout when TOM2 is set. Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3366 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03dram: Add utilities for decoding DDR3 SPDsAlexandru Gagniuc
Add convenience utilities for decoding DDR3 SPDs and printing the information to the console. These have proven invaluable when writing the VX900 memory initialization. These are used in the VX900 branch Information printed has the following format: > SPD Data for DIMM 51 > Revision: 10 > Type : b > Key : 2 > Banks : 8 > Capacity: 1 Gb > Supported voltages: 1.5V > SDRAM width : 8 > Bus extension : 0 bits > Bus width : 64 > Optional features : DLL-Off_mode RZQ/7 RZQ/6 > Thermal features : ASR ext_temp_range > Thermal sensor : no > Standard SDRAM : no > Row addr bits : 13 > Column addr bits : 10 > Number of ranks : 1 > DIMM Capacity : 1024 MB > CAS latencies : 6 7 8 9 > tCKmin : 1.500 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 36.000 ns > tRCmin : 49.125 ns > tRFCmin : 110.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns Change-Id: I30725a75caf74ac637db0a143344562bd9910466 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3267 Tested-by: build bot (Jenkins)
2013-06-03spd.h: Add all known SPD_MEMORY_TYPE definitions.Alexandru Gagniuc
This file was missing some definitions, so add them. Also turn the defines into an enum. The reason for doing this is that functions can now explicitly take an spd_memory_type as a parameter: > int do_something_with_dram(enum spd_memory_type type, ...) Which is a lot more explicit and readable than: > int do_something_with_dram(u8 type, ...) These are used in the VX900 branch. Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3266 Tested-by: build bot (Jenkins)
2013-06-03include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other definesPaul Menzel
Probably due to different (character) widths for a tab, sometimes only one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For the “correct” alignment, that means where a tab is eight characters, two tabs are necessary. Change it accordingly. Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3263 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03Asus F2A85-M: Fix the _CRS PCI0 bus infoRudolf Marek
On Asus F2A85-M, the Linux kernel complains that the _CRS method does not specify the number of PCI busses. [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS Just put there 256. This should be part of re-factoring of the whole ACPI stuff. The same change was already done for the AMD Brazos (SB800) boards, based on commit »Persimmon DSDT: Add secondary bus range to PCI0« (4733c647) [1]. [1] http://review.coreboot.org/2592 Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3320 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-03AMD Geode CS5536: downgrade BIOS_ERRChristian Gmeiner
There is no need to use everywhere BIOS_ERR. Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3307 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03console: add support for QEMU's debugconGerd Hoffmann
Add support for sending debug output to an I/O port. It can be used together with QEMU's isa-debugcon driver to log the coreboot output to a file. The port is configurable and defaults to 0x402 which has established as the de facto standard. For example, SeaBIOS+OVMF [1] use that one too. [1] http://www.linux-kvm.org/page/OVMF Open Virtual Machine Firmware Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03haswell: allow for disabled hyperthreadingAaron Durbin
There were assumptions being made in the haswell MP and SMM code which assumed the APIC id space was 1:1 w.r.t. cpu number. When hyperthreading is disabled the APIC ids of the logical processors are all even. That means the APIC id space is sparse. Handle this situation. Change-Id: Ibe79ab156c0a171208a77db8a252aa5b73205d6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3353 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03haswell: fix overflow handling TOUUDAaron Durbin
It's possible that the TOUUD can be set to less than 4GiB. When that is the case the size_k variable is an extremely large value. Instead ensure TOUUD is greater than 4GiB before adding said resources. Change-Id: I456633d6210824e60665281538300fd15656b86d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03Intel Lynx Point: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3182 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03Intel BD82x6x: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3183 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3197 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03am335x: Clean up/fix some settings in the am335x Kconfig.Gabe Black
Some settings in the am335x Kconfig weren't actually used for anything, some where place holders, and some where left over from another CPU. The memory addresses are in the internal RAM in the SOC as described in the reference manual. The stack is put where the internal ROM had its stack, and the bootblock is put at the bottom of that region as the manual suggests. The ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the bootblock currently takes up. Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3327 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-06-02Provide sane Kconfig default for cmos.default.Denis 'GNUtoo' Carikli
Without that fix we have with CONFIG_USE_OPTION_TABLE: OPTION cmos_layout.bin build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'. Stop. rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c That log was captured with make V=1 but the error also appear with make. Tested on the PC Engines ALIX.1C with the following commit (Change-Id: Ia87b090) [1]: PC Engines ALIX.1C: Add CMOS defaults. [1] http://review.coreboot.org/#/c/3323/ Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3223 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-05-31Lenovo ThinkPad X60: cleanup Native VGA init.Denis 'GNUtoo' Carikli
Change-Id: Iaefa23a6257fd0295357465eb03ccadbef0f70da Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31AMD Trinity boards: Add reserved memory area for SPI base address in ACPISteven Sherk
- SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. I have tested on Parmer. Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3347 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30AMD Llano, Brazos boards: Use `sizeof(var)` to get its sizePaul Menzel
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe config« [1] contains the same change and is ported over. In the commit message Rudolf makes the following comment. »Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR?« Testing on the ASRock E350M1, no regressions were noticed. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3248 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-30AMD Trinity boards: Use `sizeof(var)` to get its sizeRudolf Marek
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? These changes are based on Rudolf’s original patch »ASUS F2A85-M: Correct and clean up PCIe config« [1], where it was just done for the ASUS board. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3247 Tested-by: build bot (Jenkins) Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-29qemu: remove vga hookGerd Hoffmann
Extra care for the qemu vga should not be needed any more. Since release 0.12 qemu loads the vgabios into the PCI ROM bar, so everything works exactly like it does on real hardware. Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29cpu/amd/geode_lx/Kconfig: Select TSC_MONOTONIC_TIMERChristian Gmeiner
The following is an excerpt from serial log of the Bachmann OT200. $ grep usec coreboot_log clocks_per_usec: 500 Root Device init 48034 usecs CPU_CLUSTER: 0 init 133251 usecs PCI: 00:01.0 init 33376 usecs PCI: 00:01.1 init 9930 usecs PCI: 00:01.2 init 9929 usecs PCI: 00:04.0 init 9929 usecs PCI: 00:0f.0 init 185788 usecs PCI: 00:0f.2 init 21473 usecs PCI: 00:0f.3 init 9930 usecs PCI: 00:0f.4 init 9930 usecs PCI: 00:0f.5 init 9930 usecs PCI: 00:0f.6 init 9930 usecs PCI: 00:0f.7 init 9929 usecs Change-Id: I4d0805c4cf8fcb25ec107615787fc6da0c945a30 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3308 Tested-by: build bot (Jenkins)
2013-05-26beaglebone: initial Kconfig and MakefilesGabe Black
Initial structure of Beaglebone port Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM consolePaul Menzel
Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console support by copying GNUtoo’s commit for the Lenovo ThinkPad X60. commit 4560ca5003fe38a066616e8de1a8a414284750fd Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support. Reviewed-on: http://review.coreboot.org/3142 Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3187 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-26snow: Add a name to the serial console UART choice block.Gabe Black
This allows other boards to have the same choice block without confusing kconfig. Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3293 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-25Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`Ronald G. Minnich
multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3242 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-24cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMERPaul Menzel
Thanks to Aaron Durbin coreboot provides monotonic timers. Select the LAPIC monotonic timer for the AMD AGESA CPUs. The following is an excerpt from serial log of the ASRock E350M1. $ grep usec seriallog-20130502_100902.log 01.016: Root Device init 1578 usecs 01.029: CPU_CLUSTER: 0 init 112415 usecs 01.029: PCI: 00:00.0 init 3240 usecs 01.088: PCI: 00:01.0 init 104572 usecs 01.088: PCI: 00:01.1 init 1663 usecs 01.088: PCI: 00:11.0 init 1662 usecs 01.088: PCI: 00:14.0 init 1662 usecs 01.088: PCI: 00:14.3 init 8665 usecs 01.088: PCI: 00:14.4 init 1665 usecs 01.088: PCI: 00:18.0 init 1662 usecs 01.088: PCI: 00:18.1 init 1663 usecs 01.088: PCI: 00:18.2 init 1663 usecs 01.088: PCI: 00:18.3 init 1663 usecs 01.088: PCI: 00:18.4 init 1663 usecs 01.088: PCI: 00:18.5 init 1665 usecs 01.088: PCI: 00:18.6 init 1664 usecs 01.088: PCI: 00:18.7 init 1663 usecs 01.088: PNP: 002e.2 init 1576 usecs 01.088: PNP: 002e.5 init 1577 usecs 01.088: PNP: 002e.a init 1590 usecs 01.088: PNP: 002e.b init 30144 usecs 01.088: PCI: 03:00.0 init 1663 usecs So the graphics device needs around 100 ms for being initialized. The full serial log is in the Gerrit comments. Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3172 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-24cpu/intel/haswell/Kconfig: Intend help text with two spacesPaul Menzel
Commit »haswell: 24MHz monotonic time implementation« (c46cc6f1) [1] added the Kconfig variable `MONOTONIC_TIMER_MSR` with a help text, but only used one space instead of the suggested two spaces for indentation. So add one space. »Lines under a "config" definition are indented with one tab, while help text is indented an additional two spaces.« [2] [1] http://review.coreboot.org/3153 [2] https://www.kernel.org/doc/Documentation/CodingStyle (Chapter 10: Kconfig configuration files) Change-Id: I39cf356bfd54c66a2f1b837c6667dcc915e41f29 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3262 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>