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BUG=None
BRANCH=None
TEST=Compiles successfully and pmc rst status POR is seen.
Change-Id: Ic09cb46d9be7670e467543e42b251efb1a4313d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5dbfae6bbc0f4f30e216e37b515f4120f7833a38
Original-Change-Id: Id0c2b208222deaf099b8938ba583551979588d52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220721
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9106
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Also, get rid of unused clk_rst variables.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I6487162454159a81b31fe0d6d39c2bdbed3f859a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 030081fe85fc9609fdf2003cf51b7350e08f0429
Original-Change-Id: I880ae5c396c33006f6b184cca7f171e4373f4016
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220720
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9105
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Both buttons are active low.
BUG=chrome-os-partner:32517
BRANCH=None
TEST=Compiles successfully and volup and voldown button presses are detected in
pseudo keyboard driver in depthcharge
Change-Id: If217a75f95042af8a831e7109d9b1acb10c55823
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c393e166a1ed0bc7920078aac6accf442abb5955
Original-Change-Id: I08f94972db53aa17a63f6e16cbaebe7af358cdc2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220687
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9104
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Measure the MTS load time, MTS initialization time, and
the ramstage verification/load time.
BUG=None
BRANCH=None
TEST=Booted and noted timings.
Change-Id: I1eb1e3a73316a3fa76ef8e73314bedde34c6c582
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b5b34a3abd388359b7d1cba5a858e4e5a402b476
Original-Change-Id: I71119689182e86406d5052f007908152d41e9092
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219715
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9103
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There's no need to add DMA ranges for these boards as
that memory is allocated within dpethcharge now. Additionally,
the DRAM_DMA_* Kconfig options were removed resulting in 0
values.
BUG=None
TEST=Built rush and ryu.
BRANCH=None
Change-Id: I597437960e4fddbf6d26f0b15ddeefc4557adc8b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f26b503d759b2bac902e58e928d7c625c1a6c575
Original-Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219710
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9101
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:31821
BRANCH=None
TEST=Built and booted to kernel prompt on ryu. Rush compiled successfully.
Change-Id: I63ba55c53094c185d72dcb5c5d0d766461989806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a9aa565244bae5659e458ea90064eb5b803d574
Original-Change-Id: I5b00fbcb8e414c67563f1ad548f84c281898f939
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219392
Original-Reviewed-by: Tom Warren <twarren3959@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9100
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Clean up functions to write to clk_enb and rst_dev registers and add
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183
Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219191
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9099
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Since PSCI dynamically determines which EL to transition
to based on SCR_EL3 there's no need to provide that
information.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel with MP.
Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c
Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218924
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The PSCI functionality initially includes CPU_ON and CPU_OFF
functions. Upon entering secmon if the parameters are non-NULL
then a PSCI CPU_ON action is done for the current CPU.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel
using PSCI. Turned CPUs on and off.
Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748
Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9097
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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If an exception is taken that the secmon won't return
to, there needs to be way to reset that cpu's state
w.r.t. stack usage. Therefore, provide secmon_trampoline
which will reinitialize the exception stack and SP_EL0
and start executing with SP_EL0 like the initial state
of the secmon entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also tested when PSCI
is employed in the kernel.
Change-Id: Ie9f5bbe715dcbcf8b67ea40f9a3a5088ac7aa2ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1f546ee3e9eca93baaa1ae0437351205bf548a5
Original-Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9096
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639
Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9095
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Two things:
1. Not returning once setting the return state.
2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x))
With these 2 changes arguments and results are being processed
correctly.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and brought up SMP using PSCI.
Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8
Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9094
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.
I2C6 init/enable will be moved to ramstage in the next CL.
BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I42106778a26c5a1d1483cc308b8314599c391539
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b
Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218900
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9093
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to process PSCI commands SMC instructions need to be
serviced. Provide a simple way for users of SMC to register their
handlers by function.
The SMC layer hooks into the exception processing, however it only
processes AARCH64 SMC calls. All others are ignored.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Added nop smc call to depthcharge. SMC handled and continue booting
to kernel.
Change-Id: I378f13c29220ff9f37040f094bf9cfb69259af0c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76d2febc50397348b68d38532b8f37e2b3cf6a30
Original-Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218846
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9092
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The exception vectors were not reinitialized in secmon yet.
Add that as well as the split BSP vs non-BSP path. In doing
so bring in the cpu.c semantics for determining bsp at runtime.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also noted only one CPU
printing messages.
Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32
Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218845
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9091
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's helpful to differentiate the startup paths for
the BSP and the non-BSP. Therefore have c_entry
be an 2 element array of function pointers. The
non-BSP paths have an entry point one instruction after
stage/module entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe
Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218844
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9090
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The cpu.c contains some helpful construts as well as ramstage
devicetree handling. Split the 2 pieces so that cpu.c can be
reused in secmon.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted.
Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f
Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218842
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9089
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to build upon the arm64 exception handlers need
to be registered. This provides very basic support to
register a handler for a specific exception vector.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel.
Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a
Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218650
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9088
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With the generic spin table support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=None
Change-Id: I7c9ebd16cd7d5e938e686df2225c612581382983
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb0d79f89e27fcd51cc751a94008b3801f5c6d0b
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Change-Id: Ic9949144ed1e9a952290d50b6726bf5891547896
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218657
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9087
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With the generic spin table support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Booted into kernel.
Change-Id: I8644f8a81b24bf4e00f8fac1d1018f9db77c952f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1a4fe27070a80c8448051ec0565120901378673
Original-Change-Id: Id0832a4553101a366f011099e0744f6630d91924
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218656
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9086
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Support the generic spin table code instead of having
the one-off implementation.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor.
Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf
Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218655
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9085
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There was a hacky and one-off spin table support in tegra132.
Make this support generic for all arm64 chips.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Ran with and without secure monitor booting smp into the kernel.
Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748
Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218654
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9084
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's helpful to know if the current running CPU
is the BSP. Therefore, provide that semantic.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I18cb8ab5149c3337e22b1f6046b1af266be7e47c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b390dc70b658c207cd3b64408713ec4cddab3172
Original-Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218653
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9083
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to provide richer semantics for running code
on all CPUs add an all-but-self construct.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: If8dd28ff7f34d93592ab2025a65a2fd665e4e608
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a4622f63a065f620f0c92ef92eeb2aa5c2b441d
Original-Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218652
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9082
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and secmon loads and jumps to payload successfully.
Change-Id: I929cf2c938fb5d8c20e13fbd1fdbd349378914ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e5d6adc63c4d820417985e34f1f04810b38422b
Original-Change-Id: I442546178ad945e7639a99dd2943d13a69b06d09
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214372
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9081
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Secure monitor runs at EL3 and is responsible for jumping to the payload at
specified EL and also to manage features like PSCI.
Adding basic implementation of secure monitor as a rmodule. Currently, it just
jumps to the the payload at current EL. Support for switching el and PSCI will
be added as separate patches.
CQ-DEPEND=CL:218300
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles succesfully and secure monitor loads and runs payload on ryu
Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34
Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214371
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9080
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
stage_entry is the best place to enter for secmon, since it sets up all the
stacks right. The only need we need to take care is losing out on the parameter
passed to secmon. This patch adds an entry point for secmon rmodule and moves
the argument from x0 to x25, which is restored just before the jump to c_entry
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I9638e9716b3bd5bff272e88fe9d965528d71e394
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ffedb03208bafab6d5886db0259ec205dd20588f
Original-Change-Id: I74a7a609fbc08692d68708abe132cd219c89b456
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217570
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9079
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Provide SCR_EL3 initialization on all CPUs. This settings were
chosen in such a way that nothing would need to be done if EL3
is abandoned after transitioning to EL2 or EL1. If persistent
EL3 program is used those SCR policies can be updated within
that program.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Built and booted through kernel. Printed out SCR setting for
each CPU.
Change-Id: Ib44acd8ae40dbca590740340632f5b72998e9dd8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f77b903afbafad7d439ec50fc48f1eaa37827d90
Original-Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218300
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9078
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
As the arm64 boot flow handles initializing the GIC by
way of the driver provide the SoC support for that
driver and use it.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted kernel on ryu.
Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e
Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217514
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9077
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
|
|
For every CPU that comes online initialize the GIC for
that CPU. This allows the per-cpu register state to
be initialized for every CPU that comes online.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted to kernel on ryu.
Change-Id: I467ca38d51ac67ffc19b1b4fc6fafa9394a876c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2faf33fad80fd7ecb884d3ad40917f5a629a5b2
Original-Change-Id: I58d0ffcfe65cffc6a4dd2678c041219e1e698aaf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217513
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9076
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
|
|
The GIC is ARM's "Generic Interrupt Controller". This
change essentially implements the rudimentary support
for a GICv2 implementation that routes all interrupts
to Group1. This should also work for GICv1 with security
extensions.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted kernel using the code.
Change-Id: I9c9202c1309ca9e711e00d742085a6728552c54b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d1cd9b6b76035af107b7dc876f90777698162d34
Original-Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217512
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9075
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
|
|
CQ-DEPEND=CL:216826,CL:218300
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and we are able to start execution of libpayload in
EL2 and reach kernel login prompt
Change-Id: I233f9867470a4723f320dc0dcaa670a56dcf0f5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 169948a2afeeb7848daeb37600963bd503527f1a
Original-Change-Id: I336d73085f08ca03e533555a10b88f20d74b4347
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217826
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully
Change-Id: Ife5300db8721a158f8a3b027aca4c51e4ea513a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 02bcdc7069e271563b7fd1893b92fb4d33cf8529
Original-Change-Id: I59e0f8d26d50baf68561b38f370195dea98881e1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217572
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9073
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and dma areas are setup fine by libpayload mmu
Change-Id: I6d2d1dbcfc9bdeea94c89a9a3fce486203269642
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0425e87f21bcb92861240d6437769a5b28e9929b
Original-Change-Id: I1034a4dcf6c9ee56bee4ea5d18e91a8d51895429
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217571
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9072
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Transition library acts as a common interface for handling exceptions. The only
thing that needs to be implemented by exception.c is the exc_dispatch routine to
handle the exceptions as required.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and exceptions are tested using test_exc
Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425
Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217143
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9071
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Transition library provides the following functionalities:
1) Setup the environment for switching to any particular EL and jump to the
loaded program at that EL. In short "Execute program X at exception level Y
using the state Z"
2) Provides routines for exception entry and exception exit that can be used by
any program to implement exception handling. The only routine required by the
program would be exc_dispatch which handles the exception in its own required
way and returns by making a call to exc_exit. On exc_exit, the transition
library unwinds the whole stack by popping out the saved state of xregs
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and exceptions are tested for ramstage on ryu
Change-Id: I8116556109665e61a53e4b3987d649e3cfed64a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ab888e8cae0c5f1e79b0e16ca292869f16f1cca
Original-Change-Id: I90f664ac657258724dc0c79bd9f6ceef70064f90
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216375
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9070
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Coreboot compiles successfully
Change-Id: I1fba44974314effa1065e3637aaa5430584a4cc6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a4791232de764ebe40d9b3de5c63479dec7da003
Original-Change-Id: I95fdff5d1580faf4cb4f85d6acae7a834b8ff0bf
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218031
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9069
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
If mmu_init is called more than once then, free_idx should be reset to
1. Here, the assumption would be that mmu_init will not be called more than
once. However, this is not necessarily true. Thus, free_idx should be reset to 1
every time we are initializing ttb from scratch.
BUG=None
BRANCH=None
TEST=Compiles sucessfully and boots to kernel
Change-Id: I5ac0af43346a492583380b0f15101390fc98d182
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 398a68c3b08d82cfa521d235af2c1922629bdf56
Original-Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216906
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9068
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Rush builds were throwing a _sync_sp_el0 exception due
to commit 65af2f3d (tegra132: support arm64 SMP bringup).
Fixed by copying over the rush_ryu devicetree.db, which
adds all the CPUs to the device tree. Basically the same
as commit 8f61ca2da but for rush.
BUG=None
BRANCH=None
TEST=Booted rush OK, brought up rush kernel from USB.
Change-Id: Ia91260ed36364ae1cfdd28932f09df9486c7e638
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 649391a402527cef1465d5a948323ad95c77917d
Original-Change-Id: Ic9e34494ec8e6ad82e6020df6ad6fecd8763ac7e
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217792
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
If there are no devices underneath a device in a devicetree the
bus pointer in a struct device is NULL. Check for this condition
before proceeding in walking through the children devices.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Ran through coreboot w/o any devices under the cpu_cluster device.
No more exceptions.
Change-Id: I9aedbc0dffc638b878bd0ffacfa318b6eb30d504
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21e181077eba3c5ee03afca1738a24c21a8fc19
Original-Change-Id: I891aeb36319dce67ce9e431156c85c74177c7ab7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217511
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Instead of relying on config variables to determine the current el, use
{read/write}_current macros for accessing registers.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and boots to kernel login prompt
Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564
Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217148
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9065
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932
Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9064
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Allow read/write to registers at a given el. Also, make read/write registers at
current el call this newly added function.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d
Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9063
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b
Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216373
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9062
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Nvidia tracks their MTS versions using decimals. Update
the format so there isn't an extra step in communicating
versions while debugging things.
BUG=chrome-os-partner:31864
BRANCH=None
TEST=Booted and confirmed decimal print out.
Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35
Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217260
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9061
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Now that there is cpu devicetree support retire the
bring_up_secondary_cpu option as the devicetree is the
way going forward to do other CPU bring up.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted with 2nd core.
Change-Id: I3e8812cd2183f2126c11c36ff4844c15b3cbfc1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7eab33b763d33d6be210ddb69e3c67411bad0fd0
Original-Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216929
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Now that arm64 and tegra132 has cpu devicetree support stop
using the bring_up_secondary_cpu option.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and brought up 2nd core.
Change-Id: I3ffca6c1fa0932d8aafea30a160608b5593ae154
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c45b22ce9fd0345c3e599fd814993db66e2b96cc
Original-Change-Id: I210bea73f8249de15f99d0c062600e789184eefd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216928
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9059
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Two weak functions were added so that architecture specific operations
on each segment of payload or stage can be performed.
Each architecture must define its own operations, otherwise the
behavior will default to do-nothing functions.
This patch has been updated by to fit more in line with
how program loading is currently being done. The API is the
same as the original, but all call sites to stages/payloads
have been updated. This is known to break any archs that use
rmodule loading that needs cache maintenance. That will be fixed
in a forthcoming patch. Also, the vboot paths are left as is
for easier upstreaming of the rest of the vboot patches.
Original-Change-Id: Ie29e7f9027dd430c8b4dde9848fa3413c5dbfbfa
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/239881
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit c82c21ce87a4c02bd9219548a4226a58e77beef0)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifcee5cd9ac5dbca991556296eb5e170b47b77af7
Reviewed-on: http://review.coreboot.org/8837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I973abf2224762bf7a53d71177544ade15db50cba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8856
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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This change also depends on mrc due to changes in pei_data.h
Report smbios type 17 for each memory
CQ-DEPEND=CL:210005
BUG=None
BRANCH=None
TEST=Compiles successfully
See smbios type17 in OS by dmidecode
Original-Change-Id: If83c99364726cd17c719a59ed8ac993736c63b9a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210399
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 6da6b4ffb3a45fdd766b88220c2adb168b3c5e10)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I39ea9ef9b342239fe26846ab0a928f6a680c21e8
Reviewed-on: http://review.coreboot.org/8956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add smbios type 17 which can optionally be implemented
at the platform or mainboard level
In order to create SMBIOS type17, you will need to fill
memory_info data
BUG=None
BRANCH=None
TEST=Compile successfully on rambi and samus
Boot to chromeOS on samus and rambi
Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210005
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63
Reviewed-on: http://review.coreboot.org/8955
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iaf8167839f8506bd2ab08c2ba9f8317ba2437f28
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Paul Menzel
Reviewed-on: http://review.coreboot.org/9054
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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The static gpio_t initializers are stylish, but they are still a little
too annoying to write and read in day-to-day use. Let's wrap that in a
macro to make it a little easier to handle.
BUG=None
TEST=None
Change-Id: If41b2b3fd3c3f94797d314ba5f3ffcb2a250a005
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 102a5c0a800f43d688d11d1d7bbc51e360341517
Original-Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220250
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This updates timer.h to #include the header necessary for u32,
and to change the one instance of uint32_t to u32 to be uniform.
BUG=none
BRANCH=none
TEST=compiled
Change-Id: I4d67045206fd94985774b8d46a307bbb2e337f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ff2629fdf3c69c203fa61ec894bb4895990cb5e
Original-Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220612
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds a mainboard-specific bootblock function that will be used
to set up some board-specific parameters which are currently set up
in the SoC bootblock function.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Change-Id: I86c90f7ade824fb9d6b71ca3349d1ce9eb4772fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03e0bb2eaca7a54c3df95b21d856ef4114d3c833
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4
Original-Reviewed-on: https://chromium-review.googlesource.com/220399
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9050
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Serial Peripheral Flash Interface (SPFI) block allows
communication with various devices over the SPI bus.
It uses a configurable transaction interface and it clocks
the bus according to the configured command, address, gap (aka
dummy) and data lengths.
This controller requires the SPI_ATOMIC_SEQUENCING flag set
(write and read done in the same transaction) as it cannot
directly control CS and will assert/de-assert CS at the
beginning/end of a transaction itself.
Note that the size of any transfer cannot be greater than
64KB - 1, as this is configured in a 16-bit field.
The SOC has 2 SPFI interfaces each of them providing 5 slave select
lines. SPFI 0 supports single and dual modes, SPFI 1 supports
single, dual and quad modes.
For SPFI interface 0:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi0clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set
- CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration parameters are also required:
Signal name Pad name MFIO mode
spim0_d0_txd MFIO_MIPS_10 0
spim0_d1_rxd MFIO_MIPS_9 0
spim0_mclk MFIO_MIPS_8 0
spim0_cs0 MFIO_MIPS_2 1
spim0_cs1 MFIO_MIPS_1 1
spim0_cs2 MFIO_MIPS_55 1
MFIO_MIPS_28 1
spim0_cs3 MFIO_MIPS_56 1
MFIO_MIPS_29 1
spim0_cs4 MFIO_MIPS_57 1
MFIO_MIMPS_30 1
For SPFI interface 1:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi1clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set
- CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration parameters are also required:
Signal name Pad name MFIO mode
spim1_d0_txd MFIO_MIPS_5 0
spim1_d1_rxd MFIO_MIPS_4 0
spim1_mclk MFIO_MIPS_3 0
spim1_d2 MFIO_MIPS_6 0
spim1_d3 MFIO_MIPS_7 0
spim1_cs0 MFIO_MIPS_0 0
spim1_cs1 MFIO_MIPS_1 0
MFIO_MIPS_58 1
spim1_cs2 MFIO_MIPS_2 0
MFIO_MIPS_55 2
MFIO_MIPS_31 1
spim1_cs3 MFIO_MIPS_56 2
spim1_cs4 MFIO_MIPS_57 2
BUG=chrome-os-partner:31438, chrome-os-partner:32441
TEST=Tested as bare-metal driver on Pistachio FPGA
Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91
Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217320
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9049
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.
BUG=none
TEST=board urara still builds
Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78
Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220401
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: Ib7396189f4bee0fdd6a8ce5c9ab1277806cb5dcc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ca9efe59a7fcb99412410d509a7f9a91b6ef3ec
Original-Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214600
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9047
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e
Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216927
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Use the formal devicetree way for bringing up each of
the cpus. This includes providing a cpu_driver as well
as calling arch_initialize_cpus() with the proper
operations to start the cores.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP on ryu.
Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a
Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216926
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9043
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be
SMP aware but the ARMv4 part does not.
Until we need real SMP on ARMv4, work around that situation
with stub defines.
Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9046
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds SMP bring up support for arm64 cpus. It's
reliant on DEVICE_PATH_CPU devices in the devicetree.
Then for each enabled device it attempts to start then
initialize each CPU. Additionally, there is a cpu_action
construct which allows for running actions on an individual
cpu.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted both cores on ryu into linux.
Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e
Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216925
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a cpu-internal.h for internal prototypes to the
architecture specific code.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted.
Change-Id: I12a379f86056a9a2007a7c036d65b5e08e558d0e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5dcd488326f6496d80eb1fe1ff4414ebba1280e9
Original-Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216924
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9041
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide a simple spinlock implentation for arm64. A value
of 0 is unlocked and a value of 1 is locked.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup on ryu.
Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c
Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9040
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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The spinlock header file was not residing in the correct place.
It needs to live under 'arch/smp'.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with SMP. spinlock.h found.
Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0
Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9039
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The load-acquire/store-release operations (including exclusive
variants) form a basis for atomic operations. Also remove
the dmb, dsb, and isb functions from lib_helpers as barrier.h
already included these. Lastly, utilize barrier.h.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup using barriers.
Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118
Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216921
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9038
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0
Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216920
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9037
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I4bf5d98e409840cf07a7759e9273d770f3bbf8bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ec672e52eda69f2b5abb747807a496bb973088f
Original-Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216429
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9036
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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The code should be GPL. Update accordingly.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=None
Change-Id: I051ceb3f12e9938819b513413aae43cbf51d9b86
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cdff53ebf4c1a1d86d68054c2d25dce45b69ff48
Original-Change-Id: I26a40a239afd851d351dbda0d716ef992b88b6c8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216428
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9035
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f
Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216426
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9034
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of directly using the clk_src_id based on enum for clock source, every
device needs to have its own set of clk source ids defined. This prevents
accidentally selecting a wrong clk source if the ids are different from host1x's.
Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id
represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for
handling the common clock sources based on id to get the proper frequency in
software.
[pg: integrated a later commit to fix the build]
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5d40fb49b81e8838b2be071d32c466213215e0d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27d5d6a34d1c826c6095c18368efb78c228d4ca8
Original-Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216761
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 13c30c50a9e8a7f3c48673a2f6c144ba546129b6
Original-Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217342
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9033
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide access to the MIDR_EL1 register to obtain the
main id for determining CPU implementer and part/revision
information.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and printed the output of this function on ryu.
Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c
Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216423
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9032
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9
Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216421
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9031
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: Id046592415574badb97026224e1e525c174eece4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7
Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/215863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9030
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Expanded sdram.c to add support for LPDDR3 init. This code can
be used with matching BCT .inc files to have LPDDR3 SDRAM
initialized by coreboot instead of the T132 BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I53801d9399dbf67fd86d0a2521174f0668567620
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 60e130c47c1894925a12f251af5b83a1fa144d57
Original-Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214753
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149
Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9028
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of calling out the gpio index and port numbers use
real names. It's semantically clearer and there's only one
place to adjust the hardware values.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted.
Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c
Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215542
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9027
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
more plld errors observed from the kernel.
Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b
Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Depending on the requested frequency the plld cannot
necessarily obtain the exact clock. Therefore provide the
closest configured frequency as a return value. This is
equivalent to the t124 patch.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Built and noted plld actual value close to requested.
Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863
Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214843
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/9025
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With the latest changes to include stack storage within ramstage, we no longer
need to define Kconfig options for ramstage/exception stacks in arm64.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel on ryu
Change-Id: I7361d8f567453e775240151fd1180c49025141b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9aaa89115a67606fcb66eb354741043f7f2094bf
Original-Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214607
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9023
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These symbols should have been removed with the stack
refactoring. I'm not sure how it was missed.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel with both cpus.
Change-Id: Ia6c2103d7b5e2c9d74cdc5d1b5f42f8954812231
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d9432b5cf0cce3bfdbfd5371fb3280e3cc746a42
Original-Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215541
Reviewed-on: http://review.coreboot.org/9024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instruct the SoC to bring up the 2nd core.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Brought up 2nd core in Linux.
Change-Id: I4b31ea5f1466c43abce273b2bfb6a4d06b7faa63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74c62e62a6790de65e303123abee2be1dfffbee3
Original-Change-Id: I5f5febc4719951188106041f73625231eafe1b08
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214778
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9022
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Until PSCI is functional the other core still needs to be
brought up in the kernel. The kernel boots these cpus with
the spin table which is just an address in memory to monitor
a jump location.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up secondary core in linux.
Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca
Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214777
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Optionally bring up secondary cpu according to devicetree.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and enabled bringing up second core on ryu.
Change-Id: I5ede8b2f1b30a6170520cc11c18e263793cea301
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7da2dcce9be653a3c551c33bbefb3810a6949e9
Original-Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214776
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9020
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provides a minimal API for coordinating with the SoC for
bringing up the secondary CPUs. There's no eventloop or
dispatcher currently nor does it do anything proper when
one of the secondary CPUs are brought up. Those decisions
are deferred to the SoC.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu using this API.
Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376
Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214775
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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For the secondary CPUs the set of banked registers needs to be
initialized. In the boot CPU path all both the CPU's banked
registers and the global register set is initialized.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu in kernel.
Change-Id: I3a7bc708f726c4435afca817a251790f536844d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 813b0a8b3faacf2342164d385e5837ebede29b18
Original-Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214774
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9018
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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exception_hwinit() provides a path for just setting the hardware
state. This allows for other CPUs but the boot CPU for setting up
the appropriate vector table.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel.
Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1
Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214773
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No need to pass in the same value for the ttb after just
calling mmu_init(). All current users are setting this once
and forgetting it.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8
Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214772
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To allow setting the entry point for the secondary CPUs
provide a pointer, c_entry, which contains the location
to branch to after setting up the stack.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel on ryu.
Change-Id: I03e54b081aa5ff70b90fbd7f1b243fdb4f42c5a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f692c5814ea5c7ff4895576e1db8361ff3b7d9fb
Original-Change-Id: Ic2f6c79cde708b24c379345aed1e2cc0760ccad8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214771
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9015
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Move the stack seeding out of assembly and into C so the
code in stage_entry.S can more easily be used. The seeding
of the stack doesn't touch at least 256 bytes to account
for current usage at time fo the call.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel on ryu.
Change-Id: Ib9659ec4265652461bde746140567f21533cc265
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f478cfe175aa674cdfdbbd890663eeaad9d82b1f
Original-Change-Id: I44004220a02b1ff06d27a0555eb4e96d9e213544
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214770
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9014
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Instead of defining the stacks by Kconfig options include
the stack sizes for all the CPUs including each of their
exception stacks. This allows for providing each CPU
on startup a stack to work with.
Note: this currently inherits CONFIG_STACK_SIZE from x86 because
of the Kconfig mess of options not being guarded.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into the kernel on ryu.
Change-Id: Ie5fa1a8b78ed808a14efeb1717b98d6b0dd85eef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6524993f016aac2ac8cd9dba9fbdd9a59260a2b6
Original-Change-Id: Ica09dc256e6ce1dd032433d071894af5f445acdb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214669
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9013
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Provide a common entry point arm64 cores coming out of reset. Also,
take into account CONFIG_ARM64_CPUS_START_IN_ELx to set the
correct SCTLR_ELx register. The SCR_EL3 initialization was removed
as that can be done in policy code in C later. Part of this refactor
allows for greater code reuse for the secure monitor.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=built and booted to linux on ryu
Change-Id: I429f8fd0cdae78318ac171722fa1377924665401
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f92a5a01f07bc370735d75d695aedd8e2ab25608
Original-Change-Id: If16b3f979923ec8add59854db6bad4aaed35e3aa
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214668
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9012
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The armv8 cores in tegra132 start in EL3. Indicate as such.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted Kconfig selection.
Change-Id: I80f323a7d14c5376c8233c42dcc28f64ef07c9a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8af81929a82e3b686026b2ea648145e5fee98970
Original-Change-Id: I83370a03cfc0f04058ae2b6d87b09b96642df97d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214667
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9011
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Depending on the armv8 implementation the cpus could start in
EL1, EL2, or EL3. Therefore allow the SoC to select the appropriate
mode.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I8787fd1bc4e14f03d829e6a5e5af915e29314770
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb6b092a43e34fbc64d941bb62f19a6b8ac2c5de
Original-Change-Id: Id063681ef7691097e528c105fffac5d467585e4e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214666
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9010
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There are 2 things wrong with the current implementation:
1. the stack isn't guaranteed to be aligned to CONFIG_STACK_SIZE.
2. the stack isn't necessarily CONFIG_STACK_SIZE bytes.
Utilize the smp_processor_id() function to obtain the correct
cpu_info structure to obtain the correct index.
BUG=chrome-os-partner:31545
BRANC=None
TEST=Built and booted.
Change-Id: I43d4a2baa26e48147bc0dbdb3e9e13ad023f0690
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e2c32b1a46ac8dc1364ed03c195322c0bf28dd7f
Original-Change-Id: I2825118e2313dbbf13712a4afdfa05a2e38ee3a4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214665
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9009
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Implement smp_processor_id() for the arm64 cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: Id2fca068f92cdc816b02b5e7ce1229517787684a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5c5c68329631ce0fc3cebef1c2422aa44ac192d
Original-Change-Id: I7a1cd2f94ba4ae1854450cc60ef8a62f2457aabb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214664
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9008
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to accomodate MP on arm64 one needs to be able to determine
the current logical processor id. Because it depends on the SoC
implementation the SoC needs to provide this implementation.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I2f09df9bf7d4f829d8f45471bf7281a4ddba2fc8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6033e73d70c3b8296b36ff36b4b848b176917e12
Original-Change-Id: I9511b54b5a1ab340b0f1309b0d9976be68b50903
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214663
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There are 2 cores visible to the OS and both need to be
brought up. Therefore, provide the proper number of cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted CONFIG_MAX_CPUS=2.
Change-Id: I8a99891506af0fb3aa0284475c3c4be8bb69268b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efa6c0343521dd98b86eacc94737f3497b721f95
Original-Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214661
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This just removes some unneeded symbols and comments. Additionally,
moved most of the absolute symbols into the individual sections.
Also, aligned data sections to 64 bytes (typical cache line size).
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted through coreboot normally on ryu.
Change-Id: I8ceed5a48078f70911122d304f2953795af0b421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0524d4769613dc4a762e0a8e1bc1d2549d2df743
Original-Change-Id: I304e3702247a06507f5f4e23f8776331a3562c68
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214662
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of relying on the encoding of gpio_get_in_tristate_values()
normalize the ids.
BUG=chrome-os-partner:31602
BRANCH=None
TEST=Built and noted correct output w/ coresponding correct device
tree selected in depthcharge.
Change-Id: I6fc712aceb56d701725759503b9cfa1061ed25d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1037d473f35613bf39a4b27a9c1ade718b852c0d
Original-Change-Id: I7d5449bc14e776fd9faa86af0f80690c3d9ae92d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214840
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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