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2018-08-13mb/google/poppy/variants/nocturne: remove icc_max overridesNick Vaccaro
Remove icc_max overrides to allow SoC code to set proper icc_max based on CPU SKU. BUG=b:78122599 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash to nocturne, boot to kernel and verify device doesn't hang after a few minutes. Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27996 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/poppy/variant/nocturne: update PL2 based on CPU skuNick Vaccaro
This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27997 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/poppy/variant/atlas: Update PL2 based on CPU skuGaggery Tsai
This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27765 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13intel/apollolake: Fix typo in dptf.aslChris Zhou
Fix define typo in dptf.asl BUG=none TEST=emerge-octopus coreboot PASS Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13mb/google/octopus/variants/fleex: Set up DPTF tableJohn Su
Follow thermal table (b:112274477 comment#1) for first tunning. BUG=b:112274477 TEST=Match the result from DPTF UI. Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13mediatek/mt8183: Add DRAM resource in ramstageTristan Shieh
Add DRAM resource in ramstage to load payload. BUG=b:80501386 TEST=Load bl31 and depthcharge correctly on Kukui with more patches applied. Change-Id: Ie793b403bbbdb3c231dfa2caef29dcbb596b1a61 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27971 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13security/vboot/Makefile: Use shell cat instead of make file commandRaul E Rangel
The make `file` command is apparently a v4.2 feature only. Replace it with a shell cat. BUG=none TEST=verified fwid.region was created correctly Change-Id: I5e32a521ad3e6759853f0cde2e4c4db6e564d3be Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-13soc/broadcom/cygnus: Increase romstage SRAM size in memlayoutPhilipp Deppenwiese
* Needed for additional code in later patches. * SOC is obsolete anyway. Change-Id: I5bbdf19cc886103e9e7a6b75219d6881cfe9c757 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23764 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/octopus: Enable SAR config for Intel 9560 moduleJohn Zhao
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key. coreboot reads the VPD and creates the ACPI table as per the WGDS spec. BUG=b:112288077 TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry. Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Do not configure IOStandby for WLAN_PE_RSTFurquan Shaikh
PERST signal is asserted/deasserted by ACPI routines during suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in failure to resume from suspend state with wake-over-WLAN. This change removes the IOStandby configuration for WLAN_PE_RST. BUG=b:112371978 Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Configure WiFi wake as NC when using CNViFurquan Shaikh
When CNVi is being used, external wake using GPIO_119 is not required. This change configures GPIO_119 as PAD_NC if CNVi is taken out of reset. BUG=b:112371978 Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12soc/intel/apollolake: Get rid of cnvi.aslFurquan Shaikh
There is no need to add a special cnvi.asl file for the CNVi device. This can be handled by drivers/intel/wifi just like a PCIe WiFi device. This change gets rid of the cnvi.asl file and its usage in southbridge.asl file. BUG=b:112371978 Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Use correct chip for CNVi deviceFurquan Shaikh
This change uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows up in ACPI node 2. It is possible to pass any parameters from devicetree to wifi driver for SSDT generation. BUG=b:112371978 Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12drivers/intel/wifi: Get rid of unused wrdd.aslFurquan Shaikh
This change gets rid of unused wrdd.asl in intel wifi driver. This file became redundant when all boards moved to using SSDT for wifi device. Change-Id: I8b5b3816d77c90e75052c58a3120ab62185873a7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27963 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12drivers/intel/wifi: Skip adding SSDT entry if device is disabledFurquan Shaikh
This change checks to ensure that device is enabled before adding entry into SSDT. BUG=b:112371978 Change-Id: Ibe4811bef8cf0978b7a82d66a32f96247b9c823d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/google/octopus: Dynamically disable CNVi/PCIe deviceFurquan Shaikh
This change checks to see if CNVi module is out of reset: 1. If yes, then PCIe device for WiFi is disabled. 2. If no, then CNVi device is disabled. BUG=b:112371978 Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-08-12soc/intel/apollolake: Add CNVi device to list of PCI devsFurquan Shaikh
This change adds CNVi device to list of PCI devs. BUG=b:112371978 Change-Id: I6def98db3846c2244812a9a2ce84340bd2149b48 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/google/octopus: Disable unused I2C2 in devicetreeFurquan Shaikh
I2C2 is unused on all octopus variants. This change disables it in devicetree. BUG=b:112458032 Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28016 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1Furquan Shaikh
This change updates GPIO configuration for fleex boards with id >= 1 This follows the same model as phaser: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. d. Disable unused I2C devices in devicetree. BUG=b:112458032 TEST=No errors observed on boot-up on fleex. Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/asus/maximus_iv_gene-z: Add VBTTristan Corrick
The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 3603). Tested with Linux 4.9 and everything works as expected. Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/28050 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-11drivers/pc80/tpm: add support for SLB9665 TPM2.0 moduleKamil Wcislo
SLB9665 are not initialized correctly. It looks like SLB9665 and SLB9660 return the same DEV ID. Initialize these devices according to TPM Kconfig selections. Tested on apu2 with following change: https://review.coreboot.org/#/c/coreboot/+/28000/ Change-Id: Ic20b9a65ef6a4ee392a9352f7c9bf01b2496f482 Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/21983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10soc/cavium/cn81xx: Fix minor thingsPatrick Rudolph
* Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10[HACK]cavium/cn81xx/soc: Don't advertise CAR area as usablePatrick Rudolph
It's broken. Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10lib/fit: support booting initrd placed above 4GiBPatrick Rudolph
Store initrd offset as 64bit integer. Tested on Cavium CN81XX EVB: The initrd could be loaded when placed above 4GiB. Previously it failed to find the initrd. Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10mb/google/octopus: add support for new shared memory configAaron Durbin
Allow for shared dram configuration by introducing a new table that collapses the common settings after removing the part numbers. When employing this scheme the part number comes from CBI. BUG=b:112203105 TEST=Placed part number in cbi. Faked out memory sku id. And enabled DRAM part num always in cbi. Everything checked out. Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-10src/drivers: Fix typoElyes HAOUAS
Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27916 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up CMOS filesAngel Pons
Options that were deemed unneceesary on other code reviews have been removed from the layout files. In addition, the checksummed range has been extended to cover sata_mode and gfx_uma_size. Change-Id: Id9e904f447809231806a786e39ed638f21e1bc5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard codeAngel Pons
I ported ga-h61m-s2pv based on the two Gigabyte b75m boards. Based on another mainboard's code review comments, this patch improves the code quality of these three similar boards. ga-h61m-s2pv is tested and confirmed to be working, but I cannot say the same regarding the other two mainboards as I do not have them. Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10fit: Handle decompression errors properlyPatrick Rudolph
Set payload to NULL in case of decompression errors. Fixes the attempt to boot a kernel that couldn't be decompressed. Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10src/soc/intel: Add new device IDs to support coffeelakeMaulik
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h 2. Add entry to identify CFL U GT and CPU to respective files 3. Add entry to identify CFL U to report_platform.c BUG=none BRANCH=none TEST=Boot to CFL U RVP board with this patch and check if coreboot is able to enumerate various devices and display correct component names properly in serial logs. Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-10arm64: Turn architectural register accessors into inline functionsJulius Werner
Accesses to architectural registers should be really fast -- they're just registers, after all. In fact, the arm64 architecture uses them for some timing-senstive uses like the architectural timer. A read should be: one instruction, no data dependencies, done. However, our current coreboot framework wraps each of these accesses into a separate function. Suddenly you have to spill registers on a stack, make a function call, move your stack pointer, etc. When running without MMU this adds a significant enough delay to cause timing problems when bitbanging a UART on SDM845. This patch replaces all those existing functions with static inline definitions in the header so they will get reduced to a single instruction as they should be. Also use some macros to condense the code a little since they're all so regular, which should make it easier to add more in the future. This patch also expands all the data types to uint64_t since that's what the actual assembly instruction accesses, even if the register itself only has 32 bits (the others will be ignored by the processor and set to 0 on read). Arm regularly expands registers as they add new bit fields to them with newer iterations of the architecture anyway, so this just prepares us for the inevitable. Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Drop checks for current exception level, hardcode EL3 assumptionJulius Werner
When we first created the arm64 port, we weren't quite sure whether coreboot would always run in EL3 on all platforms. The AArch64 A.R.M. technically considers this exception level optional, but in practice all SoCs seem to support it. We have since accumulated a lot of code that already hardcodes an implicit or explicit assumption of executing in EL3 somewhere, so coreboot wouldn't work on a system that tries to enter it in EL1/2 right now anyway. However, some of our low level support libraries (in particular those for accessing architectural registers) still have provisions for running at different exception levels built-in, and often use switch statements over the current exception level to decide which register to access. This includes an unnecessarily large amount of code for what should be single-instruction operations and precludes further optimization via inlining. This patch removes any remaining code that dynamically depends on the current exception level and makes the assumption that coreboot executes at EL3 official. If this ever needs to change for a future platform, it would probably be cleaner to set the expected exception level in a Kconfig rather than always probing it at runtime. Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Remove set_cntfrq() functionJulius Werner
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of others that are all accessed through the raw_(read|write)_${register}() family of functions. There's no reason why this register in particular should have an inconsistent accessor, so replace all instances of set_cntfrq() with raw_write_cntfrq_el0() and get rid of it. Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10marvell: Remove 'mvmap2315' SoCJulius Werner
I'm pretty sure this SoC doesn't actually exist. Change-Id: I53e268ee1795e524a2a4562d67a2b9f28af966d1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10google: Remove board 'rotor'Julius Werner
Rotor is dead, long live [PROJECT NAME REDACTED]! Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27964 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: add support for fetching DRAM part number from CBIAaron Durbin
Add 3 new Kconfig options: DRAM_PART_NUM_IN_CBI DRAM_PART_NUM_ALWAYS_IN_CBI DRAM_PART_IN_CBI_BOARD_ID_MIN These control whether to 1. attempt to use CBI at all 2. always use cbi and 3. conditionally use cbi based on board id. The intent is that the MIN variant would be used for the tranisition period then cut over to ALWAYS after full transition. Since multiple OEMs have different schedules these options are there to bridge the gap. yorp. bip, and octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case someone does the MIN values are 255 to always take the old path. BUG=b:112203105 TEST=Set correct part number on phaser during testing. Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09arch/x86/tables.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure arch_write_tables, the pointer "rom_table_end" is updated every time a table is created. However, after creating last table, pointer rom_table_end is not used, though it is updated. Add a "(void)rom_table_end;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a34026795c7f0d1bb86c5f5c0469d40aa53994a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09cpu/x86/mp_init.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure save_bsp_msrs, the structure pointer "msr_entry" is updated every time procedure save_msr() is called. However, after the last call of save_msr(), "msr_entry" is not used, thus causing a static analysis error. Add a "(void)msr_entry;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0fb336fbf49eec3da255fadbe38b3a38768d0cf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/cpu: Fix typoElyes HAOUAS
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device: Fix typoElyes HAOUAS
Change-Id: I65e57b37db9649b30ca25b2150f21ebffee73105 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/ec/google/chromeec: Fix typoElyes HAOUAS
Change-Id: Ia05c9c5233319fe74d81c1f1db6ca3c2d875f9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/include: Fix typoElyes HAOUAS
Change-Id: Iff445dccf29957078b8308d73fb302d03cf47d31 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/lib: Fix typoElyes HAOUAS
Change-Id: Ie5bf036a63a254dd95b45a0823086c8079eeafe2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/mainboard: Fix typoElyes HAOUAS
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/arch: Fix typoElyes HAOUAS
Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/northbridge: Fix typoElyes HAOUAS
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/security/vboot: Fix typoElyes HAOUAS
Change-Id: Ie98ee00a83d837b6d6491fed3a474048dc23e104 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/superio: Fix typo and remove unneeded whitespaceElyes HAOUAS
Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09google/grunt: Override BayHub EMMC driving strengthKevin Chiu
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09drivers/spi/spi_flash.c: Check input parameterRichard Spiegel
In procedure spi_flash_cmd_erase(), parameter "len" is not validated and could lead to the return of an invalid (non-initialized) value. Validate the parameter early on. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0b5129a15c9e0ea45f4dba4ab0729196cb64699b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device/pci_rom.c: Remove double initializationRichard Spiegel
In procedure pci_rom_probe(), variable vendev is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a71aa1aea2047ab2d98e09d1d6610de552b6cb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27949 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09arch/x86/exception.c: Remove double initializationRichard Spiegel
In procedure exception_init(), structure pointer gates is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27948 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09cpu/x86/mp_init.c: Fix error treatmentRichard Spiegel
In procedure allocate_cpu_devices(), if structure pointer new is null skip using the pointer. Add a "continue;" to skip using the pointer. The issue was found by static analysis tool. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7011fbfa0725f22a6dfbca6752e668eddac3463c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27951 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: remove disable_periodic_retraining optionsAaron Durbin
The Micron material that was broken has long since been fixed that required this option. glkrvp had these stale entries and were subsequently copied to octopus. Remove the need for this option. BUG=b:35581751 Change-Id: Id73584367c2ad0e4958b5ea0f04a28e5fc82d085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09cpu/intel/smm: Make sure SMRR base is aligned to SMRR sizeArthur Heymans
If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09rk3288: Dig up two more KB of SRAM from under the couch cushionsJulius Werner
RK3288 has always been notoriously low on SRAM, to the point where its boards have less than 100 bytes left in both their bootblock/verstage sections. This becomes a problem every time we try to add a tiny amount of code to common coreboot interfaces that are included in them. This patch manages to add another KB to each, one from the CBMEM console (which now might get cut off a bit, but that's life) and one by moving the TTB_SUBTABLES to PMUSRAM. PMUSRAM is a weird world where write accesses must always be exactly 4 bytes long or they hang the CPU, so we mostly ignore it... but thankfully, page table entries are exactly 4 bytes long and that's the only thing we write to this region, so it works out in this case. Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-09drivers/spi/winbond: Improve structure packingPatrick Rudolph
Use bitfields to pack the struct more tightly. Change-Id: If1e7a5a3a9504327f987403ec0a7b79b2383792a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27815 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09superio: fix and extend pnp_info of wpcd376iStefan Tauner
The implementation of wpcd376i in coreboot is based on the superiotool output which apparently was incorrect. This patch refines the implementation to match the datasheet. Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-09lib/edid.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure cea_hdmi_block, the variable "b" is used as an index into a buffer of EDID bytes. At the end, it's incremented but not used, thus causing a static analysis error. Add a "(void)b;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: Ibd0b4a21bf82fcc46a627bc75564a850b7374989 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27929 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/poppy/variants/atlas: Do not override icc_maxCaveh Jalali
Skylake SoC code now sets the icc_max based on the CPU SKU, so we should not hard-code it in the device tree. BUG=b:110890675 BRANCH=None TEST=boots on atlas Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-08-08security/tpm: Report tpm_unmarshal_response warningRichard Spiegel
In procedure tpm_unmarshal_response(), variable "rc" is used early to decide if it should return NULL. Later however, the code proceeds to its end even if one subroutine reports error. If "rc" is not 0, report that there was a partial error in the procedure. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7575bc75104fd97f138224aa57561e68f6548e58 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08security/vboot: Split fwid.region build targetRaul E Rangel
Add the ability to specify the fwid version via a file instead of via config. This makes it so when doing an incremental build all objects are not invalidated when bumping the fwid. The coreboot ebuild will create this file to pass the latest version. BUG=b:112267918 TEST=ran dmidecide -t 0 and verified version was present Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-08mainboard/google/kahlee: Set SYSTEM_TYPE_LAPTOPRaul E Rangel
This configures the ACPI FADT perferred power management profile to PM_MOBILE instead of PM_DESKTOP. I'm not sure what impact this actually has. I just noticed the other boards have it set. BUG=b:110971913 TEST=Made sure SYSTEM_TYPE_LAPTOP shows up in coreboot.config Change-Id: Iea1b8359b80d167e69745358f543f025713294ba Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08soc/amd/stoneyridge: Prevent reboot in romstageRaul E Rangel
By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/stoneyridge: Dump MCA registersMarshall Dawson
Add a function to provide a rudimentary dump of the Machine Check Architecture registers. These values survive a warm reset. BUG=b:65445599 TEST=Verify on a Grunt having propensity for #MC errors Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/fam15: Add MCA bank register definitionsMarshall Dawson
Define the additional registers used for each Machine Check Architecture bank. Change-Id: I962f23662789a3b974f4946555f67fcfc6147df8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/stoneyridge: Add warm reset detectionMarshall Dawson
Extend the existing reset handling features in Stoney Ridge to plan for, and recognize, warm resets. The ColdRstDet bit is always zero on a cold reset, and is intended as a mechanism for the BIOS to determine the type of a reset that occurred. Set ColdRstDet=1 after all cores have been initialized, so that any subsequent reset may be identified as warm/cold. A later patch will check the value during mp_init. Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Improve formattingMarshall Dawson
Remove for() braces from around single lines. Remove extra blank lines. This cleans up checkpatch problems in a subsequent patch. Change-Id: I329ac03365e51799581c56eed27ee54de6826f14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Rename MCA status registerMarshall Dawson
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-08ec/google/chromeec: add support for retrieving DRAM part numberAaron Durbin
The DRAM part number can be stored in the CBI data. Therefore, add support for fetching the DRAM part number from CBI. BUG=b:112203105 TEST=Fetched data from CBI on phaser during testing. Change-Id: Ia721c01aab5848ff36e11792adf9c494aa25c01d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: add new dimm info saving APIAaron Durbin
The current call for saving dimm info passed the lpddr4_cfg and memory sku id. In order to prepare decoupling the part number from lpddr4_cfg provide a new API, save_lpddr4_dimm_info_part_num(), which explicitly takes the part number. The previous API now uses the new one internally. BUG=b:112203105 Change-Id: Ieadf452b6daa3231a0c5e3be61b0603b40d0fff2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: Add support for LPDDR4 nWR settingRavi Sarawadi
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to be set to 24 clock cycles. The nWR field, though, is only in the GLK FSP, so just update that field conditionally based on the GLK Kconfig option. BUG=b:112062440 TEST= build test Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/amd/stoneyridge/acpi.c: Remove fixed value variablesRichard Spiegel
In procedure generate_cpu_entries(), the code was copied from code that could change variables "plen" and "pcontrol_blk" based on number of cores. This is not the case with stoneyridge (2 cores only), and there's no need to use the variables. Remove them and replace with fixed values. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27877 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08device/pci_device.c: Remove unused variable attr settingRichard Spiegel
In procedure pci_get_resource, when setting an IO mapped base address, variable attr is &= with PCI_BASE_ADDRESS_IO_ATTR_MASK. However, in this particular code flow variable attr is not used later. Remove the line. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: Ia4fdda1be92d22017a7a913a911db15aaa440b69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08lib/bootmem.c: Remove unused setting of variable "begin"Richard Spiegel
The variable "begin" is extracted from the structure, but 4 lines below it's overwritten with "end - size". This causes a static build scan error that should be fixed. Remove the initial assignment of variable "begin". BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0a265747e61289f045c5cac09e40478bd31e16fc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27886 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08mb/intel/cannonlake_rvp/devicetree: Remove spurious CPP directivesArthur Heymans
The devicetree is not run through a C pre-processor, so remove it. Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27927 Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08src/soc/intel/common: Configure the gspi chip select state correctlyAamir Bohra
This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/27889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-07arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner
cache_sync_instructions() has been superseded by arch_program_segment_loaded() and friends for a while. There are no uses in common code anymore, so let's remove it from <arch/cache.h> for all architectures. arm64 still has an implementation and one reference, but they are not really needed since arch_program_segment_loaded() does the same thing already. Remove them. Leave it in arm(32) since there are several references (including in SoC code) that I don't feel like tracking down and testing right now. Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07arm64: Disable MMU during legacy payload handoff (without Arm TF)Julius Werner
coreboot payloads expect to be entered with MMU disabled on arm64. The usual path via Arm TF already does this, so let's align the legacy path (without Secure Monitor) to do the same. Change-Id: I18717e00c905123d53b27a81185b534ba819c7b3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07sdm845: Implement bitbang UART for bootblockJulius Werner
This patch replaces the UART in the bootblock of SDM845 with a bitbang implementation. Since SDM845 hardware UART needs a firmware blob loaded into it before it becomes usable, it is not really suited for use in the bootblock (since by the time we can read blobs from SPI, the bootblock is essentially over anyway). This solution allows us to still have some console output during early SoC initialization. Change-Id: I0c252ec83a7993edce5c4debc687f1fdd0d7b36d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07security/tpm: Check for NULL pointerFurquan Shaikh
Change bce49c2 (security/tpm: Improve TCPA log generation) missed checking for NULL pointer before accessing the tcpa_table returned by tcpa_log_init. This change fixes the boot hang observed on octopus by ensuring pointer is checked for NULL before using it. BUG=b:111403731 TEST=Verified that octopus boots up fine. Change-Id: I2e46197065f8db1dc028a85551546263e60d46b2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07sb/intel/i82801[ijg]x: remove stale board-specific comments from ich*.aslStefan Tauner
Apparently they were introduced when refining ICH7 support when porting Kontron 986LCD-M and then copied over to ICH9 and 10. Change-Id: I2d9ece608955310d22b79574b9113a1521b2076c Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-07mb/google/poppy/variants/nautilus: Set CABC_EN to GPO high before EDP power onSeunghwan Kim
If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on, it may cause damage on the GPIO pad. To prevent, we would set this pad to GPO on romstage before EDP power on. Since we need to cover all systems in market, I put it into romstage instead of early_gpio_table. BUG=b:111860510 BRANCH=poppy TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-07mb/google/poppy: Add variant callback for romstage GPIO configurationFurquan Shaikh
This change adds variant callback to get GPIO configuration table in romstage and configures these GPIOs before memory training is performed. BUG=b:111860510 BRANCH=poppy Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07mb/google/poppy/variants/nautilus: Add SKU info to SMBIOSFurquan Shaikh
This change provides implementation of smbios_mainboard_sku() to add proper "skuX" string to SMBIOS table 1. BUG=b:112163362 TEST=Verified "dmidecode -t 1" reports skuX correctly. Change-Id: I7e42d2c80d791ea7170d066d2eeaa0c6811eb9c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06soc/amd/stoneyridge: Call AMD ALIB method with AC/DC stateMarc Jones
AMD ALIB Function 1 accepts the AC/DC startup state. This is reported to be required for AMD PSPP settings. BUG=b:112020107 TEST= build test Change-Id: Ibb6c872d84745217912956c15d6ca2e8ba387561 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27785 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06mainboard/google/kahlee: Add PSPP override settingMarc Jones
Add default PSPP AGESA setting for Kahlee/Grunt mainboards. BUG=b:112020107 TEST= build test Change-Id: I8a8605402379de88a04f3a16553c308513fa1531 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06google/grunt: Move PSP_SELECTABLE_SMU_FW to socRichard Spiegel
Now that an updated bootloader with important fixes is available at coreboot repository, all stoneyridge boards should use it. Move the selection of SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge. BUG=b:111428800 TEST=Build and boot grunt. Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27844 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06src/soc/intel: Add AML IGD in platform reportingGaggery Tsai
This patch revises IGD naming and adds AML IGD in platform reporting. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown in platform reporting. Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06soc/intel/skl: Add AML IccMax and remove unused infoGaggery Tsai
This patch adds AML IccMax for VR configuration. From doc #594883, the IccMax for Core was changed to 28A, we need this patch to accommodate the changes. Besides, removes unused sku information from sku_icc_max_mapping structure. BUG=b:110890675 BRANCH=None TEST=Remove icc_max from DT & emerge-atlas coreboot chromeos-bootimage & Tested with AML-Y and KBL-Y SKUs. Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27610 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06mb/google/octopus/variants/baseboard: Update Power Limit1Sumeet Pawnikar
Update power limit1 value from 8W to 10W. There is an error in the energy calculation for current VR solution on GLK. Experiments show that when power limit1 set to 10W, gained performance improvement with SoC TDP reaches max (6W) power. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06soc/amd/stoneyridge: Enable spread spectrum in bootblockRaul E Rangel
setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt ConfigKane Chen
From doc 571118, the bit 5 of OdtConfig is nWR config. If the bit 5 is set, MRC will set MR1 nWR field to 24. If the bit 5 is clear, MRC will set MR1 nWR field to 6. Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/27814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06mb/google/octopus/variants/fleex: Enable Weida touchscreen deviceCrystal Lin
This change adds ACPI properties for WDT8752A device. BUG=b:111402335, b:111102092 BRANCH=master TEST=Verify touchscreen on fleex works with this change Change-Id: Id186d5b87343007ae7e631d5d27464ee27e5b27d Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add rammus devicetree.cbZhuohao Lee
Use the default value for Iccmax which is specified in vr_config.c. The AcLoadline and DcLoadline keep the poppy value. Besides, the USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT and the others on the daughterboard are set to USB2_PORT_LONG. Those setting need to be fine tuned later. BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: Icabfac04c94b3d480872c243d811509e274ef122 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06mb/google/poppy/variants/rammus: add gpio settingZhuohao Lee
The gpio setting is based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>