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2016-08-08drivers/elog: use offsets for checking cleared buffersAaron Durbin
There's only 2 users of checking if the event buffer is cleared to the EOL value. Each were passing pointers of the in-memory mirror while also doing calculations for the size to check. Since the in-memory mirror is one big buffer the only thing required to know is the offset to start checking from. The check is always done through the end of the buffer. BUG=chrome-os-partner:55932 Change-Id: Icd4a7edc74407d6578fc93e9eb533abd3aa17277 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16096 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08sconfig: pass in devicetree filenameMartin Roth
Instead of forcing the hardcoded 'devicetree.cb' filename under the mainboard directory, this allows mainboards to select a filename for the devicetree file. This allows mainboard variants that need to use different devicetree files to live under the same directory. Change-Id: I761e676ba5d5f70d1fb86656b528f63db169fcef Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12529 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-08drivers/elog: perform writes in terms of offsetsAaron Durbin
Instead of taking pointers and back-calculating the proper offset perform writes in terms of the offsets within the elog region in flash. BUG=chrome-os-partner:55932 Change-Id: I5fd65423f5a6e03825c788bc36417f509b58f64d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16095 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-08-08supermicro/h8scm: Remove last unused chip.h fileMartin Roth
Change-Id: I84d61c8ade6e42e314a31e1155b4d5628b16199a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16081 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-08drivers/elog: remove parameters from elog_flash_erase()Aaron Durbin
The elog_flash_erase() was only called to erase the entire elog region in flash. Therefore, drop the parameters and perform the full erase. BUG=chrome-os-partner:55932 Change-Id: I6590347ae60d407bc0df141e9196eb70532f8585 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16094 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: remove unnecessary check in elog_shrink()Aaron Durbin
There was a check against the next event offset against the shrink size in elog_shrink(). However, all calls to elog_shrink() were conditionalized on the next event offset exceeding the full threshold. The shrink size is set to the minimum of the full threshold and a percentage of the elog region size. Therefore, it's impossible for the next event offset to be less than the shrink size because full threshold is always greater than or equal to the shrink size. BUG=chrome-os-partner:55932 Change-Id: Ie6ff106f1c53c15aa36a82223a235a7ac97fd8c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16093 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: use event region size when adding a clear eventAaron Durbin
For the elog shrink case we log the number of bytes shrunk from the event log. However, when clearing the log the size recorded was the entire region size including the header as well as the event region space. To be more consistent mark the clearing event with the number of bytes actually cleared out (excluding the header size). BUG=chrome-os-partner:55932 Change-Id: I7c33da97bd29a90bfe975b1c6f148f181016f13f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16092 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: remove unused functionAaron Durbin
get_rom_size() is no longer used. Remove it. BUG=chrome-os-partner:55932 Change-Id: Id9fa8f67b67ee355243a5c763cfafa0ce76e9b2b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16088 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08soc/intel/common: fix gsmi handlerAaron Durbin
The gsmi_exec() expects the parameter to be a pointer to the 32-bit register storage of the SMI save state. The previous code was passing a pointer with the value obtained from the saved-state -- not a pointer to the storage of the register value. This bug causes gsmi to not log events because it's interrogating the parameter buffer itself as if it were a pointer. BUG=chrome-os-partner:55932 Change-Id: I37981424f1414edad1456b31cad1b99020d57db6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16087 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08chromeos chipsets: select RTC usageAaron Durbin
Since RTC is now a Kconfig ensure RTC is selected on the x86 chipsets which are in Chrome OS devices. This allows the eventlog to have proper timestamps instead of all zeros. BUG=chrome-os-partner:55993 Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16086 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08vendorcode/google/chromeos: remove unnecessary includes in elog.cAaron Durbin
The elog.c file had stale includes no longer needed. Remove them. BUG=chrome-os-partner:55932 Change-Id: I891a57d08281c3c56e9d35489d6dea6c47eaa27b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16085 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08commonlib/region: make buffer argument const for writeatAaron Durbin
The buffer for writeat() should be marked as const as the contents won't be manipulated within the call. BUG=chrome-os-partner:55932 Change-Id: I968570c1cf80f918a07b97af625a56f11b5889c1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16084 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08soc/intel/skylake: Clean up SoC ASL code.Barnali Sarkar
List of changes done here in this patch 1. Remove CARD definition from EMMC and SD Card Controller in scs.asl since _RMV method does not get evaluated while setting up removable attribute in sysfs in kernel. "cat /sys/block/mmcblk1/removable" this command always returns 0. This CARD Device includes _ADR which follows SDIO Bus format. But, SD/EMMC sits on PCI Bus. Hence this CARD Device specific _ADR code is also not needed. 2. Remove Base Address for ACPI debug output memory buffer in systemagent.asl as it is not getting used throughout the code. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: I29effaffdafcc21e26445ec3c54aedecdbc50274 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16068 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08soc/intel/skylake: Cleanup patch for Skylake SoCBarnali Sarkar
Here is the list of items of code cleanup 1. Define TCO registers in smbus.h and not in pmc.h (as per EDS). 2. Include smbus.h wherever these TCO register defines were used. 3. Remove duplication of define in gpio_defs.h. 4. Remove unnecessary console.h include from memmap.h as no prints done. 5. Remove unnecessary comment from pch.c. BUG=none BRANCH=none TEST=Built and boot kunimitsu. Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16027 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08google/reef: Configure SDIO D1 to enable SCS Power GatingJagadish Krishnamoorthy
SDIO D1 pin needs to be configured as Native mode to enable SCS Power Gating. BUG=chrome-os-partner:54251 TEST=Verify SCS Power Gating Change-Id: Ic33b26443203217678e11d195eb965a7e628ad82 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/16062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-08google/chromeec: Enable/Disable ccache with config variableMartin Roth
If the CONFIG_CCACHE variable is NOT set, define the CCACHE variable as blank on the Chrome EC make command line. This will overrride and disable the CCACHE variable in the Chrome EC makefile. Change-Id: Idb1da06941084cea104d77748820971edf151f7b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16035 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-08vendorcode/amd/pi/Lib: Fix reporting fatal errorPatrick Georgi
Instead of writing the first word of 6 "post code structs" where only one exists (leading to 0xDEAD and 5 garbage words), write the correct set. Change-Id: Ifdfa53a970dda33dc9dc8c05788875077c001ecf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1361054, #1361055, #1361056 Reviewed-on: https://review.coreboot.org/16058 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-08Use VBOOT_SOURCE instead of hardcoding vboot pathPaul Kocialkowski
This replaces all occurrences of a hardcoded vboot path to the VBOOT_SOURCE variable, that may be overridden from the command line, witch fallback to the source from 3rdparty. Change-Id: Ia57d498d38719cc71e17060b76b0162c4ab363ed Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-08-06soc/intel/skylake: Add Kabylake device IdsRizwan Qureshi
Adding kabylake device ids for chip inits. Skylake and Kabylak do not differ much, the intention is to support both SoCs in the same code base. Change-Id: I9ff4c6ca08fe681798001ce81cca2c085ce32325 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16049 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-06google/reef: Enable I2C2 for use in bootblockDuncan Laurie
Enable I2C bus 2 for early init so it can be used by vboot for TPM communication for verifying the memory init code. BUG=chrome-os-partner:53336 BRANCH=none TEST=build and boot on reef Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16059 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-06acpi: Generate object for coreboot table regionDuncan Laurie
Generate an object to describe the coreboot table region in ACPI with the HID "CORE0000" so it can be used by kernel drivers. To keep track of the "CORE" HID usage add them to an enum and add a function to generate the HID in AML: Name (_HID, "CORExxxx") BUG=chromium:589817 BRANCH=none TEST=build and boot on chell, dump SSDT to verify contents: Device (CTBL) { Name (_HID, "CORE0000") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadOnly, 0x7AB84000, // Address Base 0x00008000, // Address Length ) }) } Change-Id: I2c681c1fee02d52b8df2e72f6f6f0b76fa9592fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16056 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-06drivers/intel/fsp1_1: only set a base address for FSP in COREBOOT CBFSAaron Durbin
The -b FSP_LOC argument to cbfstool is only valid for the COREBOOT CBFS. Don't pass that value for all other CBFS regions. Change-Id: Ib5321e7a7dbee8d26eb558933c8ce3fea50b11fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05drivers/intel/fsp2_0: Ensure EC is in right mode before memory initFurquan Shaikh
If EC_GOOGLE_CHROMEEC is enabled, ensure that the EC is in correct mode before running memory init. This saves additional memory training required in recovery path because of reboot later in ramstage. BUG=chrome-os-partner:54245 Change-Id: Ic71c054afdcd0001cea95563fe513783b56f3e60 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05google/reef: Correct SD card pins configChiranjeevi Rapolu
SD CLK and CLK_FB needs to be pulled down by 20K. SD CD_N is active LOW, needs to be pulled up by 20K SD WP pin is not connected for uSD cards, enable writes by default by pulling low by 20K. BUG=chrome-os-partner:54866 BRANCH=None TEST=Test with uSD cards. Change-Id: Ia4bbd966ffb21e276dfc31a74f4ea54718900d66 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05soc/intel/quark: Add missing breaksLee Leahy
Add missing breaks in reg_access.c. TEST=Build and run on Galileo Gen2 Found-by: Converity Scan #1361261 Change-Id: I8be57f0758e5918a605e20ab9002747e0cc958e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16069 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-08-05drivers/spi: Add support for Micron N25Q128AWerner Zeh
Although we have already support for the flash chip N25Q128 there is a similar type available which has the same geometry and opcodes but unfortunately a slightly different device type ID. While the already supported N25Q128 has the ID 0xbb18 this one has the ID 0xba18. To make both types available in the flash support table, use N25Q128A as the flash name. This name can be found in the datasheet which can be found here: https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf TEST=Booted and verified that MRC cache could be written Change-Id: I02a47692efb23a9a06a289c367488abd256b8e0c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16061 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05drivers/intel/fsp2_0: Add checklist supportLee Leahy
Add the Kconfig value to point to the checklist data files. TEST=Build and run on Galileo Gen2 Change-Id: I3737b46162214fad139382193de944ec5d175645 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16039 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05soc/intel/quark: Add bootblock_c_entryLee Leahy
Add the bootblock_c_entry routine to make it more explicit where the code transitions from assembler to C. TEST=Build and run on Galileo Gen2 Change-Id: Ib5f580c30b58d3c82fedddf63c368e617d401515 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16064 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05soc/intel/quark: Clean up debug output levelsLee Leahy
Change the debug output levels for quark: * Remove excess debug output * Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c TEST=Build and run on Galileo Gen2 Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16006 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05soc/intel/quark: Disable FSP serial outputLee Leahy
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8 (BIOS_SPEW). Use the console log level to choose between the serial port address and NULL and pass it to FSP for the serial port address. TEST=Build and run on Galileo Gen2. Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16005 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05soc/intel/quark: Add FSP 2.0 romstage supportLee Leahy
Add the pieces necessary to successfully build and run romstage using the FSP 2.0 build. Because romstage is using postcar, add the postcar pieces so that romstage can attempt to load postcar. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15866 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05soc/intel/quark: Add FSP 2.0 boot block supportLee Leahy
Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-04sb/amd/sb700: Do not reset fifo after skipping the sent bytesTimothy Pearson
Port commit e08493 to the SB700 platform Change-Id: Ie18c6cc0ccb31a0d16a80fcb4c2e147c19e228fe Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16054 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
In some cases, we don't want the Chrome EC firmwares (both EC and PD) built directly by the coreboot build system or included in images at all. This is already supported with EC_EXTERNAL_FIRMWARE but it does implement a binary (build and include) or (neither build nor include) policy. Some cases require the ability to separately control whether the EC and PD firmwares should be built and included by the coreboot build system, only included from externally-built images or not included at all. This introduces config changes implementing that behaviour, renaming options to make it clear that they are specific to the Chrome EC. Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
Change-Id: Ide87c45806c5e58775c77e7f780efb4cf81a70c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16014 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-04soc/apollolake: Return correct wake status in _SWSShaunak Saha
Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-04soc/intel/apollolake: Configure gpio ownershipJagadish Krishnamoorthy
For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-04google/reef: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: If5a6a1cb8f065a8c3a6a19d9441a21d60b39e579 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16031 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-04soc/intel/skylake: Correct address of I2C5 DeviceBarnali Sarkar
This corrects the address of the I2C5 Device. The I2C Controller #5 is on PCI Bus 0: Device 25: Function 1. The ACPI Address Encoding Logic is - High word = Device #. Low word = Function #. So, I2C5 (_ADR) = 0x0019 0001. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: I4719a843260ef58cc2307e909e9ccbffea519177 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16048 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-04lib/timestamp: Add timestamps to CBMEM in POSTCAR stageFurquan Shaikh
POSTCAR stage has cbmem online. So, all timestamps need to be added to cbmem timestamp region. BUG=chrome-os-partner:55848 TEST=Verified that timestamps added in postcar show up in cbmem -t. Change-Id: I64af8c1e67b107d9adb09de57c20ea728981f07c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16032 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-03lenovo/x60: Fetch 16 bits when trying to parse bit 13Patrick Georgi
I'm not sure if that's the right fix here, but assuming the bit mask is right, the inb is wrong. Change-Id: I7e33019af088780a09be12513200bec63734bf97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229556 Reviewed-on: https://review.coreboot.org/16026 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-08-03sb/amd/sb[6|7|8]00: Initialize PICTimothy Pearson
The PIC was not initialized, leading to hangs when booting Linux as a payload. This error was hidden by both SeaBIOS and GRUB due to both payloads initializing the PIC as a matter of routine. Change-Id: I9a3b9bd831d4dafdd0bb82ea023026a10fe7efca Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16018 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-08-03spi/tpm: read TPM version in larger chunksVadim Bendebury
The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's read 50 bytes at a time to reduce the SPI register read wrapper overhead, and increase the length limit to 300 bytes to accommodate longer version strings. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/16000 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03google/gale: Add more board ID variantsKan Yan
EVT1 has two board IDs. Use binary first mode of base3 encoding for board ID. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I1cac1f74207f42616111d39db5c0494b7d1a0fb2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2b16cc74c4c147315b7db345678bbaf536ab4a7b Original-Change-Id: I6e95c7be4a6d28a0aae38b0838bd2ab71d288ba1 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364623 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/16030 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add code to support I2C TPM for KevinJulius Werner
Coming Kevin revisions will switch back to an I2C TPM. This patch adds the required configuration options and code to support that. Since the TPM type can currently only be changed at compile time, we can no longer support older Kevins with the same image. In order to build for Kevin revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2. BRANCH=None BUG=chrome-os-partner:55523 TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage binary had the appropriate code differences. Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9 Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364222 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16029 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add support for Gru rev1Julius Werner
This patch adds support for the Gru rev1 board. This board differs from rev0 by no longer relying on the I2C backlight booster and requiring the same ODT SDRAM settings as newer Kevin boards. BRANCH=None BUG=chrome-os-partner:55087 TEST=None Change-Id: I1428760540a0aaaa0c02c6cb5b0981294ba4df33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8de7bcc78c6c48c251c85185e238cea7812f7a28 Original-Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364624 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16028 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03soc/intel/quark: Support access to CPU CR registersLee Leahy
Add support to access CR0 and CR4. TEST=Build and run on Galileo Gen2. Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03mainboard/intel/galileo: Add FSP 2.0 Kconfig supportLee Leahy
Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15864 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03soc/intel/quark: Add header files for FSP 2.0Lee Leahy
Add the FSP 2.0 header files for Quark. These files were run through the drivers/intel/fsp2_0/header_util to convert the data types so that they are compatible with the coreboot build system. TEST=Build and run on Galileo Gen2. Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15863 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03soc/intel/quark: Prepare for FSP2.0 supportLee Leahy
Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03soc/intel/quark: Initialize MTRRs in bootblockLee Leahy
Initialize the MTRRs for use by bootblock and romstage. Display the MTRRs. TEST=Build and run on Galileo Gen2. Change-Id: Ib1d422c738820163f54771c65034ae77301237ec Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15861 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03soc/intel/quark: Remove use of EDK-II macros and data typesLee Leahy
Include assert.h to use coreboot's ASSERT macro. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2 Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15858 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03fsp_broadwell_de: Add DMAR table to ACPIWerner Zeh
Create DMAR table for Broadwell-DE SoC. TEST=Booted MC BDX1 into lubuntu15, dumped ACPI tables with acpidump and disassembled DMAR table using iasl. The table contents are as expected and the kernel loads DMAR table without errors. Change-Id: I7933ba4f5f0539a50f2ab9a5571e502c84873ec6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15913 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
PCI root ports with "Address Translation Service" capability can be reported in DMAR table in the ATSR scope to let the OS know how to handle these devices the right way when VT-d is used. Add code to create an entry for a PCI root port using the type "SCOPE_PCI_SUB". Change-Id: Ie2c46db7292d9f1637ffe2e9cfaf6619372ddf13 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15912 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
DMAR tables can contain so called "Address Translation Service Reporting" (ATSR) structure. It is applicable for platforms that support Device-TLBs and describe PCI root ports that have this ability. Add code to create this ATSR structure. In addition, a function to fix up the size of the ATSR structure is added as this is a new type and using the function acpi_dmar_drhd_fixup() can lead to confusion. Change-Id: Idc3f6025f597048151f0fd5ea6be04843041e1ab Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15911 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03mainboard/intel/galileo: Remove use of EDK-II macros & data typesLee Leahy
Add assert.h to use coreboot's ASSERT macro. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15859 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03soc/intel/quark: Make ramstage relocatableLee Leahy
Relocate ramstage into CBMEM. TEST=Build and run on Galileo Gen2 Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15994 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-03drivers/intel/fsp2_0: Update the debug levelsLee Leahy
Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Remove fsp_print_upd_info declarationLee Leahy
Remove unused function declaration. TEST=Build and run on Galileo Gen2 Change-Id: Id971829c19c2535c975a68c44fb3697f60d0b4ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Disable display of FSP headerLee Leahy
Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16002 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Handle FspNotify callsLee Leahy
Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. Display the MTRRs before the first call to fsp_notify. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: FSP driver handles all FSP errorsLee Leahy
Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInitLee Leahy
Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15850 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add display HOB supportLee Leahy
Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into util.h * Move hob_type enum into util.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add UPD display supportLee Leahy
Add UPD display support: * Add a Kconfig value to enable UPD value display * Add a routine to display a UPD value * Add a call before MemoryInit to display the UPD parameters * Add a routine to display the architectural parameters for MemoryInit * Add a weak routine to display the other UPD parameters for MemoryInit * Add a call before SiliconInit to display the UPD parameters * Add a weak routine to display the UPD parameters for SiliconInit TEST=Build and run on Galileo Gen2. Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15847 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Monitor FSP setting of MTRRsLee Leahy
Display the MTRR values in the following locations: * Before the call to FspMemoryInit to document coreboot settings * After the call to FspMemoryInit * Before the call to FspSiliconInit * After the call to FspSiliconInit * After the call to FspNotify * Before the call to FspNotify added in patch 15855 TEST=Build and run on Galileo Gen2 Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15849 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-02google/lars & intel/kunimitsu: Disable EC buildMartin Roth
The Chrome EC codebase no longer supports the google/lars and intel/kunimitsu boards. Disable the build in those platforms. Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02superio/fintek/f81866d: Add support for UART 3/4Fabian Kunkel
Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since UART 1/3 and 2/4 share the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15564 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-02google/reef: Add pull up 20K for LPC SERIRQKane Chen
per hw team's check and info from EDS, this pin needs to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory verified the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a Reviewed-on: https://review.coreboot.org/15951 Tested-by: build bot (Jenkins) Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-02intel/amenia: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/15777 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02soc/intel/apollolake: Add iosstate macros for GPIOShankar, Vaibhav
IO Standby State (IOSSTATE): The I/O Standby State defines which state the pad should be parked in when the I/O is in a standby state. Iosstate set to 15 means IO-Standby is ignored for this pin (same as functional mode), So that pin keeps on functioning in S3/S0iX. Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/15776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02drivers/fsp2_0: Increment boot count for non-S3 bootFurquan Shaikh
If ELOG_BOOT_COUNT is enabled and the boot is not s3 resume, then increment boot count. BUG=chrome-os-partner:55473 Change-Id: Ib3e77180bd640ec0424978e73034d7c99cdcba95 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15948 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-02intel/apollolake: Enable upper CMOS bank in bootblockFurquan Shaikh
Upper CMOS bank is used to store the boot count. It is important to enable it as soon as possible in bootblock. BUG=chrome-os-partner:55473 Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15998 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-02elog: Include declarations for boot count functions unconditionallyFurquan Shaikh
There is no need to add guards around boot_count_* functions since the static definition of boot_count_read is anyways unused. BUG=chrome-os-partner:55473 Change-Id: I553277cdc09a8af420ecf7caefcb59bc3dcb28f1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15997 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-02drivers/intel/fsp2_0: Display FSP calls and statusLee Leahy
Disable the chatty FSP behavior for normal builds. Use a Kconfig value to enable the display of the FSP call entry points, the call parameters and the returned status for MemoryInit, SiliconInit and FspNotify. The debug code is placed into drivers/intel/fsp2_0/debug.c. TEST=Build and run on Galileo Gen2 Change-Id: Iacae66f72bc5b4ba1469f53fcce4669726234441 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02i2c/w83795: Fix chip type messagePatrick Georgi
(val & 4) == 1 is always false. Since val & 4 is either zero or non-zero, just drop the second test (for "== 1"). Validated against the data sheet that this is really the right register, bit and value. Change-Id: I627df9a9b4fddfff486689e405f52a3b54135eef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1241864 Reviewed-on: https://review.coreboot.org/16009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-02amd/amdfam10: eliminate dead codePatrick Georgi
if (gart) { foo = gart?a:b; } never evaluates to foo=b. Change-Id: Ibc7376687374065585b125a670dea5fe46bda97a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347365 Reviewed-on: https://review.coreboot.org/16008 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-02console: Drop leftover struct console_driverKyösti Mälkki
Change-Id: I4d529f6393937e5b97d8546f9348b44a448330e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/16007 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-02intel/skylake: Fix UART build optionsFurquan Shaikh
1. skylake does not support UART over I/O. So, NO_UART_ON_SUPERIO needs to be selected by default. 2. Move BOOTBLOCK_CONSOLE under UART_DEBUG. 3. Include bootblock/uart.c only if UART_DEBUG is selected. Change-Id: I4e996bea2a25b3b1dfb9625d97985a9d3473561b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16025 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-02intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & TianoPrabal Saha
Without this patch, eDP output is non-functional pre-graphics driver regardless of payload (SeaBIOS, Tianocore) or video init method (VBIOS, GOP driver) and once the standard Windows Intel HD graphics driver is loaded. Test: Boot Windows on peppy and auron_paine, install Intel HD Graphics driver, observe functional eDP output with full video acceleration. Debugging method: adjust location of call to run VBIOS within coreboot, observed that eDP output functional if the VBIOS is run before the power optimizer lines, broken if run afterwards. Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/15261 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-01soc/intel/quark: Enable use of hard resetLee Leahy
Select HAVE_HARD_RESET in the KCONFIG file to enable use of the hard_reset routine. TEST=Build and run on Galileo Gen2 Change-Id: Ib11a80b64cf1c55aec24f2576d197da9017b9751 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15992 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01soc/intel/common: Fix build error in reset.cLee Leahy
Fix build error caused by macro substitution in the function definition when the Kconfig value HAVE_HARD_RESET is not selected. src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0 void hard_reset(void) ^ src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token { ^ make: *** [build/bootblock/soc/intel/common/reset.o] Error 1 TEST=Build and run on Galileo Gen2 Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15988 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01arch/x86: Enable postcar consoleLee Leahy
Add a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-01arch/x86: Display MTRRs after MTRR update in postcarLee Leahy
Display the MTRRs after they have been updated during the postcar stage. TEST=Build and run on Galileo Gen2 Change-Id: I1532250cacd363c1eeaf72edc6cb9e9268a11375 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15991 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01siemens/sitemp_g1p1: Fix typoPatrick Georgi
Change-Id: I1c9af223d3598c4822905acce0cf9b1dca6ad1b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287066 Reviewed-on: https://review.coreboot.org/15981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-08-01soc/intel/common: Enable MTRR display during bootblock & postcarLee Leahy
Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15990 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01soc/intel/quark: Fix car_stage_entry routine name.Lee Leahy
Change routine name from car_state_entry to car_stage_entry. TEST=Build and run on Galileo Gen2 Change-Id: Ifd11db3fa711f2fe52ade1c6cde94f9be1f3a652 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15857 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetreeFabian Kunkel
This patch adds IO and IRQ information for UART 3/4 to the devicetree. Patch with Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e is needed. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: I1d8fa16950079a47775f48166486415bd5d24f42 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15621 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Add different DDR3 clk settingsFabian Kunkel
This patch adds two SPD files with different DDR3 clk settings. The user can choose which setting to use. Lower clk settings saves power under load. SoC Model GX-411GA supports only up to DDR3-1066 clk mode. Both SPD settings were tested with memtest for several hours. Power saving is around half a watt under heavy memory load. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Change PCIe linesFabian Kunkel
This patch binds PCIe lanes 2 and 3 to one PCIe device. PCIe device 2.4 becomes x2. Tested with the connected FPGA on PCIe 2.4. FPGA doubles transfer rate from/to the AMD. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15905 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31superio/nuvoton: Add Nuvoton NCT6791DOmar Pakker
This adds support for Nuvoton NCT6791D Super I/O chips. Makes use of the common Nuvoton early_serial.c. Based on the Datasheet supplied by Nuvoton. Datasheet Version: January 8th, 2016 Revision 1.11 Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40 Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15967 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-07-31src/vboot: Capitalize RAM and CPUElyes HAOUAS
Change-Id: Iff6b1b08b8159588b964d9637b16e1e0bfcca940 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/lib: Capitalize ROM, RAM, NVRAM and CPUElyes HAOUAS
Change-Id: Id0871b0c2eb31e2d728180b44cc5b518b751add4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15985 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/drivers: Capitalize CPU, RAM and ACPIElyes HAOUAS
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15983 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/acpi: Capitalize ACPI and SATAElyes HAOUAS
Change-Id: I7a4f1bd5c9e3c8152ebdd9118adddbc526d03a53 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15959 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>