summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2014-12-30ipq8064: make timer services availableMarc Jones
Make sure it is initialized at different stages. BUG=chrome-os-partner:27784 TEST=manual . not much at this point, just verified that it compiles Original-Change-Id: I343e7a6648e2ca935606cd76befd204aabd93726 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196592 (cherry picked from commit aedc41924313e5c21aef97b036f5a0643d59082d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4a90ae5ba6c9a561b7d5c938d18b6ea2b855855f Reviewed-on: http://review.coreboot.org/7981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30ipq/arm: Redesign hooks for bootblockVadim Bendebury
The following patches had to be squashed to properly build all the different ARM boards. ipq8064: storm: re-arrange bootblock initialization The recent addition of the storm bootblock initialization broke compilation of Exynos platforms. The SOC specific code needs to be kept in the respective source files, not in the common CPU code. As of now coreboot does not provide a separate SOC initialization API. In general it makes sense to invoke SOC initialization from the board initialization code, as the board knows what SOC it is running on. Presently all what's need initialization on 8064 is the timer. This patch adds the SOC initialization framework for 8064 and moves there the related code. BUG=chrome-os-partner:27784 TEST=manual . nyan_big, peach_pit, and storm targets build fine now. Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197835 (cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> arm: Redesign mainboard and SoC hooks for bootblock This patch makes some slight changes to the way bootblock_cpu_init() and bootblock_mainboard_init() are used on ARM. Experience has shown that nearly every board needs either one or both of these hooks, so having explicit Kconfigs for them has become unwieldy. Instead, this patch implements them as a weak symbol that can be overridden by mainboard/SoC code, as the more recent arm64_soc_init() is also doing. Since the whole concept of a single "CPU" on ARM systems has kinda died out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had already been done on Storm/ipq806x, which is now adjusted to directly use the generic hook.) Also add a proper license header to bootblock_common.h that was somehow missing. Leaving non-ARM32 architectures out for now, since they are still using the really old and weird x86 model of directly including a file. These architectures should also eventually be aligned with the cleaner ARM32 model as they mature. BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Storm and confirmed in the disassembly that bootblock_soc_init() is still compiled in and called right before the (now no-op) bootblock_mainboard_init(). Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231940 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57 Reviewed-on: http://review.coreboot.org/7879 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30baytrail: Add defines and functions for GPNCOREKein Yuan
BUG=chrome-os-partner:25159 BRANCH=firmware-rambi-5216.B TEST=Build pass for Rambi Original-Change-Id: I049f9254fe25aabf13d891579444bba2cfcf68c5 Original-Change-Id: Ib7c814660262e2507813ee5970190f98530dfe5e Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197984 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit dd05055f2f74fc0e4875733c0e5dedcbae302bfa) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iee01407a73bec420ab47d07524a3f1fd0f4d9817 Reviewed-on: http://review.coreboot.org/7892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30SPI: Add Eon EN25S64 support.Marc Jones
BUG=chrome-os-partner:25907 BRANCH=baytrail(rambi) TEST=Read and write MRC and ELOG on Glimmer with Eon device. Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d Original-Reviewed-on: https://chromium-review.googlesource.com/198324 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com> Original-Tested-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e Reviewed-on: http://review.coreboot.org/7935 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-30SPI: Fix Eon supportMarc Jones
The Eon SPI25 code had a number of issues: - fix page write calculation - fix erase segment - fix id check - fix sector size - make commands EN25 generic This makes the code similar to other SPI25 devices used in coreboot. BUG=chrome-os-partner:25907 BRANCH=baytrail(rambi) TEST=Read and write MRC and ELOG on Glimmer with Eon device. Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/198323 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com> Original-Tested-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8917e778cd62f3745189336d23c0c6118887d893 Reviewed-on: http://review.coreboot.org/7934 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30drivers/spi: Prepare Spansion driver for use in CBFS wrapperVadim Bendebury
Since the same driver is going to be used at all coreboot stages, it can not use malloc() anymore. Replace it with static allocation of the driver container structure. The read interface is changed to spi_flash_cmd_read_slow(), because of the problems with spi_flash_cmd_read_fast() implementation. In fact there is no performance difference in the way the two interface functions are implemented. BUG=chrome-os-partner:27784 TEST=manual . with all patches applied coreboot proceeds to attempting to load the payload. Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197931 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2 Reviewed-on: http://review.coreboot.org/7933 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30Provide a common CBFS wrapper for SPI storageVadim Bendebury
Coreboot has all necessary infrastructure to use the proper SPI flash interface in bootblock for CBFS. This patch creates a common CBFS wrapper which can be enabled on different platforms as required. COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the common CBFS interface and prevents default inclusion of all SPI chip drivers, only explicitly configured ones will be included when the new feature is enabled. Since the wrapper uses the same driver at all stages, enabling the new feature will also make it necessary to include the SPI chip drivers in bootblock and romstage images. init_default_cbfs_media() can now be common for different platforms, and as such is defined in the library. BUG=none TEST=manual . with this change and the rest of the patches coreboot on AP148 comes up all the way to attempting to boot the payload (reading earlier stages from the SPI flash along the way). Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197800 Original-Tested-by: Vadim Bendebury <vbendeb@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41 Reviewed-on: http://review.coreboot.org/7932 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30drivers/spi: add support for another Spansion chipVadim Bendebury
Add the device ID definitions and properties for the SPI chip used on the AP148 board (Google Storm). BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to read the payload. Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197895 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b Reviewed-on: http://review.coreboot.org/7931 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30rtc: Add an RTC API, and implement it for x86.Marc Jones
This CL adds an API for RTC drivers, and implements its two functions, rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the CMOS as lost state now uses the RTC driver instead of accessing the those registers directly. BUG=None TEST=Built and booted on Link with the event log code modified to use the RTC interface. Verified that the event times were accurate. BRANCH=nyan Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197795 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> This is the first half of the patch. (cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883 Reviewed-on: http://review.coreboot.org/7889 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30cbmem: use a single id to name mapping tableVadim Bendebury
CBMEM IDs are converted to symbolic names by both target and host code. Keep the conversion table in one place to avoid getting out of sync. BUG=none TEST=manual . the new firmware still displays proper CBMEM table entry descriptions: coreboot table: 276 bytes. CBMEM ROOT 0. 5ffff000 00001000 COREBOOT 1. 5fffd000 00002000 . running make in util/cbmem still succeeds Original-Change-Id: I0bd9d288f9e6432b531cea2ae011a6935a228c7a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199791 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5217446a536bb1ba874e162c6e2e16643caa592a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d839316e9697bd3afa0b60490a840d39902dfb3 Reviewed-on: http://review.coreboot.org/7938 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-30CBMEM: Always build for x86 romstageKyösti Mälkki
Always build CBMEM for romstage, even for boards that will not use it. We further restrict car_migrate_variables() runs to non-ROMCC boards without BROKEN_CAR_MIGRATE. This fixes regression of commit 71b21455 that broke CBMEM console support for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME. Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7877 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30Intel FSP: Fix GPI status outputKyösti Mälkki
Propagate commit 07c3fc089 to Intel FSP. Change-Id: Ie3e05df7fc06cb0ed6142edfedafab0cde74a68c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7966 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-30mainboard/lenovo/t530/Kconfig: No Super I/O on this boardEdward O'Callaghan
Disable Super I/O related topics showing in menuconfig. Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7985 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-29edid: fill reserved bits fields in cb_framebufferPatrick Georgi
If it's a 4 byte format (as per documentation), there are some reserved bits, so let's mark them as such... Unfortunately undone while upstreaming changes. Change-Id: I50f12cfff2c9bb9d082a5f3c3ac54c0d514d862c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Originally-Reviewed-on: http://review.coreboot.org/7674 Reviewed-on: http://review.coreboot.org/7964 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-29Revert "src/Kconfig: Don't treat warns as errors on Clang builds yet"Edward O'Callaghan
This reverts commit 9b63c9bde2fc3b3a2d42e68618e043cf282bc566. Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Change-Id: I4f547d20c5096877b2010602a087e41702939f77 Reviewed-on: http://review.coreboot.org/7506 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-29northbridge/amd/pi/northbridge.c: Remove superfluous logic operandAlexandru Gagniuc
The "((1ull << (sizeof(modules) * 8)) - 1)" statement evaluates to 0xffffffff, but there's no need to AND with that value, as 'modules' is already 32-bit. The '&&' is most likely a typo, which meant bitwise and, as indicated by the structure of thus operation. Remove this superfluous statement. This also fixes a clang warning. Change-Id: Ie55bd9f8b0ec5fd41e440f56dcedd40c830bf826 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7965 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-28intel baytrail broadwell: Include microcode updatesKyösti Mälkki
Commit 66e0c4c renamed the variable. Change-Id: I9e8dc3e7f140411d04b35a21ada76aaa578832fb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7960 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-28intel: Fix microcode alignmentKyösti Mälkki
CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS. Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only used with PLATFORM_FSP. CPU_MICROCODE_CBFS_LEN was no longer used at all. Change-Id: I0454397924d2526d97b1f095cc371ba962873c99 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7957 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-28RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMsKyösti Mälkki
After relocation the weak symbol map_oprom_vendev is no longer NULL. Always have empty stub function defined. Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7956 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-28RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPIKyösti Mälkki
After relocation the weak symbols are no longer NULL. Always have empty stub function defined. Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7955 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-28RELOCATABLE_RAMSTAGE: Fix weak symbols with ramstage_cacheKyösti Mälkki
We had NULL reference with cache_loaded_ramstage() if CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM was not set so boot never proceeded to ramstage. Cache implementation outside CBMEM provides means for platform-specific location so there is no need of weak attributes here. Change-Id: I1eb1a713896395c424fde23252c374f9065fe74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7954 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-27samsung/exynos*/Makefile.inc: Simplify unnecessary ifeqEdward O'Callaghan
It's not needed, as we can use a simpler macro instead. Change-Id: Ib96f5cfa434d0383ee3bfe49995a8f8830987f20 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7925 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-26blaze: change ramcode 0001/0010 to use 792MHz bctJerry Wang
This change updates the cfg file for Micron/Samsung 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad Original-Signed-off-by: Jerry Wang <jerryw@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/199296 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7 Reviewed-on: http://review.coreboot.org/7902 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26nyan*: Detect watchdog resets and reset the whole machine.Gabe Black
When a watchdog reset happens, the SOC will reset but other parts of the system might not. That puts the machine in a funny state and may prevent it from booting properly. BUG=chrome-os-partner:28559 TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/198582 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7900 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-26tegra124: Add a utility function to read the cause of the most recent reset.Gabe Black
When a watchdog reset happens, the SOC will reset but other parts of the system might not. In order to detect those situations we can check the rst_status register in the PMC. BUG=chrome-os-partner:28559 TEST=With this and a change which uses the new function in the nyan boards, built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/198581 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72 Reviewed-on: http://review.coreboot.org/7899 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-26blaze: change ramcode 0000 to use 792MHz bctKen Chang
The original sdram-hynix-2GB-792.inc was just copied from nyan bct file. This change updates the cfg file for Hynix 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I9534b4df6d35193179de124309df12ed830098a0 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197660 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 797dabe54f2679bb5717961dda1947df453eb0f1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie67bedb29d5d9c3a3b58d949ddf9600716c385ec Reviewed-on: http://review.coreboot.org/7898 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26nyan*: I2C: Implement bus clear when 'ARB_LOST' error occursTom Warren
This is a fix for the 'Lost arb' we're seeing on Nyan* during reboot stress testing. It occurs when we are slamming the default PMIC registers with pmic_write_reg(). Currently, I've only captured this a few times, and the bus clear seemed to work, as the PMIC writes continued (where they'd hang the system before bus clear) for a couple of regs, then it hangs hard, no messages, no 2nd lost arb, etc. So I've added code to the PMIC write function that will reset the SoC if any I2C error occurs. That seems to recover OK, i.e. on the next reboot the PMIC writes all go thru, boot is OK, kernel loads, etc. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197732 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc Reviewed-on: http://review.coreboot.org/7897 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26soc/samsung/exynos5250/clk.h: Trivial, fix spelling in commentsEdward O'Callaghan
Change-Id: Iaacd4d7977ddeff4204acdc32d4d13fd88b6660b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7928 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26soc/samsung/exynos5250/clock.c: Trivial whitespace fixesEdward O'Callaghan
Reduce difference with exynos5420/clock.c by fixing some whitespace and an include directive. Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7926 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26soc/samsung/exynos: Sync 'power.c' between chip variantsEdward O'Callaghan
Change-Id: I06d83be840b49ee7523b34e1dba5ec038256b3f4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7918 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-25soc/samsung/exynos: Make 'ps_hold_setup()' staticEdward O'Callaghan
Change-Id: I272fea9c2767c341e8a545bf7a9ac18eefa2bda5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-23TPM: Fix i2c driver dependencyKyösti Mälkki
Change-Id: I59545ef734dff41ba55dcddd541c54b17b0855bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7914 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-22hp/pavilion_m6_1035dx: Enable IOMMUAlexandru Gagniuc
Change-Id: Ia14490c9074d35b7dde99e38b4ee169d4e4589a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7678 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-22amd/agesa/f15/Proc/Common/S3SaveState.c: Sync with f15tnEdward O'Callaghan
Change-Id: If46079c1affc7d74767c4215467fd6754b24f20c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7576 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-22lib/edid.c: Fix mismatch between format string and variable typeAlexandru Gagniuc
Use 'd' instead of 'hhd' when printing absolute year of manufacture. This is the correct type in this case, as the result is autoatically promoted to int. Change-Id: Ice4155bb1a04f206ae55c45c260089d6971b77d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7885 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Use common agesawrapperKyösti Mälkki
Callout FCH_OEM_CONFIG is made during AMD_INIT_RESET, so it was required to provide GetBiosCallOut here too. Change-Id: I0eab858677d14536293385ca37daab3e538132e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7826 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam15tn fam15rl fam16kb: Add OemInitMid()Kyösti Mälkki
Change-Id: Icbad42168ec3afb7780c0c2ddc17aa405e08d693 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7825 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add OemCustomize hooks structureKyösti Mälkki
We should potentially provide an OEM platform hook to manipulate parameters around any entry point to AGESA. Use structure for such ops to avoid weak functions and lots of empty function stubs. Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7824 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Ignore error in OemCustomizeInitEarly()Kyösti Mälkki
It does not really matter if we continue or return after a failed assertion, system configuration is invalid anyway. Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam15: Unify agesawrapperKyösti Mälkki
Disable TSC output for now. Change-Id: I078b4f0170aaf0ada58e464cf609c234204f8196 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7822 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Common laterunaptask()Kyösti Mälkki
Change-Id: I580f975aa987a333074de3d63744ad5f9008377d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7821 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Common agesawrapper_amdinitlate()Kyösti Mälkki
Change-Id: I3d532989559ffd7fd0f63e15c2c60bcfe5ec9101 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam15: Ignore AmdCreateStruct() errorsKyösti Mälkki
Change-Id: I1b7c95e08d74784e0f144cd5836d46bda64a3596 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7819 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Use memset() on agesawrappersKyösti Mälkki
Change-Id: Icc8da62c6d1644e16f7db6c634796ad597c755c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7818 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam12 fam14: Use lowercase void in agesawrappersKyösti Mälkki
Change-Id: I1755796049c2c3f2090cd6a4b4e28a71b807c7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7817 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam14: Add amd_initenv()Kyösti Mälkki
Not part of wrapper to AGESA, but workaround for enable_resources(). Also remove remains of comments in non-fam14 wrappers. Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7816 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add amd_initcpuio() and amd_initmmio()Kyösti Mälkki
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20amd/torpedo: Drop unused code in agesawrapperKyösti Mälkki
Change-Id: I4c7fdfb64689cc8ba7e00bd7966d5c5857baf7c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7814 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam14: Increase MMCONF regionKyösti Mälkki
Increase to max 64 buses, as there are no benefits of limit 16. NOTE: It appears there is no matching (early) programming of the region to non-posted MMIO. Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7813 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam12: Fix MMCONF regionKyösti Mälkki
MMIO for non-posted region used hard-coded setting for 64 buses while MSR programming was for 256 buses. Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7812 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19qemu-armv7: Trivial style fixesDavid Hendricks
Minor style fixes to avoid future bikeshedding. - Opening brace for functions go on their own lines. - use fixed-length types where appropriate. BUG=none BRANCH=none TEST=it compiles Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: If9855d32c8ed1f5977937806c8c4cce65dd7d450 Original-Reviewed-on: https://chromium-review.googlesource.com/196955 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit e2bfeed18636af6b532e2e8f118de22a658fe41b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/mainboard/emulation/qemu-armv7/uart.c Change-Id: I8e09db53534802262168e65ec4cd47b96386490a Reviewed-on: http://review.coreboot.org/7867 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19nyan*: Clear VDDIO_SDMMC3 to reset SD card reader.Hung-Te Lin
When across warm reset, if VDD_3V3_SD_CARD gets power-cycled but VDDIO_SDMMC3 does not, we will get ~1.5V leakage on VDD. To fix that, we reset VDDIO_SDMMC3 to 0 along with VDD_3V3_SD_CARD in Coreboot. Payloads must turn on VDDIO_SDMMC3 explicitly before accessing SD card. Note the warnings of "VDD_SDMMC must set early" in comment seems only happens on U-Boot and can be removed. BUG=chrome-os-partner:27053 BRNACH=nyan TEST=Ctrl-U to boot from SD card, login and type "reboot", then Ctrl-U to boot again. Without this patch, system will fail in loading kernel. Original-Change-Id: I7f85995317d18587d514ea3afcff3bfea0a33e93 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196961 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 2cfdb78d9dc229a3c06f19bbe137d59d923908a4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie7d814e0424478c35a56fbc959437ee6a555684a Reviewed-on: http://review.coreboot.org/7866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19nyan*: Disable SD card reader power gpio.Hung-Te Lin
When warm booting, SD card reader on Tegra 124 needs to be reset by setting power GPIO to zero. Since we don't really access SD card in Coreboot, set it to zero and let payloads enable power when they need to access SD cards. CQ-DEPEND=CL:196783 BRANCH=nyan BUG=chrome-os-partner:27053 TEST=emerge-nyan coreboot depthcharge chromeos-bootimage # With related changes in depthcharge, boots SD card successfully. Original-Change-Id: I2d368eb9480c978e9e343648b58a729028c94622 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196774 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 62bb7d04dff1a87474a8557f144b24e6b7d006ae) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3429535d0d032f9db89d8e70a525a6281102537a Reviewed-on: http://review.coreboot.org/7865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19nyan*: Add fast link training functionsJimmy Zhang
Some panels (including those on Big DVT) cannot work fine without link training before sending the video signals, especially multi-lane Full HD panels. We need to use the fast link training functions from kernel to support them. BRANCH=Nyan BUG=chrome-os-partner:28128, chrome-os-partner:28129 TEST=tested on nyan, nyan_big dvt. Vince verified on Full HD panels. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4 Original-Reviewed-on: https://chromium-review.googlesource.com/196162 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1 Reviewed-on: http://review.coreboot.org/7864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19AGESA: Remove redundant redeclarationKyösti Mälkki
Change-Id: I9172769c314850b384abbddf0200d5833e2a8b26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19AGESA: Only fam14 sets Ontario APU IDsKyösti Mälkki
Change-Id: I3d249a1234599e3820e4ad9b852bbb03a89dd49a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19cpu/armltd/cortex-a9: Remove stub func dead codeEdward O'Callaghan
Change-Id: Ia8246e2bdf346883072a924d8808f14f48d44bb3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-19intel/i945: Use define for `BSM`Paul Menzel
Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5929 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-19intel/truxton: Add dummy cache-as-ram regionKyösti Mälkki
Board has no chance of working without a cache_as_ram.inc, but without a specified CAR region we also break builds. Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19gigabyte/ga-b75m-d3h: Drop redundant EARLY_CBMEM_INITKyösti Mälkki
It is implied by DYNAMIC_CBMEM. Change-Id: I6859c4950ce568fb76c7604e9e994031a3d94d78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19beaglebone: use new arm bootblock infrastructureAlexander Couzens
8b685398 change config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: Ifac4a18a2e380c3472f51aaa7cc7842b01a2553e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7190 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19arm/ti/am335x: use new arm bootblock infrastructureAlexander Couzens
commit 8b685398 (ARM: Overhaul the ARM Makefile.) changes config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: I70cbe3abad8443c5dc71c8ba76a35973a5284477 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7189 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19AMD amdfam10: Drop EXT_CONF_SUPPORTKyösti Mälkki
Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690. Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7809 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AGESA fam12 fam14: Drop EXT_CONF_SUPPORTKyösti Mälkki
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped from other AGESA families. Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AMD binaryPI: Drop EXT_CONF_SUPPORTKyösti Mälkki
Change-Id: I2ec08df2eb8e65bc759de9917894df9d0c8b1995 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19spd_cache debug: Log invalid CRC checksumTobias Diedrich
"SPD has a invalid or zero-valued CRC" is not a very useful message, so show the actual and expected values. Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7393 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-19mainboard: Strip out some dead includesEdward O'Callaghan
Change-Id: I0079fa089ba863c6e447bcee3440a7e0ba0f2372 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7429 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-12-19AMD 00730F01: Change Makefile to use BLOB sizes for packingBruce Griffith
The new AMD PSP and SMU BLOBs currently have fixed sizes in the southbridge Makefile. Future PSP and SMU updates may require more space and thereby cause the make to fail with cryptic error messages. Change the makefile to compute CBFS locations and the corresponding PSP pointer table entry values based on the actual file sizes. Additionally, the FWM directory has expanded to 4096 bytes. The Avalon makefile is modified to zero-pad the FWM directory using the "dd" system command. There is dead code in the makefile to allow hardware validated boot ROMs, but the option is hard-coded to be disabled. Remove the HVB dead code. Change-Id: I4705cede8ed001a71bb4f49598444255c9609d52 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7726 Reviewed-by: Marshall Dawson <marshall.dawson@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19southbridge/amd/cimx/sbX00/early.c: Update grammar in commentsMartin Roth
Along with the spelling fixes, it was requested that I correct this comment. Updating "LocateImage() take minutes" to "LocateImage() takes minutes" everywhere that comment occurs. Change-Id: I28cd47476cb42ba3e404e064695a7fd97d581834 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7848 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Initialize LPC pads in bootblock for port 80Martin Roth
Port 80h codes were coming out of bootblock and romstage scrambled, or were not coming out at all. Initializing the LPC signal pads as LPC fixes that issue. Change-Id: I16943513f2eb6fe8fa58766aaa82dac182440c34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7802 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
The GPIO_OUT_LOW #define was missing an internal comma in both soc/intel/baytrail and soc/intel/fsp_baytrail. Thanks to Werner Zeh for pointing this out. Change-Id: I2e5507058739e5fdc2c0e43e0380058458870e46 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7801 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-18amd/olivehillplus/romstage.c: remove not useful variable 'halt'WANG Siyuan
The variable 'halt' is not useful and results in a compile error because of: 1b2f2a07 Introduce halt() build error: src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main': src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow] In file included from src/include/cpu/x86/lapic.h:6:0, from src/mainboard/amd/olivehillplus/romstage.c:29: src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow] cc1: all warnings being treated as errors make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1 Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/7847 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
This one is special because qemu is really far from anything real but shares some common features. Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6939 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-18Drop VIA Epia-NStefan Reinauer
ROMCC cleanup. Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7855 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia-M series of boardsStefan Reinauer
ROMCC cleanups Change-Id: Ic4c9d9eb8c7edc506c8a8e8eeeacf759cbaead74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7854 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia mainboardStefan Reinauer
.. and also drop the northbridge and southbridge used by the board. This is one of the last boards to not use ROMCC for romstage. Let's get rid of it. Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7853 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop Intel E7520 and E7525 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18intel/truxton: Un-romcc-ify boardStefan Reinauer
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7852 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-18AMD Trinity: Update SMU firmware from 10.9 to 10.14Zheng Bao
The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e. The FirmwareTNHeader is not called by any one in latest PI. It seems to be useless for now. Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-12-17chromeos: Add empty functions when CONFIG_CHROMEOS is disabledDuncan Laurie
This allows the chromeos header and functions to be included without needing to guard with #if CONFIG_CHROMEOS. BUG=chrome-os-partner:28234 BRANCH=None TEST=emerge-rambi coreboot Original-Change-Id: I523813dc9521d533242ae2d2bc822eb8b0ffa5e2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196265 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b78ccada9a01f54a60993dfc2c618201d31df9ad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic2f7127966da716e114336c30829a6403d82e180 Reviewed-on: http://review.coreboot.org/7843 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Fix chromium merge issueMarc Jones
This cleans up a mis-merge in elog.c and puts the following change back: drivers/elog: Unmangle header include out of pre-proc cond commit a3119e5835e4b8fd510d046c56a3bf2bf43a5c0d Change-Id: Iafbbd381efdb103717022d2a3c342da376a9428f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
In order to protect ourselves from the kernel driver not honoring or placing the correct frequency in the backlight register always set one. This code path picks 200Hz as the default if nothing is specified in device tree. It's somewhat arbitrary but that frequency is valid for all the eDP panel specs we've seen being used on baytrail devices. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted in normal mode. Noted register write stuck. Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196821 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Reviewed-on: http://review.coreboot.org/7845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17rambi: align gpu pipea settings with the VBIOSAaron Durbin
In the normal mode case these settings aren't overwritten by the VBIOS because the VBIOS does not run. Therefore, the settings need to align with what the VBIOS programs so that there is a consistent panel power sequencing. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted. Noted settings set by firmware for both dev and normal mode match. Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196822 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf Reviewed-on: http://review.coreboot.org/7846 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
This ensures that SPI is ready when eventlog code is used. x86 platforms which use eventlog invoke elog_clear() in GSMI and elog_add_event_raw() when deciding the boot path based on ME status. For the SMM case spi_init() is called during the finalize stage in SMM setup. For the boot path case we can call spi_init() at the beginning of BS_DEV_INIT and it will be ready to use when the boot path is determined from the ME status. BUG=none BRANCH=none TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi (Baytrail) with follow-up patch Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1 Original-Reviewed-on: https://chromium-review.googlesource.com/194525 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad Reviewed-on: http://review.coreboot.org/7756 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-17chromeos: vboot_loader: Add support for SW_WP_ENABLED flagShawn Nematbakhsh
Set VB_INIT_FLAG_SW_WP_ENABLED according to the status returned by an optional platform / mainboard function vboot_get_sw_write_protect(). BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` and reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: Ifb852d75cc106d10120cfee0a396b0662282051a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c4668fc8a9ab31d9cf876b3d9ad3405756d4d683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idace325439958f6b490d2e6705d55e95305c4b2a Reviewed-on: http://review.coreboot.org/7750 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: cbmem: Move the call to cbmemc_reinit.Gabe Black
The call was after the call to vboot_verify_firmware and so would only be called when falling back to RO, aka recovery mode. This change moves it to before vboot_verify_firmware so we'll always have the cbmem console. BUG=None TEST=Built and booted on nyan and verified that the cbmem console was the same as the serial output. Built for big and blaze. BRANCH=nyan Original-Change-Id: I02d01110659689b08d32777dae384ac3e01b3b9f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196158 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d3e4a778e4a0f5ade7d633d8ce7e72ef06c44086) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id14a19a78bcb21cb0c4030c2e41195e491f690d5 Reviewed-on: http://review.coreboot.org/7777 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17tegra124: modify panel init sequenceKen Chang
Panel datasheet defines some delay between PWM signal out and backlight enable. This change fixes the current sequence and makes the delays adjustable by dt setting. BRANCH=none BUG=chrome-os-partner:28008 TEST=Verified on Big DVT and Nyan/Norrin panels. Panel works fine with dev mode, and the measurement of power on sequence meets panel requirements. Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196183 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3 Reviewed-on: http://review.coreboot.org/7776 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: enable CLAMP_INPUTSKen Chang
Enable pinmux clamp function to avoid pinmux conflict. For pins which are configured to tristate enabled, the inputs to the controller will be clamped to zero. This can be used to avoid pinmux conflicts since the tristate bit is set to 1 in the power-on-reset pinmux setting. With pinmux clamp enabled, we need to configure all the input pins to tristate disabled. BUG=chrome-os-partner:27091 BRANCH=None TEST=built and booted successfully, display worked fine. Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194060 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0 Reviewed-on: http://review.coreboot.org/7775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: Add eventlog supportDavid Hendricks
This enables event logging support for Nyan platforms. Right now this doesn't do a whole lot. We can add events in later CLs. BUG=none BRANCH=none TEST=built and booted for Nyan Rev. 1, eventlog gets initialized if necessary and can be printed by "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1 Original-Reviewed-on: https://chromium-review.googlesource.com/191200 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1bb1a00863a63e53379b02f2b466d4d8ae3cef50) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3a5d896d97dfc66ec37114bd3bac3f34e1c22bf7 Reviewed-on: http://review.coreboot.org/7774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-17Revert "elog: Use the RTC driver interface instead of reading CMOS directly."Marc Jones
This reverts commit 474313d1b6556ad8b3e6750a4096b5735cbfc846. This reverted commit was applied out of sequence and there are a number of dependencies that need to be in place prior to adding it. Remove it for now. Change-Id: If80c40867098dee2feff2b9a1d824558f4d7028d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17lib/edid.c: Use 'hh' instead of 'h' length modifier in printkAlexandru Gagniuc
The length modifiers for unsigned char were accidentally changed from 'hh' to 'h' with commit: * 1c8ee21 edid: Change static variables to auto variables. Change-Id: I4b3e63cbcde7635b842894f776373f7946bd0df8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4477 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-17intel/minnowmax: Determine board type from GPIOsMartin Roth
SSUS GPIO 5 reflects the Minnowboard Max SKU: --- GPIO 5 low is a 1GB board --- GPIO 5 high is a 2GB (or 4GB in the future) board. This allows us to determine the board type at runtime and configure the FSP appropriately. Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7797 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-17fsp_baytrail: Add code to read GPIOs in romstageMartin Roth
- Build gpio.c into romstage - Add functions to translate the GPIO # to a pad #, then return the value read from the GPIO. - Add functions to configure the GPIO - Function, Pull up/down, pull strength, Input/Output, and Output level. Change-Id: Ic37dfc9a74a598023bdf797d31087428adec176a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7796 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-17southbridge/amd rs690 & rs780 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7841 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/amd agesa & cimx spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7839 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/amd amd81XX, cs553X & sr5650 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7842 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-17southbridge/amd sb600, sb700 & sb900 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I31333742d9c90cf6d7ae3d2f324880ed53807d7f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7840 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/nvidia: Spelling/comment fixMartin Roth
Change-Id: I4f9b2b8375abe4691f279df649eaf822b87509e5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7731 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 18:25:38 +0000