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2023-08-09mb/facebook/fbg1701: Add config to additional listFrans Hendriks
´config´ is removed from measure list (CB:74750) Add 'config' to ram_stage_additional_list[] to have it measured and verified. BUG=NA TEST=boot and verify coreboot logs on facebook FBG1701 Change-Id: Id4119bc3a01e11f14a091facf81964d1a71092c1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08vendorcode/cavium: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I19c029968584fedbb6749e66c7ea2f74a7d580f4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian
On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01vendorcode/google: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-21vendorcode/amd/fsp/common: Refactor dmi_info.hKonrad Adamczyk
SoC family is able to provide SoC-specific information via amd/fsp/<soc_family>/soc_dmi_info.h. Use common amd/fsp/common/dmi_info.h for all AMD platforms. This way, duplicated dmi_info.h files in vendorcode/amd/fsp/<soc_family>/ can be removed. BUG=b:288520486 TEST=Dump `dmidecode -t 17`. Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76107 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14vc/amd/fsp/phoenix/FspmUpd: drop eMMC-related UPDsFelix Held
Phoenix doesn't have an eMMC controller and those UPDs were carried over from Picasso. The SoC's fsp_m_params.c didn't write to any of those fields, so this doesn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie3640c1493a92c1effba3ce42103d022bd8399ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/76450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14vc/amd/fsp/glinda/platform_descriptors: add dxio_port_param_type TODOFelix Held
The dxio_port_param_type enum was copied over from Cezanne, but the enum on the AGESA/FSP side changed between the generations. Add a TODO as a reminder that this needs to be updated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8063ab00a508b045265bab73197c8ca117622800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76448 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14vc/amd/fsp/*/platform_descriptor: add dxio_link_hotplug_type enumFelix Held
Add the dxio_link_hotplug_type enum definition for the link_hotplug field in the DXIO descriptor struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieeb3e3edaed2c689707edc4df7d25c777005fde2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-14vc/amd/fsp/phoenix/platform_descriptors: fix dxio_port_param_type enumFelix Held
The dxio_port_param_type enum was copied over from Cezanne to Mendocino to Phoenix, but the enum on the AGESA/FSP side changed between the generations. Update the definition to match the definition used in the Phoenix FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c87fdc8bf0849d797c2af74c1d1495c7d85019f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76447 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14vc/amd/fsp/mendocino/platform_descriptors: fix dxio_port_param_type enumFelix Held
The dxio_port_param_type enum was copied over from Cezanne to Mendocino, but the enum on the AGESA/FSP side changed between the two generations. Update the definition to match the definition used in the Mendocino FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c4d7e4e3eaf7af9a43007363135412633c7440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76446 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14vc/amd/fsp/*/platform_descriptor: drop SoC name from DDI commentFelix Held
The file for Mendocino and Phoenix still used Cezanne in the comment and from the file it's already clear to which SoC generation this belongs, so just drop the SoC name from the comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I73e8b01e46904578226bb64e5e4659016c491880 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76440 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14vc/intel/fsp/mtl: Update the MemInfoHob header to FSP version 3251.81Subrata Banik
This patch updates the MemInfoHob header file as per Meteor Lake version 3251.81. Changes include: 1. Drop DimmDFE structure variable 2. Drop unused macro MAX_COPY_DIMM_DFE_TAPS BUG=b:290898626 TEST=Able to build and boot google/rex. w/o this patch: cbmem -c -1 | grep DIMM [ERROR] No DIMMs found w/ this patch: cbmem -c -1 | grep DIMM [DEBUG]  8 DIMMs found Change-Id: I8eed410831399bb4835244f48c14d5ed9e701e68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76433 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14vc/amd/phoenix/platform_descriptor: clarify link_compliance_mode commentFelix Held
When set to 1, the link_compliance_mode element of the DXIO port descriptor will cause the corresponding PCIe port to not be trained but to output a compliance testing pattern instead. Update the comment to point out that this is only a testing mode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-13vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00Bora Guvendik
The headers added are generated as per FSP v4221.00 BUG=b:290038558 TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76147 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-06vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75916 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-23Makefile.inc: don't add fmap_config.h dependency twiceFelix Held
Commit d054bbd4f1ba ("Makefile.inc: fix multiple jobs build issue") added a dependency on $(obj)/fmap_config.h to all .c source files in all stages, so it's not needed any more to add it as a dependency to files that include fmap_config.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-22vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mappingFelix Held
For Phoenix the lane numbers in the DXIO descriptor match the ones in the schematic, so remove the corresponding text and the table from the comment on the fsp_dxio_descriptor struct. Since there's no logical to physical lane number remapping needed for the lanes in the Phoenix DXIO descriptors, drop the 'logical' from the start_logical_lane and end_logical_lane fields in the DXIO descriptor and rename those to start_lane and end_lane. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-17vc/intel/edk2: Remove edk2-stable202111 supportRonak Kanabar
This patch removes the support for edk2-stable202111 as MTL has migrated to edk2-stable202302, and no other platform is utilizing edk2-stable202111. The support for edk2-stable202111 is no longer necessary. Change-Id: Ide1864e0a42a4c0a81c3c94b1b1254f8fad062af Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75817 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16vendorcode/intel: Add edk2-stable202302 supportRonak Kanabar
edk2-stable202111 is older release of edk2. MTL FSP uses 202302 Edk2. There are structure definition changes between 202111 and 202302. One of change is in FSP_INFO_HEADER structure. Also, Next Gen Intel SoC needs 202302 Edk2. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202302 https://github.com/tianocore/edk2.git commit hash: f80f052277c88a67c55e107b550f504eeea947d3 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add UefiCpuPkg/Include Because `MpServices2.h` file is part of `UefiCpuPkg/Include/Ppi/` Add following fixes from edk2-stable202111 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements BUG=b:261689642 TEST= select UDK_202302_BINDING Kconfig for MTL, Test Build and boot rex Image Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-06-14soc|vc/amd/phoenix: Prepare for PSP verstageKarthikeyan Ramasubramanian
Update all the required sources to lay the ground work to enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-14vc/intel/fsp/fsp20/meteorlake: Add VR config entriesSubrata Banik
This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-06-04vc/intel/fsp2: Drop Intel Quark FSP headersFelix Singer
Intel Quark was dropped in commit 531023285e. Thus, drop the remaining FSP headers. Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-04vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3194_81, previous version being 3165_81. FSPM: 1. Add 'PchPcieRpEnableMask' UPD 2. Address offset changes Add "FspProducerDataHeader.h" file to support MRC version Info BUG=b:284803304 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25vc/intel/fsp/fsp20/meteorlake: Add `SaGvWpMask`Subrata Banik
This patch adds `SaGvWpMask` UPD into the FSP header. This information is required to set the SaGv work endpoint. BUG=b:283746904 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If39da58c927cc7b28b46063576f8e246ef9596d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75361 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-24vc/amd/pi/amdlib.c: Use native coreboot code over compiler builtinsArthur Heymans
Compiler builtins depend on certain CPU features flags to be passed to the compiler. This may have unwanted side effects as generating code with FPU registers. Instead use native coreboot code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e92d103fa3a6c7a56e813a583b3262676969669 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-23src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header filesSrinidhi N Kaushik
This change updates Intel Copyright License for all header files under Sapphirerapids dir Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-18vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoCFelix Held
Phoenix has one more Type C port and two more USB2 ports which are used as the legacy USB part of the two USB4 ports. The USB struct version numbers have also changed, since it's a newer and incompatible version of that struct. TEST=After changing FSP to not hard-code the USB PHY config, but use the configuration provided by coreboot, and applying this patch, the USB connector on the USB2 port 4 lines works. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If52934595dd612154b97e7b90dbd96243146017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5738e73f2121e2558831fbaa9c92a2fd0926ad88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: More sure ucDoneFlg is initializedArthur Heymans
One some codepaths ucDoneFlg is not initialized. This fixes a clang warning. Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Make order of operators more explicitArthur Heymans
Clang warns about this. Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix superfluous bracketsArthur Heymans
Clang warns about this. Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix casting enum of different typesArthur Heymans
Clang warns about this. Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans
The clang compiler warns about this. Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/cavium: Fix additions to stringArthur Heymans
The clang compiler is confused about adding integers to strings. Adding brackets around the macros fixes this. TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I2ea17322352d977bf0ec3ee71b14463fa218d07c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74541 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans
TEST: BUILD_TIMELESS=1 binary remains the same. Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans
The binary does change on these with BUILD_TIMELESS. Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12vendorcode/cavium: Fix set but unused variablesArthur Heymans
TEST: BUILD_TIMELESS=1 remains the same. Change-Id: Id2cb37dbe4d450fe7f91a527b5cd73ac55863548 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74542 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-11vc/intel/fsp/mtl: Update header files from 3084_85 to 3165_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3165_81, previous version being 3084_85. FSPM: 1. Change UPD name from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' 2. Change UPD name from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' 3. Change UPD name from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage' 4. Address offset changes FSPS: 1. Remove deprecated UPD 'PcieDpc' 2. Address offset changes BUG=b:280005256 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-05vc/google: Decouple DSM_CALIB from CHROMEOSMatt DeVillier
DSM (Dynamic Speaker Management) uses calibration parameters stored in a VPD (Vital Product Data) FMAP region to configure the audio output via an ACPI _DSD table. This has no dependency on a ChromeOS, and can be used by Linux/Windows drivers if appropriately configured. Remove the dependency of DSM_CALIB (and the calibration file) on CHROMEOS and replace it with VPD, so that non-CHROMEOS builds can utilize this feature as well. Move files from underneath vc/google/chromeos to underscore the point. TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton parameters present in _DSD table. Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-01vendorcode/mediatek/mt8192: Cast enum typesArthur Heymans
Clang warns about using the wrong enum types as arguments. Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74546 Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-04-27vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vauleChris Wang
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-24vendorcode/mediatek/mt8192: Add or remove bracketsArthur Heymans
This fixes clang compilation warnings about logic problems and superfluous brackets. Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS caseFelix Held
When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be selected. This causes vc/google/chromeec/acpi/chromeos.asl to be included in the DSDT and chromeos_acpi_gpio_generate to be called when generating the coreboot SSDT. When a mainboard also uses DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0 and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only checked if the GPIO table was non-NULL, which caused the function to exit early and not generate the OIPG package which causes the kernel to complain about referencing the non-existing OIPG package. To avoid this, only exit in the GPIO table pointer being NULL case if the number of GPIOs is non-0. TEST=Error about missing OIPG ACPI object in dmesg disappears on birman. Before: [ 0.241339] chromeos_acpi: registering CHSW 0 [ 0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330) [ 0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531) [ 0.241933] chromeos_acpi: failed to retrieve GPIO (5) [ 0.242011] chromeos_acpi: registering VBNV 0 [ 0.242113] chromeos_acpi: registering VBNV 1 [ 0.242284] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.242462] chromeos_acpi: installed With the patch applied: [ 0.242580] chromeos_acpi: registering CHSW 0 [ 0.242714] chromeos_acpi: registering VBNV 0 [ 0.242817] chromeos_acpi: registering VBNV 1 [ 0.242990] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.243249] chromeos_acpi: installed Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74375 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29vc/amd/fsp/mendocino/FspmUpd: Update UDP structure for MDN-FSPChris.Wang
Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none TEST=Build/Boot to Chrome OS Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie4021cebb57e3ec22191486aafd9099eec0fbd99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-29vc/intel/fsp/mtl: Update header files from 3064_81 to 3084_85Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3084_85, previous version being 3064_81. FirmwareVersionInfo.h: 1. Define INTEL_FVI_SMBIOS_TYPE macro FSPM: 1. Remove deprecated UPD `BclkSource` 2. Address offset changes FSPS: 1. Add `CnviWifiCore` UPD 2. Address offset changes BUG=b:274051289 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I24dea1a31dbb592f9dea4246a3d490e5d23dca9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-27vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPDPatrick Huang
To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1 BUG=b:273841155 BRANCH=None TEST=Build Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/mendocino: Add UPDs for DPTC current limitsPatrick Huang
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC. Make sure UPD parameterare are set to be aligned. BUG=b:245942343 BRANCH=none TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD. Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-25soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu
Add support for Intel SPR-SP to uncore_acpi.c. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-20soc/amd/mendocino: Consume fsp misc_data hobJason Glenesk
Provide support function to query fsp misc_data hob and return smu reported power and thermal limit. BUG=b:253301653 TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in the hob. Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064Subrata Banik
This patch updates the Memory Hob Info data structure as per FSP v3064 source code change. BUG=b:273894357 TEST=Able to see `smbios type 17` table while booting google/rex. Without this patch: [DEBUG] 0 DIMM found With this patch: [DEBUG] 8 DIMM found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-08vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3064_81, previous version being 2523_80.. FSPM: 1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size SocTraceHubMemReg1Size. 2. Remove depricated UPD RDODTT. 3. Address offset changes. FSPS: 1. Address offset changes. FspUpd.h: 1.Corrected UPD signatures. BUG=b:TBD Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-02vc/siemens/hwilib: Change uint32_t return type to size_tJan Samek
The commit fcff39f0ea47 ("vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'") changed the 'dstsize' input parameter type from uint32_t to size_t. This patch changes also the return parameter, which is often directly compared with the aforementioned input parameter value. This should introduce no change on 32-bit builds and stay consistent across the project in the case of 64-bit builds and avoid comparisons of integers of different width here. BUG=none TEST=No changes to hwilib behavior on any of the siemens/mc_apl1 or siemens/mc_ehl variants. Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-02-23vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4031.01Bora Guvendik
The headers added are generated as per FSP v4031.01 BUG=b:270416522 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5513169, chrome-internal:5511170 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ia21807ee71c98489fd96f870c2d61f54e094c3d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-17vc/intel/fsp/mtl: Update header files from 2473_86 to 2523_80Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 2523_80, previous version being 2473_86. FSPM: 1. Rename DMI UPDs 2. Address offset changes FSPS: 1. Address offset changes BUG=b:266499304 Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-13soc/amd/mendocino: Add svc_write_postcode call instead of stubMartin Roth
To assist in debugging, add a way for PSP_verstage to send postcodes to the system. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05vc/amd/pi: Fix "No such file or directory"Elyes Haouas
Fix: cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs] Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-03vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshakeBora Guvendik
Expose DisableDynamicTccoldHandshake in header so that coreboot can disable it. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS, check UPD value in debug FSP build. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72693 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31vendorcode: Add VariableFormat.hPatrick Rudolph
Add the EDK2 variable format header in order to access the SPI flash variable store. https://github.com/tianocore/edk2/blob/edk2-stable202005/MdeModulePkg/Include/Guid/VariableFormat.h Commit Hash: 9d510e61fceee7b92955ef9a3c20343752d8ce3f Change-Id: Ibe44925555a7d1d2361dd48c0325b840bd68e0ca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61959 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-29vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header filesJonathan Zhang
Intel Sapphire Rapids Scalable Processor was product launched on Jan. 10, 2023. Add the FSP/HOB header files corresponding to 2022 ww43 git tag EGLSTRM.0.RPB.0090.D.03. Change-Id: I818da37c10f40045d98a9f73e82034c3fe6459e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71948 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-24vc/intel/fsp/mtl: Update header files from 2431_80 to 2473_86Kulkarni, Srinivas
Update header files for FSP for Meteor Lake platform to version 2473_86, previous version being 2431_80. FSPM: 1. Removed deprecated UPD PcieMultipleSegmentEnabled 2. Address offset changes FSPS: 1. Removed deprecated UPD ForcMebxSyncUp 2. Address offset changes BUG=b:261150757 Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.corp-partner.google.com> Change-Id: Ie396ad7ef4da2d1c52d37477bbb0815d2d650841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2023-01-18vc/siemens/hwilib: Use 3rd person singular in commentPaul Menzel
Change-Id: I1d9d123d2a29178541ab24c70ba529f6bfa2b6c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-18vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'Werner Zeh
The parameter 'maxlen' can be a bit confusing as it actually is referring to the size of the destination memory block where the requested parameter is stored to. Rename it to 'dstsize' and change the type to size_t to be more clear here. In addition, add a comment line for this parameter in the description of the function 'hwilib_get_field()'. This patch has no impact to the generated binary (checked with timeless build). Change-Id: I572dc0f3ff3d0c177d608332a88991396b82c2fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72045 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-01-18vc/siemens/hwilib: Fix coding styleWerner Zeh
As per the code style there is no space before the opening brace of a function declaration. Delete the space in hwilib.c and hwilib.h. Change-Id: Ie122ccd2dbae97f595463a097826d3415718a8bc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72044 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian
Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian
Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3503.00Bora Guvendik
The headers added are generated as per FSP v3503.00 BUG=b:261159242 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5318308, chrome-internal:5318129 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2023-01-13vc/siemens/hwilib/Makefile.inc: Fix "No such file or directory" errorElyes Haouas
Fix: cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-12vc/eltan/security/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-07vc/google: Add and use POST_CODE_CLEAR definitionMartin Roth
The CR50 code clears the post code value. Add this as a #define. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-03vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: CC romstage/mainboard/amd/pademelon/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/amd/gardenia/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24vc/google/chromeos: use fw_config field to return sar filenameEric Lai
Use fw_config field to return sar filename instead of fw_config probe. Return filename unconditionly because the sar_id must be valid in CBI. If invalid sar_id, the file won't exist in CBFS by design. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80Subrata Banik
Update header files for FSP for Meteor Lake platform to version 2431_80, previous version being 2404_00. FSPM: 1. Address offset changes FSPS: 1. Address offset changes Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14vc/google/chromeos/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13vc/eltan/security/mboot/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-12vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.hSaurabh Mishra
Changes include: - FirmwareVersionInfoHob.h is removed to use new header file FirmwareVersionInfo.h. BUG=b:260183604 TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-12vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.hSaurabh Mishra
Changes include: - Add header file FirmwareVersionInfo.h BUG=b:260183604 BRANCH=None TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69882 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/mediatek/mt8195/Makefile.inc: Remove path to non-existent folderElyes Haouas
The directory src/vendorcode/mediatek/mt8195/dramc/include never existed, and was added in commit b0b8dc37 (vendor/mediatek: Add MT8195 dram initialization code). Found using 'Wmissing-include-dirs' command option. Change-Id: Iec349e816a1b646f1ea5fa1db13e05a78ffe1af8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70464 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Also make sure that the address of the lcl_usb_phy struct is located below the 4GB boundary, so that the truncation to 32 bits won't result in pointing to a different memory location than intended. In this error case, which I don't expect to happen, print an error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its default values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09vc/intel/fsp: Update ADL N FSP headers from v3343.04 to v3343.05Shaik Shahina
Update generated FSP headers for Alder Lake N from v3343.04 to v3343.05. Changes include: -FspsUpd.h : Update UfsEnable UPD description in comments BUG=b:228110908 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa. Change-Id: Ieff33df2d2b0884a9788e05e06da5bdae1be08de Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70446 Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09vc/mediatek/mt8192/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I79457d8548700eeb534419f8e41990fad05edb68 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70398 Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09vc/eltan/security/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ia6f72acf0ae90c98ccf1fbbeedd7fbf5f194b4cc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70385 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configurationFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-06vc/cavium/bdk/libbdk-arch/bdk-numa.c: Fix old-style function definitionElyes Haouas
Change-Id: Ia56f813933143ef69c97f1b7643693c6eade6abe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-05vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.12Bora Guvendik
The headers added are generated as per FSP v3361.12 BUG=b:261159242 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Change-Id: Id7986017e1256627027a45325238bf29e0c00cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-26vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.hSaurabh Mishra
Fix compilation issue due to enum macro redefinition by safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig. Back-ported from commit f7e8adac7b3123 ("edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due to enum macro redefinition. BUG=b:260183604 TEST=Verify MTL Rex0 build with the patch and verify the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-19vc/amd/fsp/glinda/platform_descriptors.h: Update for glindaFred Reitberger
Update definitions on glinda used by birman. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I03065011581489b5345c16e225edc341e1d7811c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19vc/amd/fsp/morgana/platform_descriptors.h: Update for morganaFred Reitberger
Update definitions to match morgana FSP. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic893526789c05a298965702114d4a814466a5742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00vjadeja-intel
Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:255481471 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12security/tpm: improve tlcl_extend() signatureSergii Dmytruk
Until now tcg-2.0/tss.c was just assuming certain buffer size and hash algorithm. Change it to accept digest type, which the call sites know. Also drop `uint8_t *out_digest` parameter which was always `NULL` and was handled only by tcg-1.2 code. Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68745 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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