summaryrefslogtreecommitdiff
path: root/src/vendorcode
AgeCommit message (Collapse)Author
2014-01-12CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_fileVladimir Serbinenko
Number one reason to use cbfs_get_file was to get file length. With previous patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4674 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21chromeos: Check for recovery reason code in shared dataDuncan Laurie
When using RW firmware path the proper recovery reason can be retrieved from the shared data region. This will result in the actual reason being logged instead of the default "recovery button pressed" reason. 1) build and boot on falco 2) crossystem recovery_request=193 3) reboot into recovery mode, check reason with <TAB> 4) reboot back into chromeos 5) check event log entry for previous recovery mode: 25 | 2013-07-15 10:34:23 | Chrome OS Recovery Mode | Test from User Mode Change-Id: I6f9dfed501f06881e9cf4392724ad28b97521305 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61906 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4368 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07src/vendorcode/amd: remove Visual Studio remnants.Idwer Vollering
Delete files that (were overlooked and) are probably needed to build with Visual Studio. Remove doxygen helper files as well. Change-Id: I6b6cece178917ad9da1081eb6b1bb9be33066a77 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4489 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-05AMD IMC AGESA: Access the data in stack by correct lengthZheng Bao
The bug is hard to find. We were adding the feature of fan control. We met some strange things which could not be explained. Like, sometimes adding printk let the error disappear. Then we traced the code by hardware debug tool (HDT). It turned out the data in stack was overwritten. The values of AccessWidthxx are { AccessWidth8 = 1, AccessWidth16, AccessWidth32,} For the case of AccessWidth8, we only need to access the index/data once. But ReadECmsg and WriteECmsg did the loop twice, 1 more time than they are supposed to do. The data in stack next to "Value" would be overwritten. For all the cases, the code should be OpFlag = OpFlag & 0x7f; switch (OpFlag) { case 1: /* AccessWidth8 */ OpFlag = 0;break; case 2: /* AccessWidth16 */ OpFlag = 1;break; case 3: /* AccessWidth32 */ OpFlag = 3;break; case 4: /* AccessWidth64 */ OpFlag = 7;break; default: error; } Actually, the caller only takes AccessWidth8 as the parameter. We can ignore other cases for now. That is an AGESA bug. AMD's AGESA team own this code. They have given the response that they are going to update this in next release. I presume let them decide the proper way to fix that. Before that, I change the code as little as possible to make it run without crash. Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4297 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-12-04Add Intel FSP northbridge support Sandybridge and IvybridgeMarc Jones
Add support for Sandybridge and Ivybridge using the Intel FSP. The FSP is different enough to warrant its own source files. This source handle the majority of FSP interaction. "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4015 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03vboot: use out_flags to indicate recovery modeDuncan Laurie
In order to make the proper decision on loading the option rom or not the recovery mode setting needs to be known. Normally this is detected by asking the EC, but if recovery is requested with crossystem then the EC does not know about it. Instead we need to check the output flags from VbInit(). Change-Id: I09358e6fd979b4af6b37a13115ac34db3d98b09d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57474 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4223 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03vboot: Do not pass OPROM_MATTERS flag to VbInitDuncan Laurie
Since we are using VBNV to determine if developer mode is active we do not need the messy OPROM hook magic any longer. Change-Id: I1b9effef3ef2aa84e916060d8e61ee42515a2b7c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57473 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4222 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Add option to disable ChromeOSKyösti Mälkki
Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3977 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02vboot: use out_flags to indicate dev modeAaron Durbin
In order to make the proper decision on loading the option rom or not the developer mode setting needs to be known. Under early firmware selection it is possible to know the state of developer mode by a flag in out flags. Use this flag when early firmware selection is being employed to determine if developer mode is enabled or not. Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57380 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4218 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25slippy: Minor vboot related fixesDuncan Laurie
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Honor vboot's request to load the VGA option ROMBill Richardson
This removes an earlier patch that caused the VGA option ROM to be loaded by coreboot even in normal mode when it isn't needed. Change-Id: Ie0a331a10fff212a2394e7234a0dbb37570607b7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48173 Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4125 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Fix compile error in chromeos by adding stddef.hDuncan Laurie
Compile was failing with the following error: In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0, from src/vendorcode/google/chromeos/chromeos.c:22: vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t' src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload': src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function) Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48289 Reviewed-on: http://review.coreboot.org/4131 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-15vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7WANG Siyuan
The platform initialization (PI) code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. Use the name Kabini instead of Kerala everywhere. Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0 as used in `AGESA_VERSION_STRING`. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3935 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-27AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in YangtzeWANG Siyuan
src/southbridge/amd/agesa/hudson/Kconfig config default value, mainboard Kconfig config value for specific mainboard. bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3 Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3879 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15CBFS: Change the signature of cbfs_decompress.Gabe Black
Instead of returning 0 on success and -1 on error, return the decompressed size of the data on success and 0 on error. The decompressed size is useful information to have that was being thrown away in that function. Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-06AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER`Paul Menzel
Copied from a similar commit for Family 10h AGESA [1] Remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments [2] fc47bfa Revert "AMD f14 vendorcode: Fix warning" Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD AGESA: Add missing breaks to switch statement in one fileBruce Griffith
This is the same patch as an earlier one applied to family 15 [1]. Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". [1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ... Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Kabini: Add "const" modifier to AGESA function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. This same change was made for AMD Trinity APUs (Family15tn) [1]. [1] 283ba78 AGESA: Add "const" modifier to function parameters Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3837 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-05AMD SATA: Correct "them implement" to "then implement" in commentsPaul Menzel
This changelist was cherry-picked from merged community code for Parmer [1] and the paths modified so that the Parmer modification is applied against Olive Hill. [1] 0086162 AMD SATA: Correct _them implement_ ... in comments Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3841 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-04AMD Kabini: Add AGESA/PI code for new processor familySiyuan Wang
Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Nick Dill <nick.dill@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3836 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-06-28amd/agesa/f15/Lib/amdlib.c: Add missing breaks to switch statementBruce Griffith
Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". Change-Id: I3d43acaf64e2e2d9717421cb547fec35e582cf8b Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3539 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28amd/agesa/f15/Proc/CPU: Add length modifier to eliminate compiler warningsBruce Griffith
This change adds length modifiers to constant values to eliminate compiler warning messages. Change-Id: I032cb37cec788e2b5f79f5bbf9efc19a7892dc14 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3538 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28vendorcode/amd/agesa/f15: Eliminate compiler warningsBruce Griffith
This change is mostly type casts to eliminate compile time warnings. These specific changes are mostly cherry-picked from AMD Family 14 code and, as such, contain artifacts copied over from F14. For example, there are a number of UINT64 casts that are commented out rather than removed. This is to maintain consistency between AGESA versions. Ultimately, this is in preparation for turning on warnings as errors for AMD Family 15 server parts. Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3525 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-09fam15 vendorcode: Change license to BSD from AMD software licenseSiyuan Wang
fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the AMD software license agreement. Change this license to 3-clause BSD. Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-06AGESA: Add "const" modifier to function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16chromeos: use cache-as-ram migration API for vbnvAaron Durbin
It's possible that the vbnv global variables may be accessed in romstage after cache-as-ram is torn down. Therefore use the cache-as-ram migration API. Wrappers were written to wrap the API to keep the existing code as close as possible. Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-14EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.Ronald G. Minnich
build-snow got broken when the snow makefile improved. So fix it. While we're at it, create a script like the update-microcode scripts that gets the bl1. I thought about making this a common script but the various names and paths always evolve, leaving me thinking it's not worth it. This script is just a piece of the snow build script. Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3238 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-04AMD F15: Fix warning in Proc/CPU/FeatureMartin Roth
Fix Warning: cpuFeatureLeveling.c:265, GNU Compiler 4 (gcc), Priority: Normal cast to pointer from integer of different size [-Wint-to-pointer-cast] with an intermediate cast to (intptr_t) Change-Id: I3bfd2ea1e797632316675338789dabef8f73ba64 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04AMD F15: Fix warnings in Proc/CommonMartin Roth
This fixes 3 warnings in the Proc/Common directory: AmdS3Save.c:250, GNU Compiler 4 (gcc), Priority: Normal AmdS3LateRestore.c:123, GNU Compiler 4 (gcc), Priority: Normal cast from pointer to integer of different size [-Wpointer-to-int-cast] Fixed with a second cast to (intptr_t) AmdInitReset.c:153, GNU Compiler 4 (gcc), Priority: Normal statement with no effect [-Wunused-value] Fixed by commenting the line out as it is in the other families code. Change-Id: Ib35ec466671712af01568b7c2a18ee138fe883c0 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3125 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03AMD SATA: Correct »them implement« to »then implement« in commentsPaul Menzel
The following command was used to correct all occurences of this typo. $ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/' Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-20Eliminate use of pointers in coreboot tableStefan Reinauer
Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3115 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-04-16AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in commentsPaul Menzel
When looking into possible reasons for a proposed revert [1], I noticed that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14AMD CIMx sb800/SATA.c, sb900/Sata.c: Fix R*AI*D typo in commentsPaul Menzel
Spell RAID correctly in comments. Found with the following command. $ git grep -i riad Change-Id: I68e8476d885a88df589d25f88cc158d71eb04e07 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01chromeos: honor MOCK_TPM=1Aaron Durbin
The TPM code wasn't previously honoring MOCK_TPM=1. Because of this, boards with TPMs that didn't handle S3 resume properly would cause a hard reset. Allow one to build with MOCK_TPM=1 on the command line so that S3 can still work. Change-Id: I9adf06647de285c0b0a3203d8897be90d7783a1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2976 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29chromeos: remove CACHE_ROM automatic selectionAaron Durbin
It's not appropriate for the chromeos Kconfig to automatically select CACHE_ROM. The reason is that enabling CACHE_ROM is dependent on the board and chipset atrributes. Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23vboot module: fix compilation issuesAaron Durbin
There were 3 things stopping the vboot module from being compiled: 1. The vboot_reference code removed in the firmware/arch/$(ARCH)/include directory. This caused romcc to fail because romcc fails if -I<dir> points to non-existent directory. 2. The rmodule API does not have the no-clearing-of-bss variant of the load function. 3. cbfs API changes. Change-Id: I1e1296c71c5831d56fc9acfaa578c84a948b4ced Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22Unify coreboot table generationStefan Reinauer
coreboot tables are, unlike general system tables, a platform independent concept. Hence, use the same code for coreboot table generation on all platforms. lib/coreboot_tables.c is based on the x86 version of the file, because some important fixes were missed on the ARMv7 version lately. Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2863 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-03-22vboot: pass correct coreboot include pathsAaron Durbin
The coreboot include were not being passed correctly when building vboot_reference. The paths being included were of the src/<dir> form. However, vboot_reference lives in src/../vboot_reference. That coupled with the recursive make call made vboot_reference not see coreboot's header files. Fix this by appending ../ to coreboot's default include paths. Change-Id: I73949c6f854ecfce77ac36bb995918d51f91445e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2860 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22coreboot: add vboot_handoff to coreboot tablesAaron Durbin
The vboot_handoff structure contians the VbInitParams as well as the shared vboot data. In order for the boot loader to find it, the structure address and size needs to be obtained from the coreboot tables. Change-Id: I6573d479009ccbf373a7325f861bebe8dc9f5cf8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22romstage: add support for vboot firmware selectionAaron Durbin
This patch implements support for vboot firmware selection. The vboot support is comprised of the following pieces: 1. vboot_loader.c - this file contains the entry point, vboot_verify_firmware(), for romstage to call in order to perform vboot selection. The loader sets up all the data for the wrapper to use. 2. vboot_wrapper.c - this file contains the implementation calling the vboot API. It calls VbInit() and VbSelectFirmware() with the data supplied by the loader. The vboot wrapper is compiled and linked as an rmodule and placed in cbfs as 'fallback/vboot'. It's loaded into memory and relocated just like the way ramstage would be. After being loaded the loader calls into wrapper. When the wrapper sees that a given piece of firmware has been selected it parses firmware component information for a predetermined number of components. Vboot result information is passed to downstream users by way of the vboot_handoff structure. This structure lives in cbmem and contains the shared data, selected firmware, VbInitParams, and parsed firwmare components. During ramstage there are only 2 changes: 1. Copy the shared vboot data from vboot_handoff to the chromeos acpi table. 2. If a firmware selection was made in romstage the boot loader component is used for the payload. Noteable Information: - no vboot path for S3. - assumes that all RW firmware contains a book keeping header for the components that comprise the signed firmware area. - As sanity check there is a limit to the number of firmware components contained in a signed firmware area. That's so that an errant value doesn't cause the size calculation to erroneously read memory it shouldn't. - RO normal path isn't supported. It's assumed that firmware will always load the verified RW on all boots but recovery. - If vboot requests memory to be cleared it is assumed that the boot loader will take care of that by looking at the out flags in VbInitParams. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20f15tn/Include/OptionIdsInstall.h: Remove idle `… || )`Siyuan Wang
Change-Id: I4aba6cc490ab24c6db345c0c5a64a6a9985ed0ab Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/2864 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-16google/snow: rename a file so that it is clear what board it is forRonald G. Minnich
One might wonder what a board named 'build' does. Rename the file to build-snow. The fact that it is in a directory with google in the name should be enough to identify the vendor. Change-Id: I0b473cdce67d56fc6b92032b55180523eb337d66 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2766 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-08AGESA: Fix CR0_PE bit defineKonstantin Aladyshev
AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15Konstantin Aladyshev
_RDMSR instruction loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. EDX:EAX = MSR[ECX] So bit 49 will be contained in EDX register. Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis). PfcStrideDis bit disables stride prefetch generation. This leads to memory bandwidth loss. _________ Supermicro H8QGI board After applying this change i observed huge memory bandwidth increase in tests that runs on small amount of cores. But unfortunately it doesn't affect overall bandwidth results on 4P system with 48 cores. So i think that in this system leading limiting factor is AMD HT-ASSIST feature (Probe filter). But right now it is not working. System stucks in Linux boot. I have done some experiments and figured out that stuck happens when system have cores in compute unit (CU) other than CU with BSC (boot strap core). CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...) So with probe filter i can boot Linux with one (BSC) or two (BSC + secondary core in its CU) cores. And with this configuration i can see memory bandwidth on 1 core (or two cores) close to original bios. Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2588 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-25google/snow: enable GPIO entries and CHROMEOS in buildingRonald G. Minnich
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-24AMD f14 vendorcode: Fix warningMartin Roth
Add brackets around initializer in #define for PCIE_DDI_DATA_INITIALIZER to fix the warning: PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal missing braces around initializer [-Wmissing-braces] This warning happens for Inagua and South Station Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2495 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-18AMD Family12h: Fix warningsMartin Roth
Add needed prototypes to .h files. Remove unused variables and fix types in printk statements. Add #IFNDEFs around #DEFINEs to keep them from being defined twice. Fix a whole bunch of casts. Fix undefined pre-increment behaviour in a couple of macros. These now match the macros in the F14 tree. Change a value of 0xFF that was getting truncated when being assigned to a 4-bit bitfield to a value of 0x0f. This was tested with the torpedo build. This fixes roughly 132 of the 561 warnings in the coreboot build so I'm not going to list them all. Here is a sample of the warnings fixed: In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0: src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls] In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0: src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes] src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info': src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable] src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources': src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat] In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes] In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0: src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow] And fixed a boatload of these types of warning: src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default] Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-11AMD SB900: fix warningsMartin Roth
Add a prototype to a .h file Remove an unused file (GppHp.c) from the build by deleting it from the makefile. I left the file since this is vendorcode. This is the code for PCIe hotplug. Inside GppHp.c, make functions not called from outside static. This obviously isn't important since the file isn't used, but for the sake of the cleanup I thought I'd go ahead with it... This was tested with the torpedo build. This fixes these warnings: src/vendorcode/amd/cimx/sb900/Dispatcher.c: In function 'LocateImage': src/vendorcode/amd/cimx/sb900/Dispatcher.c:193:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/cimx/sb900/Usb.c:740:1: warning: no previous prototype for 'XhciA12Fix' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:65:1: warning: no previous prototype for 'sbGppHotPlugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotPlugSmiProcess': src/vendorcode/amd/cimx/sb900/GppHp.c:76:5: warning: implicit declaration of function 'SbStall' [-Wimplicit-function-declaration] src/vendorcode/amd/cimx/sb900/GppHp.c: At top level: src/vendorcode/amd/cimx/sb900/GppHp.c:101:1: warning: no previous prototype for 'sbGppHotUnplugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:134:1: warning: no previous prototype for 'sbGppHotplugSmiCallback' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotplugSmiCallback': src/vendorcode/amd/cimx/sb900/GppHp.c:158:5: warning: implicit declaration of function 'outPort80' [-Wimplicit-function-declaration] Change-Id: I5a1a20eeb81e1f4d59e3e3192f081e11d8506f56 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2349 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11snow: make build script erase 192KB instead of 128KBDavid Hendricks
This will make the build script wipe out more flash memory content. Our image is a bit bigger now that we're testing with payloads, so this is just added paranoia to prevent weird surprises caused by not flashing the full image. Change-Id: I31969922079e96886573d9d802266eb0052277cd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06AMD Fam14 - Fix warningsMartin Roth
Added casts and a couple of #ifdefs to fix the warnings in the vendorcode/amd/agesa/f14 codebase. This will allow us to re-enable 'all warnings being treated as errors' in boards such as Persimmon that are using this code. That change will follow. These are the warnings that are fixed by this patch: src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToTempRamAtPost': src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:219:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToMainRamAtPost': src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:372:30: warning: comparison between pointer and integer [enabled by default] src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:381:33: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c: In function 'ApUtilSetupIdtForHlt': src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:863:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:872:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c: In function 'LoadMicrocode': src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c:211:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapManagerInit': src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:167:52: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:183:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:669:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:676:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:683:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:684:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:687:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:691:21: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:696:3: warning: return makes pointer from integer without a cast [enabled by default] In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0, from src/northbridge/amd/agesa/family14/northbridge.c:36: src/vendorcode/amd/agesa/f14/AGESA.h:1132:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0, from src/northbridge/amd/agesa/family14/northbridge.c:36: src/vendorcode/amd/agesa/f14/AGESA.h:1133:0: warning: "TOP_MEM2" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Verified on persimmon. Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2293 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Steven Sherk <steven.sherk@se-eng.com>
2013-01-22F15tn: Fix all warnings, enable warnings as errorsMartin Roth
Enable 'all warnings being treated as errors' in thatcher and parmer. Fixed the following warnings on parmer / thatcher: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c: In function 'GetPstateGatherDataAddressAtPost': src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c: In function 'MemNInitNBDataTN': src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0: src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0: warning: "LOCAL_APIC_ADDR" redefined [enabled by default] src/include/cpu/x86/lapic_def.h:9:0: note: this is the location of the previous definition In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0, from src/mainboard/amd/parmer/mainboard.c:28: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2171 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-21Save and restore F15TN graphics command registerMartin Roth
In the AGESA routine GfxInitSview() called in the S3save path, the IO Space bit was getting cleared from the command register. This kept seabios from initializing the video bios. If the vbios was loaded by coreboot, this routine was skipped, allowing seabios to initialize vbios as well. I have modified the routine to save and restore the command register instead of clearing the IO Space bit. Change-Id: I756b0606adbc47da96780308c911852e39f547c7 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2172 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21F15tn / Hudson: Change SATA NumOfPorts register settingMartin Roth
The Number of Ports register says that it should be set to the maximum number of ports supported by the silicon. AGESA was setting this to be the number of enabled ports. If port 1 was the only port with a drive, this value got set to 0, indicating 1 port. This causes SeaBIOS to only look at port 0 and quit, never finding the drive on port 1. Dave Frodin: I also verified that this patch allows a SATA drive plugged into port 2 to be detected without a device in port 1. Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2165 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-12No random directoriesStefan Reinauer
Please, don't just add random directories for a single file because it seems convenient. There already is a chromeos directory, that should be used. Change-Id: I625292cac4cbffe31ff3e3d952b11cd82e4b151e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2137 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10Fix 2 infinite loops if IMC doesn't respondMartin Roth
ACPI code: The ACPI code is not currently being compiled in by default, but assuming that it will be at some point, I'm fixing the loop that waits for the IMC to respond after sending it a command. The loop now exits after 500ms, similar to the function in agesa. Agesa Code: a 16 bit variable will always be less than 100000. Change to be a 32 bit variable. Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-02AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functionsAladyshev Konstantin
Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE". This results in a failure of init late function: "agesawrapper_amdinitlate failed: 1" It happens because TRUE = 1 = AGESA_UNSUPPORTED. Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem. Only family f15tn does not have such bug. This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family? Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15). Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2070 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-12-12SB800: Add IMC ROM and fan control.Martin Roth
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800 platforms. - Allows user to add the IMC rom to the build and to configure the location of the "signature" between the allowed positions. - Allows for no fan control, manual setup of SB800 Fan registers, or setup of the IMC fan configuration registers. - Register configuration is done through devicetree.cb. No files need to be added for new platform configuration. - Initial setup is for Persimmon, but may be extended to any cimx/sb800 platform. Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-16Reduce number of per-mainboard changesStefan Reinauer
- Add mainboard_smi.c from arch/x86/Makefile if it's there - Add mainboard's chromeos.c from the chromeos Makefile Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1835 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13cros: Inform U-Boot via fake gpio when VGA Option ROM is loadedBill Richardson
This prepares the way for vboot to inform coreboot when it needs the VGA Option ROM loaded. Coreboot can't always know when it's needed (with keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not). By the time we get to U-Boot, it's too late, so we need two extra bits - one for vboot to tell coreboot to load the Option ROM and another for coreboot to let vboot know it's been done. This change sets up the communication, but doesn't act on it just yet. Even with this CL we always load the VGA Option ROM, so there's nothing to test. There should be no user-visible change. Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/1822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12vboot: Add option to skip TPM resume on S3 resumeStefan Reinauer
Change-Id: Ie4a98cc8af0dbcf09c7ace79668949ace5938c12 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1752 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
The MRC cache code, as implemented, in some cases uses configuration settings for MRC cache region, and in some cases - the values read from FMAP. These do not necessarily match, the code should use FMAP across the board. This change also refactors mrccache.c to limit number of iterations through the cache area and number of fmap area searches. Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1788 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Change flashmap base to reflect new FMAP in U-bootDuncan Laurie
The RO_FMAP base moved from 0x5f0000 to 0x610000. Also update Kconfig default and add a descripton so the default can be changed by boards. Change-Id: I0caad0ce6e6f19750dbbf042a5a489b558f62b96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1705 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-08ELOG: Find flash base in FMAP if possibleDuncan Laurie
Now that we have FMAP support in coreboot use it to find the offset in flash for ELOG to use. If coreboot has elog configured with a smaller size then use that over the FMAP size. This is because I set aside a 16KB region in the FMAP but we only use 4KB of it to keep the impact to boot/resume speed to a minimum. FMAP: Found "FMAP" version 1.0 at ffe10000. FMAP: base = 0 size = 800000 #areas = 32 FMAP: area RW_ELOG found FMAP: offset: 3f0000 FMAP: size: 16384 bytes FMAP: No valid base address, using 0xff800000 ELOG: base=0x003f0000 base_ptr=0xffbf0000 ELOG: MEM @0x00190ad8 FLASH @0xffbf0000 ELOG: areas are 4096 bytes, full threshold 3072, shrink size 1024 Change-Id: I3d826812c0f259d61f41b42797c58dd179f9f1c8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1706 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
Until now, the MRC cache position and size was hard coded in Kconfig. However, on ChromeOS devices, it should be determined by reading the FMAP. This patch provides a minimalistic FMAP parser (libflashmap was too complex and OS centered) to allow reading the in-ROM flash map and look for sections. This will also be needed on some partner devices where coreboot will have to find the VPD in order to set up the device's mac address correctly. The MRC cache implementation demonstrates how to use the FMAP parser. Change-Id: I34964b72587443a6ca4f27407d778af8728565f8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1701 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-10-30Fix ExecuteFinalHltInstruction function in f15h family codeKostr
Current ExecuteFinalHltInstruction function doesn't work well. (at least in configuration Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU)) System reboots when trying to halt core 2,4,6,8 or 10 (OS6234WKTCGGU is 12 core processor) Based on this information, i think that code doesn't really work with f15 compute unit (CU) system. Replacing ExecuteFinalHltInstruction function with analogous function from f15tn family code fix this problem. Both functions written from the same cahalt.asm file, but f15tn version seems more completed Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf Signed-off-by: Kostr <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/1569 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-22change conflicted typedef in src/vendorcode/amd/agesa/f15/Porting.hSiyuan Wang
src/vendorcode/amd/agesa/f15/Porting.h has some conflicted typedef with src/include/cpu/amd/common/cbtypes.h. These conflicted defines can lead to errors. Change-Id: Idad0794018bf0bd0e4e52a5aa062a12766d56c8e Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1592 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-13AMD Hudson: Enable HD audiozbao
Something about HD audio was scrubbed. Take it back. Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1427 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-07-26ELOG: Fix reporting of developer/recovery modesDuncan Laurie
Recent changes in EC/Vboot/U-boot have completely broken the logging of developer and recovery modes. Recovery mode may not be in VBNV, so if that is zero and yet we are in recovery mode then assume it is there because the button/key was pressed. Since there may not be any actual developer mode switch we look if option rom is loaded and the system is not in recovery mode and consider that as developer mode. Change-Id: I70104877b24de477217e1ff5b3a019aef22343ec Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25ELOG: Log events for Chrome OS developer/recovery modeDuncan Laurie
If a Chrome OS device is in developer mode log an event. When the device is in recovery mode also log an event and provide the recovery reason. Enable developer mode and trigger recovery mode and verify that the events are logged: 238 | 2012-06-23 17:31:56 | Chrome OS Developer Mode 239 | 2012-06-23 17:31:56 | Chrome OS Recovery Mode | User Requested from Developer Screen Change-Id: I14d41f44e04fd91340569617c7314da7e35a154f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1321 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUEzbao
The default return value should be AGESA_SUCCESS, which is zero. If it was set as TRUE, the AGESA wrapper would think it was AGESA_UNSUPPORTED. That would make no sense. And it would produce ASSERT warning in AGESA wrapper. On my parmer board, with Engine sample processor, it can not create the correct DMI table. Routine initlate will return AGESS_ERROR. ------Serial message--------- ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c', line 427 DmiTable:100123c3, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:1001ccd4, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 ----------------------------- I believe the processor with acceptable name string will create the right DMI. Change-Id: Ie86955cf9affffc964a7c9f4a2c63077ef2030de Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1350 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared DataStefan Reinauer
coreboot used to pass some information to u-boot in the coreboot table and other information in a modified flat device tree. Since the FDT code was never upstreamed and removed from our tree, u-boot was changed to get the information it needs from the coreboot table alone. However, in the process of this change only the vboot shared data structure was passed on by coreboot, so when u-boot tried to update the ChromeOS specific ACPI entries, it would accidently overwrite the vboot data. This patch passes on the ChromeOS specific ACPI data structure instead of the vboot shared data. Another change to u-boot will teach it how to get to the vboot shared data from there. Change-Id: Ifbb64eafc0d9967887b4cdeebf97d0c4ce019290 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1282 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Move GGL0001 ACPI code to generic ChromeOS codeStefan Reinauer
The only difference in this code on all our platforms is the array describing the GPIOs. Hence, only keep that array in the mainboard ChromeOS directory and move everything else to generic ChromeOS ACPI code. Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03AGESA F15tn: AMD family15 AGESA code for Trinityzbao
AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29ChromeOS: Remove remnants of FDT supportStefan Reinauer
Originally, on ChromeBooks, coreboot would provide a modified u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot can now create all the information it needs from the coreboot table and add it to its device tree itself. This means we can drop this (anyways unused) code. Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/912 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-10CIMx: Allow #define LEGACY_FREE overridesMartin Roth
For legacy free AMD systems, the #define LEGACY_FREE cannot currently be overridden. This patch allows the platform_cfg.h to override that. (I know we want to get away from that, but for now...) Also allow BIOS_SIZE to be overridden on SB700 cimx based platforms. Change-Id: I570115248bcbc686062bfb66acb56208240b847a Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1018 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-10Unmark source files as executablesAlec Ari
Change source file modes from 755 to 644 The following files have been grepped for changes: *.c *.h *Kconfig* *Makefile* Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-27ChromeOS: add missing string.h in gnvs.cStefan Reinauer
string.h is required to build with the reference toolchain. Change-Id: I9fd8d2ea8fc676d3502989cbcc7aefe3b2d738b6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/935 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-12S3 code in vendorcode folder.zbao
Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-04Don't unconditionally show ChromeOS optionsStefan Reinauer
Google ChromeOS specific options were shown in the main menu unconditionally, even on non-ChromeOS devices. Instead, hide these options unless CONFIG_CHROMEOS is set, and also put them in a separate menu. Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/848 Reviewed-by: Martin Roth <martin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-04-02S3 code whitespaces changes.zbao
some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02Add Google ChromeOS vendor supportStefan Reinauer
Google's ChromeOS can be booted super fast and safely using coreboot. This adds the ChromeOS specific code that is required by all ChromeBooks to do this. Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/817 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add TPM support to corebootStefan Reinauer
and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add Google ChromeOS vendorcode directoryStefan Reinauer
... and hook it up in Kconfig. More code to come. Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/813 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-14AGESA family 12 changes to fix torpedo warningsMartin Roth
Fixes the warnings generated in the torpedo mainboard build by AGESA. Removing broken tests. Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-02SB700 southbridge: AMD SB700/SP5100 southbridge CIMX codeKerry Sheh
Support AMD SB700 and SP5100 chipsets. Change-Id: I0955abf7f48a79483f624b46a61b22711315f888 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/560 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-02RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX codeKerry Sheh
Change-Id: If9908ffeb5b707a660db38dc44f5118347cbcc06 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-26AGESA F15: AMD family15 AGESA codeKerry Sheh
AMD AGESA code to support Orochi platform family15 model 00-0fh processores, AMD C32, G34, and AM3r2 Sockets are supported. Change-Id: If79392c104ace25f7e01db794fa205f47746bcad Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/554 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6Stefan Reinauer
Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/268 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-11sb800: sata combine mode configure fixKerry Sheh
Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller 0: IDE controller is exposed and Combined Mode is enabled. SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5 1: IDE controller is hidden and Combined Mode is disabled, SATA controller has full control of all 6 Ports when operating in non-IDE mode Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/229 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15AMD Agesa macro expansion fixefdesign98
This change fixes the use of a macro that was previously modified to fix a warning. The macro was used in a manner that doubly incremented a pointer. The pointer increment was removed from the macro call and moved elsewhere. In addition, an unused macro was removed from both Family 12 and Family 14 code. Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-15AMD Agesa changes to fix F14 boot issuesefdesign98
This collection of changes fixes a buffer addressing issue by removing one level of indirection, fixes an Agesa HT mailbox retrieval bug, and fixes a buffer location-by-signature issue. Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/215 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2011-09-07AMD SB800 southbridge updateKerry She
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>