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Add support for Intel SPR-SP to uncore_acpi.c.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Provide support function to query fsp misc_data hob and return smu
reported power and thermal limit.
BUG=b:253301653
TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in
the hob.
Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b
Signed-off-by: Jason Glenesk <jason.glenesk@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the Memory Hob Info data structure as per FSP
v3064 source code change.
BUG=b:273894357
TEST=Able to see `smbios type 17` table while booting google/rex.
Without this patch:
[DEBUG] 0 DIMM found
With this patch:
[DEBUG] 8 DIMM found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Update header files for FSP for Meteor Lake platform to
version 3064_81, previous version being 2523_80..
FSPM:
1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size
SocTraceHubMemReg1Size.
2. Remove depricated UPD RDODTT.
3. Address offset changes.
FSPS:
1. Address offset changes.
FspUpd.h:
1.Corrected UPD signatures.
BUG=b:TBD
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The commit fcff39f0ea47 ("vc/siemens/hwilib: Rename 'maxlen' to
'dstsize'") changed the 'dstsize' input parameter type from uint32_t to
size_t.
This patch changes also the return parameter, which is often directly
compared with the aforementioned input parameter value. This should
introduce no change on 32-bit builds and stay consistent across the
project in the case of 64-bit builds and avoid comparisons of integers
of different width here.
BUG=none
TEST=No changes to hwilib behavior on any of the siemens/mc_apl1 or
siemens/mc_ehl variants.
Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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The headers added are generated as per FSP v4031.01
BUG=b:270416522
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Cq-Depend: chrome-internal:5513169, chrome-internal:5511170
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ia21807ee71c98489fd96f870c2d61f54e094c3d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Update header files for FSP for Meteor Lake platform to
version 2523_80, previous version being 2473_86.
FSPM:
1. Rename DMI UPDs
2. Address offset changes
FSPS:
1. Address offset changes
BUG=b:266499304
Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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To assist in debugging, add a way for PSP_verstage to send postcodes to
the system.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix:
cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Expose DisableDynamicTccoldHandshake in header so that
coreboot can disable it.
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=Boot to OS, check UPD value in debug FSP build.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72693
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the EDK2 variable format header in order to access the SPI flash
variable store.
https://github.com/tianocore/edk2/blob/edk2-stable202005/MdeModulePkg/Include/Guid/VariableFormat.h
Commit Hash: 9d510e61fceee7b92955ef9a3c20343752d8ce3f
Change-Id: Ibe44925555a7d1d2361dd48c0325b840bd68e0ca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61959
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel Sapphire Rapids Scalable Processor was product launched
on Jan. 10, 2023.
Add the FSP/HOB header files corresponding to 2022 ww43 git tag
EGLSTRM.0.RPB.0090.D.03.
Change-Id: I818da37c10f40045d98a9f73e82034c3fe6459e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71948
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Update header files for FSP for Meteor Lake platform to
version 2473_86, previous version being 2431_80.
FSPM:
1. Removed deprecated UPD PcieMultipleSegmentEnabled
2. Address offset changes
FSPS:
1. Removed deprecated UPD ForcMebxSyncUp
2. Address offset changes
BUG=b:261150757
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.corp-partner.google.com>
Change-Id: Ie396ad7ef4da2d1c52d37477bbb0815d2d650841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
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Change-Id: I1d9d123d2a29178541ab24c70ba529f6bfa2b6c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The parameter 'maxlen' can be a bit confusing as it actually is
referring to the size of the destination memory block where the
requested parameter is stored to. Rename it to 'dstsize' and change
the type to size_t to be more clear here.
In addition, add a comment line for this parameter in the description
of the function 'hwilib_get_field()'.
This patch has no impact to the generated binary (checked with timeless
build).
Change-Id: I572dc0f3ff3d0c177d608332a88991396b82c2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72045
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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As per the code style there is no space before the opening brace of a
function declaration. Delete the space in hwilib.c and hwilib.h.
Change-Id: Ie122ccd2dbae97f595463a097826d3415718a8bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72044
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace old style declaration "const static" with "static const".
This to enable "Wold-style-declaration" command option.
Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Select HSP config to indicate that the SoC includes Hardware Security
Processor. This will allow PSP verstage to get and report the HSP state.
BUG=None
TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify
that HSP is reported during the boot sequence.
Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Add an SVC call to get the state of Hardware Security Processor (HSP) in
AMD SoCs. This SVC call will be used from PSP verstage to get and
report HSP state.
BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state
is read and reported in the firmware logs.
Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The headers added are generated as per FSP v3503.00
BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Cq-Depend: chrome-internal:5318308, chrome-internal:5318129
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Fix:
cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Fix:
cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.
This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.
BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow
Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CR50 code clears the post code value. Add this as a #define.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add the UPD dxio_tx_vboost_enable for PCIe optimization.
It will impact the PCIe signal integrity, need to double-confirm
the SI result after enabling this setting.
BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
the FSP log.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix:
CC romstage/mainboard/amd/pademelon/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/amd/gardenia/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use fw_config field to return sar filename instead of fw_config probe.
Return filename unconditionly because the sar_id must be valid in
CBI. If invalid sar_id, the file won't exist in CBFS by design.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Add an SVC command to get the previous boot status. If there is any
pre-x86 boot failure in the previous boot cycle, PSP stores it in warm
reset persistent register and triggers a warm reset. PSP verstage on the
subsequent boot gets the previous boot status and reports any failure to
the vboot before a FW slot is selected.
BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure
scenario by corrupting certain firmware blobs and observe that PSP
reports the failure boot status. On a normal boot, observed that PSP
reports successful boot.
Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update header files for FSP for Meteor Lake platform to
version 2431_80, previous version being 2404_00.
FSPM:
1. Address offset changes
FSPS:
1. Address offset changes
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Changes include:
- FirmwareVersionInfoHob.h is removed to use new header file
FirmwareVersionInfo.h.
BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Changes include:
- Add header file FirmwareVersionInfo.h
BUG=b:260183604
BRANCH=None
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69882
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The directory src/vendorcode/mediatek/mt8195/dramc/include never
existed, and was added in commit b0b8dc37
(vendor/mediatek: Add MT8195 dram initialization code).
Found using 'Wmissing-include-dirs' command option.
Change-Id: Iec349e816a1b646f1ea5fa1db13e05a78ffe1af8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70464
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this. Also make sure that the address of the lcl_usb_phy
struct is located below the 4GB boundary, so that the truncation to 32
bits won't result in pointing to a different memory location than
intended. In this error case, which I don't expect to happen, print an
error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its
default values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update generated FSP headers for Alder Lake N from v3343.04 to v3343.05.
Changes include:
-FspsUpd.h : Update UfsEnable UPD description in comments
BUG=b:228110908
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.
Change-Id: Ieff33df2d2b0884a9788e05e06da5bdae1be08de
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70446
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: I79457d8548700eeb534419f8e41990fad05edb68
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70398
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: Ia6f72acf0ae90c98ccf1fbbeedd7fbf5f194b4cc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70385
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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|
Change-Id: Ia56f813933143ef69c97f1b7643693c6eade6abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The headers added are generated as per FSP v3361.12
BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: Id7986017e1256627027a45325238bf29e0c00cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Fix compilation issue due to enum macro redefinition by safeguarding
definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig.
Back-ported from commit f7e8adac7b3123 ("edk2-stable202005: Update
MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due
to enum macro redefinition.
BUG=b:260183604
TEST=Verify MTL Rex0 build with the patch
and verify the version output prints no junk data.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Update definitions on glinda used by birman.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I03065011581489b5345c16e225edc341e1d7811c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update definitions to match morgana FSP.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update header files for FSP for Meteor Lake platform to
version 2404_00, previous version being 2364_00.
FSPM:
1. Address offset changes
2. Rename `PlatformDebugConsent` to `PlatformDebugOption`
FSPS:
1. Address offset changes
Additionally, incorporate the UPD name change for MTL romstage.
BUG=b:255481471
TEST=Able to build and boot Google, Rex to ChromeOS.
Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Until now tcg-2.0/tss.c was just assuming certain buffer size and
hash algorithm. Change it to accept digest type, which the call sites
know.
Also drop `uint8_t *out_digest` parameter which was always `NULL`
and was handled only by tcg-1.2 code.
Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68745
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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|
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The FSPM and FSPS UPD signatures hadn't been updated from their cezanne
origins. Change them to MNDCNO_M/S.
BUG=b:240573135
TEST=Build & boot, see new signature in boot log.
Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.
Re-define in the common code.
Update coreboot code to use FSP_X_CONFIG consistently.
Tested=On OCP Delta Lake, boot up OS successfully.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The headers added are generated as per FSP v3361.07
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:254054169
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is now unused by any platform.
Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Now that all agesa CPUs are removed this code is unused.
Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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No platform uses this.
Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69127
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: Ie2ef5424c3ebe75ff98361639a0f9980101c1141
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69126
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I749cf33fad12bb9bc5cd5d682df2652107d60a0f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69125
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Copied from Morgana - Needs to be updated.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3175e6e6b5c7210b7c29f30e21e5a66f234c52a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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We still had a lingering reference to the old sabrina codename in the
vendorcode directory. Searching through the code now, the only places
the sabrina codename is seen is in the release notes, as is proper.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04.
Changes include:
- FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD
BUG=b:254374913
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.
Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424
Reviewed-by: Reka Norman <rekanorman@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add two new types for MDN DDI descriptor
BUG=b:228284940
TEST=Normal boot and S0i3 cycles
Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
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This README.md file specifies the expectations and agreements implied by
contributing code to the coreboot src/vendorcode directory.
Licenses, structure, formatting and the like are all the responsibility
of the contributors, however as the code is a part of the coreboot
codebase, members of the coreboot community are allowed to modify the
code to the extent deemed necessary.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7e2aedce9383158d03be342cb10ae18d85146ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update header files for FSP for Meteor Lake platform to
version 2364_00, previous version being 2344_00.
FSPM:
1. Address offset changes
FSPS:
1. Address offset changes
BUG=b:251733481
TEST=emerge-rex intel-mtlfsp
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8e4f62890b812f68dffe215e51c433510fca018f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Initial commit of the FSP-specific code for the Morgana SoC.
This is just an initial framework and still needs to be updated
to match the Morgana FSP.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The common directory is for files that shouldn't change, or shouldn't
change much between platforms.
These will be removed from other directories and used in upcoming
commits.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The headers added are generated as per FSP v3361.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:247855492
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: I267a0aefca18492bcbcfbf7acbe271887f0a39cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Add new PSP svc call to pass psp firmware hash table to the PSP.
psp_verstage will verify hash table and then pass them to the PSP.
The PSP will check if signed firmware contents match these hashes.
This will prevent anyone replacing signed firmware in the RW region.
BUG=b:203597980
TEST=Build and boot to OS in Skyrim.
Change-Id: I512d359967eae925098973e90250111d6f59dd39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update header files for FSP for Meteor Lake platform to
version 2344_00, previous version being 2304_01.
FSPM:
1. Address offset changes
FSPS:
1. Deprecated CstateLatencyControlTimeUnit UPDs
2. Deprecated HybridStorageMode
3.Address offset changes
BUG=b:245167089
TEST=emerge-rex intel-mtlfsp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Iaee5c66811c340d12921ff9247461df36de4739a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update generated FSP headers for Alder Lake N from v3267.01 to v3301.00.
Changes include:
- FspsUpd.h: 1. Add VccInAuxImonSlope UPD
2. Update UPD Offset in FspsUpd.h
BUG=b:242152105
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa.
Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.
Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:
Updating from commit id 18cb85b5:
2load_kernel.c: Expose load kernel as vb2_api
to commit id b827ddb9:
tests: Ensure auxfw sync runs after EC sync
This brings in 15 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Add the headers for 2.2.3.1, which includes the following changes
over 2.2.0.0:
• [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry
failure in less than 5 cycles when a USB2 Ethernet Dongle is
connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter
7.20.6 for new Register settings.
• [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini
Lake/Gemini Lake – R
• [Update] MRC new version update to 1.38.
• [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from
S4 issue with latest Wifi driver.
[Update] MRC new version update to 1.39. Included fix for
MinRefRate2xEnable and support for Rowhammer mitigation.
• [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This
change specific to DDR4 memory configuration.
• GLK Klocwork Fix
• [Update] MRC new version update to 1.40.
Added in a separate directory as the default. The 2.2.0.0 headers
were left and will be used for Google boards, as some offsets have
moved.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The headers added are generated as per FSP v3301.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:243693364
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01.
Changes include:
- Add UPD Lp5BankMode
- Update UPD Offset in FspmUpd.h
BUG=b:240373012
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event
logging types as below:
* ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason
while booting into recovery mode
* ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into
developer mode.
* ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into
diagnostic mode.
Drop static structure `cros_deprecated_recovery_reasons` as it has been
replaced by vb2_get_recovery_reason_string() function.
ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those
related fw boot info along with ChromeOS boot mode/reason etc.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I932952ce32337e2d54473667ce17582a90882da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update header files for FSP for Meteor Lake platform to
version 2304_01, previous version being 2253_00.
FSPM:
1. Removed CpuCrashLogDevice
2. Address offset changes
FSPS:
Includes below new UPDs
1. VpuEnable
2. SerialIoI3cMode
3. ThcAssignment
4. PchIshI3cEnable
BUG=b:240665069
TEST=emerge-rex intel-mtlfsp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9740e5877af745124d573425da623e814d8df5d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve
FW slot boot information like (tries count, current boot slot, previous
boot slot, previous boot status and boot mode).
Upon retrieval of the vboot information, elog callback from ramstage
records the info into the eventlog.
Additionally, this patch refactors the existing event logging mechanism
to add newer APIs to record vboot firmware boot related information.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS and run below command to
check the cbmem log:
Scenario 1:
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot:
0x0 / 0x0
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot`
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Success`.
....
Scenario 2:
localhost ~ # crossystem recovery_request=1
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot`
VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Unknown`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sabrina"
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Fix the license in header file.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I025f7c571d09e4cc63a659279e63d17c098c01cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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From comments of CB:65875, we replace *_vol to *_voltage.
s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/
s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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SoC FW ID needs to be populated at offset 0x58 and 0x59 in the PSP
header.
BUG=b:217414563
TEST=Build Skyrim BIOS image and ensure that PSP verstage is getting
loaded.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibe7b26aea0567e5337ee3e6e9447aa3944c55f5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The headers added are generated as per FSP v3257_00_40.
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:238791453
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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This patch fixes a missing header file compilation issue when coreboot
selects MP_SERVICES_PPI_V2 config from MTL SoC.
The `MpServices2.h` file doesn't exist in the upstreamed EDK2 repo
(integrated with `edk2-stable202111` stable tag).
Currently MpServices2.h file is being copied from the
`edk2_stable202005` stable tag.
BUG=b:237960384 ([Intel FSP][EDK2011] MpServices2.h header is missing
in upstream EDKII git)
TEST=Able to fix the compilation issue on Google/Rex (Meteor Lake)
when MP_SERVICES_PPI_V2 kconfig is enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib7c406ff51439c93c6d15f3a69808b4d1590cfa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65624
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update partial headers to MeteorLake FSP v2253.00
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: If2d6c80bd35afd68588fef57e38064c5b1e1a888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here.
BUG=b:218709292
TEST=Set serial soft fuse, boot to kernel, check logs
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
This patch adds below UPDs into the existing FSP partial header v2222.1
FSP-M UPD:
DisableMc0Ch0
DisableMc0Ch1
DisableMc0Ch2
DisableMc0Ch3
DisableMc1Ch0
DisableMc1Ch1
DisableMc1Ch2
DisableMc1Ch3
DdrFreqLimit
GpioOverride
SerialIoUartDebugMode
SerialDebugMrcLevel
SmbusDynamicPowerGating
WdtDisableAndLock
SaIpuEnable
SkipCpuReplacementCheck
TcssDma0En
TcssDma1En
VtdBaseAddress
CpuCrashLogDevice
CpuCrashLogEnable
LCT
TdcEnable
TdcTimeWindow
Lp5CccConfig
RMTBIT
RmtPerTask
RMTLoopCount
MrcFastBoot
EnCmdRate
SaGvGear
TAT
PchHdaVcType
BdatTestType
RdEnergyMc0Ch0Dimm1
RdEnergyMc0Ch0Dimm0
CorePllVoltageOffset
RdEnergyMc1Ch1Dimm1
RdEnergyMc1Ch1Dimm0
DciEn
PchPort80Route
ActEnergyMc0Ch1Dimm1
ActEnergyMc0Ch1Dimm0
HeciCommunication2
PcdSerialDebugBaudRate
HeciTimeouts
ThrtCkeMinDefeatLpddr
PchPcieHsioRxSetCtle
BdatEnable
DisableCpuReplacedPolling
PchSataHsioRxGen1EqBoostMagEnable
CoreVoltageOffset
PchPcieHsioTxGen1DownscaleAmp
PchHdaDspUaaCompliance
VddVoltage
WRVC1D
PreBootDmaMask
tWR
RingVoltageAdaptive
PchSataHsioTxGen3DeEmphEnable
PchPcieHsioRxSetCtleEnable
RingPllVoltageOffset
OcSupport
WrEnergyMc0Ch0Dimm1
PdEnergyMc1Ch1Dimm1
PdEnergyMc1Ch1Dimm0
DmiGen3ProgramStaticEq
SmramMask
tRAS
PerCoreHtDisable
IdleEnergyMc1Ch0Dimm0
IdleEnergyMc1Ch0Dimm1
Gen3LtcoEnable
tWTR
RCVET
DmiGen3UsPresetEnable
tCWL
PwdwnIdleCounter
WRTC1D
CLKTCO
PrimaryDisplay
DisableMessageCheck
tFAW
PchSataHsioTxGen2DeEmphEnable
SerialIoUartDebugRtsPinMux
GtExtraTurboVoltage
TXTCO
PchSataHsioTxGen3DownscaleAmp
CpuRatioOverride
PostCodeOutputPort
DmiHweq
CoreVfPointCount
NModeSupport
Ddr4DdpSharedZq
RdEnergyMc1Ch0Dimm0
RdEnergyMc1Ch0Dimm1
PchSataHsioTxGen2DownscaleAmp
DebugInterfaceEnable
WrEnergyMc0Ch1Dimm0
WrEnergyMc0Ch1Dimm1
SaPllVoltageOffset
DmiGen3EndPointPreset
PchSataHsioRxGen2EqBoostMag
VDDQT
PvdRatioThreshold
CoreVfPointOffsetMode
DmiGen3DsPortRxPreset
BclkRfiFreq
SmbusArpEnable
PowerDownMode
DebugInterfaceLockEnable
RingVoltageOffset
EnableExtts
SerialIoUartDebugCtsPinMux
PchPcieHsioTxGen2DownscaleAmpEnable
Avx2VoltageScaleFactor
GearRatio
GtVoltageOverride
EccSupport
RingMaxOcRatio
TrainTrace
EnablePwrDn
IsTPMPresence
OcLock
DmaBufferSize
SOT
CoreVfPointRatio
PchPcieHsioTxGen2DownscaleAmp
TjMaxOffset
CoreMaxOcRatio
RingDownBin
PchSataHsioRxGen1EqBoostMag
BiosAcmSize
tRFC
PchPcieHsioTxGen1DownscaleAmpEnable
PdEnergyMc0Ch1Dimm0
PdEnergyMc0Ch1Dimm1
RDMPRT
TxtLcpPdBase
CMDVC
SerialIoUartDebugBaudRate
PchTraceHubMemReg1Size
CoreVoltageOverride
McPllVoltageOffset
PdEnergyMc1Ch0Dimm0
PdEnergyMc1Ch0Dimm1
GttMmAdr
PchPcieHsioTxGen1DeEmphEnable
ApStartupBase
CoreVoltageAdaptive
GtVoltageMode
PcieImrRpSelection
TxtLcpPdSize
PchPcieHsioTxGen2DeEmph3p5
ThrtCkeMinTmr
RealtimeMemoryTiming
UserBudgetEnable
PchPcieHsioTxGen3DownscaleAmpEnable
GmAdr
PchSataHsioTxGen1DeEmphEnable
CrashLogGprs
tRTP
RMC
PchSataHsioTxGen3DownscaleAmpEnable
RDODTT
RDVREFDC
PerCoreRatio
IdleEnergyMc0Ch1Dimm1
tRCDtRP
DidInitStat
SerialIoUartDebugRxPinMux
SerialIoUartDebugMmioBase
BiosSize
MmioSizeAdjustment
PchTraceHubMode
DmiGen3Ltcpre
CoreVoltageMode
DmiGen3UsPortTxPreset
Gen3EqPhase3Bypass
BclkSource
KtDeviceEnable
DciUsb3TypecUfpDbg
CoreVfPointOffset
Gen3RtcoRtpoEnable
TotalFlashSize
BclkAdaptiveVoltage
TvbRatioClipping
EnablePwrDnLpddr
WRTC2D
RankInterleave
PchSataHsioRxGen3EqBoostMag
IdleEnergyMc0Ch0Dimm1
IdleEnergyMc0Ch0Dimm0
Ratio
JWRL
Avx3RatioOffset
Avx2RatioOffset
RDVC1D
DCC
PchSataHsioTxGen2DeEmph
ExitOnFailure
IdleEnergyMc1Ch1Dimm1
IdleEnergyMc1Ch1Dimm0
RingVoltageOverride
SpdProfileSelected
ScramblerSupport
SaGvFreq
WRVC2D
DmiGen3EqPh3Method
CMDSR
RdEnergyMc0Ch1Dimm0
RdEnergyMc0Ch1Dimm1
UserThresholdEnable
ThrtCkeMinDefeat
DmiGen3EqPh2Enable
tRRD
ChHashEnable
BistOnReset
ChHashInterleaveBit
RemapEnable
RDVC2D
DIMMRONT
WrEnergyMc0Ch0Dimm0
DmiAspm
PchPcieHsioTxGen2DeEmph6p0Enable
PchSataHsioTxGen1DeEmph
RDEQT
TxtDprMemoryBase
WrEnergyMc1Ch0Dimm1
WrEnergyMc1Ch0Dimm0
DmiGen3EndPointHint
CleanMemory
PchSmbAlertEnable
SaOcSupport
PchSataHsioTxGen3DeEmph
TxtImplemented
CoreVfPointOffsetPrefix
PchHdaTestPowerClockGating
DmaControlGuarantee
DIMMODTT
ERDMPRTC2D
RootPortIndex
SkipStopPbet
VtdIopEnable
DmiGen3DsPortTxPreset
ActiveCoreCount
PchLpcEnhancePort8xhDecoding
GtVoltageOffset
DisPgCloseIdleTimeout
ActEnergyMc1Ch0Dimm1
ActEnergyMc1Ch0Dimm0
Idd3n
Idd3p
PchSataHsioTxGen1DownscaleAmpEnable
BClkFrequency
ActEnergyMc0Ch0Dimm0
ActEnergyMc0Ch0Dimm1
DdrFreqLimit
Gen3EqPhase23Bypass
WrEnergyMc1Ch1Dimm0
DmiGen3DsPresetEnable
PcieImrSize
EWRTC2D
IbeccOperationMode
VtdBaseAddress
TvbVoltageOptimization
DciDbcMode
HobBufferSize
PchHdaSdiEnable
PcieImrEnabled
IdleEnergyMc0Ch1Dimm0
SerialIoUartDebugAutoFlow
tCL
PdEnergyMc0Ch0Dimm1
PdEnergyMc0Ch0Dimm0
RDTC2D
ERDTC2D
SerialIoUartDebugParity
PchPcieHsioTxGen2DeEmph3p5Enable
PchPcieHsioTxGen1DeEmph
DmiGen3Ltcpo
PchSmbusIoBase
RaplPwrFlCh1
RaplPwrFlCh0
EnhancedInterleave
PchPcieHsioTxGen2DeEmph6p0
MemTestOnWarmBoot
Ibecc
PanelPowerEnable
BiosAcmBase
DmiGen3UsPortRxPreset
DmiAspmL1ExitLatency
CmdMirror
PchSataHsioTxGen2DownscaleAmpEnable
tREFI
CpuBclkOcFrequency
CridEnable
EpgEnable
SmbusSpdWriteDisable
DdrSpeedControl
PchSataHsioRxGen2EqBoostMagEnable
GtMaxOcRatio
DmiMaxLinkSpeed
PchSataHsioRxGen3EqBoostMagEnable
PcieImrRpLocation
CmdRanksTerminated
SkipMbpHob
SerialIoUartDebugTxPinMux
PchSataHsioTxGen1DownscaleAmp
PchPcieHsioTxGen3DownscaleAmp
PerCoreRatioOverride
PchHdaAudioLinkDmicClockSelect
SerialIoUartDebugDataBits
SrefCfgEna
Avx512VoltageScaleFactor
MmioSize
SaVoltageOffset
SaIpuEnable
ActEnergyMc1Ch1Dimm0
ActEnergyMc1Ch1Dimm1
ProbelessTrace
VtdIgdEnable
ALIASCHK
PchTraceHubMemReg0Size
DIMMODTCA
TgaSize
EWRDSEQ
SerialIoUartDebugStopBits
RDTC1D
CMDNORM
RingVoltageMode
EnableAbove4GBMmio
WrEnergyMc1Ch1Dimm1
Txt
PcieMultipleSegmentEnabled
CnviDdrRfim
FSP-S UPD:
CpuMpPpi
LidStatus
ITbtConnectTopologyTimeoutInMs
D3HotEnable
D3ColdEnable
PchLockDownGlobalSmi
PchLockDownBiosInterface
PchUnlockGpioPads
RtcMemoryLock
SkipPamLock
EndOfPostMessage
CpuUsb3OverCurrentPin
PcieRpHotPlug
SerialIoUartAutoFlow
TccActivationOffset
VmdEnable
Enable8254ClockGating
Enable8254ClockGatingOnS3
HybridStorageMode
PcieRpHotPlug
Hwp
Cx
PsOnEnable
EnergyEfficientTurbo
PchPmDisableEnergyReport
UfsEnable
FspEventHandler
GnaEnable
VbtSize
PcieComplianceTestMode
CStatePreWake
SerialIoUartDataBits
SataPortsExternal
CstateLatencyControl0TimeUnit
SataP0Tinact
PmcV1p05PhyExtFetControlEn
ApIdleManner
SataPortsSpinUp
DisableProcHotOut
ITbtPcieTunnelingForUsb4
SerialIoUartDmaEnable
SaPcieItbtRpNonSnoopLatencyOverrideMode
SaPcieItbtRpSnoopLatencyOverrideMode
MlcSpatialPrefetcher
PchXhciOcLock
PmcPowerButtonDebounce
TccOffsetClamp
LogoPixelWidth
AvxDisable
Custom1PowerLimit1
Custom1PowerLimit2
PmcCpuC10GatePinEnable
PchPmSlpStrchSusUp
IshI2cSdaPadTermination
Custom2PowerLimit1Time
RtcBiosInterfaceLock
WatchDogTimerBios
SataP1TDisp
PchPciePort8xhDecodePortIndex
PcieRpImrSelection
TcCstateLimit
PchS0ixAutoDemotion
PchFivrExtV1p05RailEnabledStates
PcieRpSlotPowerLimitScale
IshUartCtsPinMuxing
PcieRpSnoopLatencyOverrideMode
TTCrossThrottling
PsysPowerLimit1
SataRstInterrupt
IshSpiClkPadTermination
PcieEnablePeerMemoryWrite
SataP1T2M
ChipsetInitBinPtr
LogoPixelHeight
PsysPowerLimit1Time
HwpInterruptControl
DevIntConfigPtr
IshUartRtsPadTermination
PsysPowerLimit1Power
EnergyEfficientTurbo
Custom3TurboActivationRatio
PcieDpc
TurboMode
PchFivrExtVnnRailSupportedVoltageStates
ITbtDmaLtr
IshSpiClkPinMuxing
PchSbAccessUnlock
PcieRpSystemErrorOnCorrectableError
PcieRpSlotPowerLimitValue
SendEcCmd
SataSpeedLimit
SataRstPcieEnable
PchUsb3HsioCtrlAdaptOffsetCfg
SataP0T2M
PchHdaVerbTableEntryNum
DmiTS1TW
DmiTS2TW
PcieRpImrEnabled
GpioIrqRoute
SataPortsSolidStateDrive
RaceToHalt
PcieRpNonSnoopLatencyOverrideMultiplier
PcieRpUnsupportedRequestReport
AesEnable
PchFivrExtVnnRailSxVoltage
SataP1Tinact
PkgCStateUnDemotion
SataPortsZpOdd
PchSerialIoI2cPadsTermination
PchFivrExtV1p05RailSupportedVoltageStates
PchUsbLtrLowIdleTimeOverride
IshSpiMosiPinMuxing
PchProtectedRangeLimit
SaPcieItbtRpNonSnoopLatencyOverrideValue
SataP1T3M
PchPmWoWlanEnable
IshUartRtsPinMuxing
SataLedEnable
VmdGlobalMapping
PcieRpEnableCpm
IshGpGpioPadTermination
PchDmiCwbEnable
ForcMebxSyncUp
FspEventHandler
PchFivrExtVnnRailIccMax
PchPmMeWakeSts
DisableD0I3SettingForHeci
PcieRpNonSnoopLatencyOverrideMode
PmgCstCfgCtrlLock
PchUsbLtrHighIdleTimeOverride
Usb3HsioTxRate2UniqTran
SiNumberOfSsidTableEntry
IshSpiMisoPadTermination
IshUartRxPadTermination
PcieRpSlotImplemented
PchUsbOverCurrentEnable
EndOfPostMessage
SaPcieItbtRpSnoopLatencyOverrideValue
EnableHwpAutoEppGrouping
SerialIoUartDbg2
ConfigTdpLock
EsataSpeedLimit
PchTsnEnable
PowerLimit3DutyCycle
TTSuggestedSetting
PchEnableDbcObs
IehMode
VmdPort
PchFivrExtVnnRailCtrlRampTmr
PchPmSlpAMinAssert
CstateLatencyControl5TimeUnit
ProcessorTraceEnable
ChipsetInitBinLen
PchTemperatureHotLevel
Usb3HsioTxRate3UniqTranEnable
NumberOfEntries
Custom2ConfigTdpControl
PowerLimit3Lock
SiCustomizedSsid
PchUsb3HsioFilterSelP
DisableVrThermalAlert
PchIoApicEntry24_119
SmbiosType4MaxSpeedOverride
PowerLimit3Time
C1StateUnDemotion
PchDmiAspmCtrl
PchUsb3HsioFilterSelN
PchTTEnable
PcieRpNoFatalErrorReport
Custom1ConfigTdpControl
PmcC10DynamicThresholdAdjustment
PchFivrVccinAuxRetToLowCurModeVolTranTime
BiProcHot
VmdPortFunc
PchUsb3HsioFilterSelNEnable
PchHdaVerbTablePtr
TurboPowerLimitLock
PcieRpSystemErrorOnNonFatalError
PmcUsb2PhySusPgEnable
PcieRpSystemErrorOnFatalError
PchProtectedRangeBase
VccSt
PchFivrExtVnnRailSxEnabledStates
EnableHwpAutoPerCorePstate
CstateLatencyControl1TimeUnit
SaPcieItbtRpSnoopLatencyOverrideMultiplier
PchPmSlpS4MinAssert
PcieRpTransmitterHalfSwing
Usb3HsioTxRate3UniqTran
RenderStandby
ProcessorTraceOutputScheme
SkipFspGop
PchHdaPme
EcCmdProvisionEav
BgpdtHash
Usb3HsioTxRate0UniqTran
UsbOverride
PkgCStateDemotion
EnableAllThermalFunctions
PchPmWolEnableOverride
IshSpiCsPinMuxing
PchIshSpiCsEnable
IshUartCtsPadTermination
PmcV1p05IsExtFetControlEn
MaxRingRatioLimit
PchIshPdtUnlock
IshUartTxPinMuxing
PchFivrExtV1p05RailIccMax
BiosGuardAttr
LogoPtr
CpuBistData
ShowSpiController
PchPmWolOvrWkSts
SataP0T1M
CstCfgCtrIoMwaitRedirection
TcoIrqEnable
PchHdaLinkFrequency
ITbtForcePowerOnTimeoutInMs
SerialIoSpiCsEnable
VmdMemBar2Base
TStates
SiSkipSsidProgramming
TccOffsetTimeWindowForRatl
AmtSolEnabled
PchUsb3HsioCtrlAdaptOffsetCfgEnable
PchFivrExtVnnRailIccMaximum
PchEspiLgmrEnable
SkipPamLock
IshGpGpioPinMuxing
PchUsb3HsioFilterSelPEnable
PchFivrExtVnnRailVoltage
SataPortsDevSlpResetConfig
ProcHotLock
PchDmiTsawEn
SerialIoSpiCsPolarity
PkgCStateLimit
EnableRsr
PmcDbgMsgEn
PchPmPwrCycDur
NumOfDevIntConfig
SerialIoSpiDefaultCsOutput
PchPmPciePllSsc
PxRcConfig
CstateLatencyControl4TimeUnit
PcieRpPmSci
ConfigTdpBios
PmcPdEnable
PchT1Level
PmcModPhySusPgEnable
DisableTurboGt
EnableTcoTimer
IshSpiMisoPinMuxing
IshI2cSclPinMuxing
PcieRpCorrectableErrorReport
C1StateAutoDemotion
PchEspiLockLinkConfiguration
PchFivrExtV1p05RailCtrlRampTmr
SataRstPcieStoragePort
PchFivrExtV1p05RailVoltage
PchPmSlpSusMinAssert
PchHotEnable
PcieRpNonSnoopLatencyOverrideValue
TcoIrqSelect
PcieRpCompletionTimeout
FwProgress
StateRatioMax16
ConfigTdpLevel
IshI2cSdaPinMuxing
PcieRpPhysicalSlotNumber
SerialIoUartParity
TxtEnable
PchLegacyIoLowLatency
PchUsbLtrMediumIdleTimeOverride
PchPmPmeB0S5Dis
SerialIoUartPowerGating
PcieRpSnoopLatencyOverrideValue
PchPmSlpLanLowDc
PchT2Level
CstateLatencyControl2TimeUnit
PchPmSlpS3MinAssert
PchUsb3HsioOlfpsCfgPullUpDwnResEnable
MonitorMwaitEnable
Usb3HsioTxRate1UniqTran
Eist
IshSpiMosiPadTermination
PowerLimit4Lock
Custom3PowerLimit1Time
PcieEnablePort8xhDecode
DualTauBoost
WatchDogEnabled
MaxRatio
Custom2TurboActivationRatio
PchFivrExtVnnRailEnabledStates
ApplyConfigTdp
IshI2cSclPadTermination
PowerLimit2Power
ThermalMonitor
CpuUsb3OverCurrentPin
PchTTLock
Custom1PowerLimit1Time
PchEspiHostC10ReportEnable
Usb3HsioTxRate2UniqTranEnable
SataPortsInterlockSw
EnablePerCorePState
PsysPowerLimit2Power
UfsEnable
PchPmDisableNativePowerButton
VmdVariablePtr
Custom3PowerLimit2
PchPmDisableEnergyReport
Custom3PowerLimit1
DmiTS3TW
EnforceEDebugMode
CstateLatencyControl3TimeUnit
VmdCfgBarBase
DmiSuggestedSetting
SataPortsEnableDitoConfig
SerialIoUartBaudRate
Usb3HsioTxRate1UniqTranEnable
SataPortsHotPlug
MachineCheckEnable
Custom1TurboActivationRatio
Custom2PowerLimit1
Custom2PowerLimit2
VmdMemBar1Base
SaPcieItbtRpLtrConfigLock
SataP0TDispFinit
PchFivrExtVnnRailSxIccMaximum
PchTsnLinkSpeed
SataThermalSuggestedSetting
SaPcieItbtRpLtrEnable
TimedMwait
PchTsnMultiVcEnable
PcieRpFunctionSwap
PcieEqOverrideDefault
SataP1T1M
PsysPowerLimit2
PchLanLtrEnable
SerialIoUartStopBits
SciIrqSelect
C1e
PchFivrExtVnnRailSxIccMax
PowerLimit3
PowerLimit2
PowerLimit1
MeUnconfigOnRtcClear
PcieRpPcieSpeed
PchUsbLtrOverrideEnable
UsbPdoProgramming
Custom3ConfigTdpControl
SataP1TDispFinit
PchFivrDynPm
VmdPortDev
EnableItbm
MinRingRatioLimit
PcieRpFatalErrorReport
MctpBroadcastCycle
EcCmdLock
StateRatio
PchPmVrAlert
DmiTS0TW
LogoSize
PchIoApicId
SaPcieItbtRpForceLtrOverride
PcieRpSnoopLatencyOverrideMultiplier
IshUartTxPadTermination
PchCrid
SataRstPcieDeviceResetDelay
ProcHotResponse
BltBufferSize
MlcStreamerPrefetcher
PcieRpLtrConfigLock
SiSsidTablePtr
SataP0TDisp
PchUsb3HsioOlfpsCfgPullUpDwnRes
BltBufferAddress
PcieRpDetectTimeoutMs
PpinSupport
SataRstRaidDeviceId
PchPmLatchEventsC10Exit
IshUartRxPinMuxing
PpmIrmSetting
EnergyEfficientPState
PchFivrExtV1p05RailIccMaximum
PortResetMessageEnable
PchReadProtectionEnable
BiosGuardModulePtr
PchWriteProtectionEnable
AmtEnabled
PchHdaCodecSxWakeCapability
SiCustomizedSvid
PcieEdpc
TccOffsetLock
PchPmPwrBtnOverridePeriod
SaPcieItbtRpNonSnoopLatencyOverrideMultiplier
WatchDogTimerOs
PchTTState13Enable
PowerLimit1Time
PchT0Level
IshSpiCsPadTermination
SataP0T3M
Usb3HsioTxRate0UniqTranEnable
SataTestMode
PmcOsIdleEnable
PowerLimit4
PcieRpAcsEnabled
PavpEnable
UsbTcPortEn
Additionally, optimize the `reserved` fields across header files.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I976a5762701711fbf000c43c5ff05f9bd93f688f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00.
FSPM:
Includes below 2 UPDs
1. TdcEnable
2. TdcTimeWindow
FSPS:
Address Offset changes.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Add header files generated from FSP 2173_00 source build for Meteor Lake platform.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Do not discard the const qualifier in `GnbRegisterWriteTNDump()` to fix
the compiler warning below.
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.o
In file included from src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:53:
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: In function 'GnbRegisterWriteTN':
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:836:57: error: passing argument 3 of 'GnbRegisterWriteTNDump' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
836 | GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
| ^~~~~
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h:68:35: note: in definition of macro 'GNB_DEBUG_CODE'
68 | #define GNB_DEBUG_CODE(Code) Code
| ^~~~
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:86:33: note: expected 'VOID *' {aka 'void *'} but argument is of type 'const VOID *' {aka 'const void *'}
86 | IN VOID *Value
| ~~~~~~~~~~~~~~~~~~~~~^~~~~
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.o
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: At top level:
cc1: note: unrecognized command-line option '-Wno-pragma-pack' may have been intended to silence earlier diagnostics
cc1: all warnings being treated as errors
Found-by: gcc (Debian 11.3.0-3) 11.3.0
Change-Id: I2039cf66030030458bd247a31adc0621b9d033e6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The headers added are generated as per FSP v3172
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I5aa0611b19bb4f6667a95d2539cc2d17de6dcf07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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