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2024-11-27drivers/wifi: Support Bluetooth BiQuad Bypass FilterJeremy Compostella
This feature provides ability to identify non-LTE platform and disable BiQuad Bypass filter logic in hardware for Bluetooth usecases reducing device power consumption. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BBFB method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e213 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-27drivers/wifi: Support Bluetooth Per-Platform Antenna GainJeremy Compostella
The ACPI BPAG method provide information to controls the antenna gain method to be used per country. The antenna gain mode is a bit field (0 - disabled, 1 -enabled) defined as follow: - Bit 0 - Antenna gain in EU - Bit 1 - Antenna gain in China Mainland The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BPAG method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e210 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-21vc/google/chromeos/sar: Use size_t instead of int for size functionJeremy Compostella
BUG=b:346600091 TEST=Compilation successful Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e225 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-18vendorcode/intel/fsp/skx_sp: Fix PCI domain scanningPatrick Rudolph
Properly scan all logical stack when creating PCI domains. Fixes PCI bus ranges being used on other stacks, since they look unused, as not all stacks are checked. Change-Id: I13c8b389a585dbccec182d3c98021f1d9d648b2c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-13vc/google: Refactor config to set Fn key scancodeKapil Porwal
Create a new config option to indicate that a board has Google Strauss keyboard. The scan code for Fn key will be set to 94 if the new config is selected. Previously each board was setting the integer config option for Fn key scan code which was not scalable. The new option is a bool and can be easily selected by different boards. BUG=none TEST=Verify coreboot.config before and after this change. Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h headerRonak Kanabar
This patch is to add FspProducerDataHeader.h header file to support MRC version Info in RPL. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06vendorcode/intel: Add edk2-stable202305 supportRonak Kanabar
Add edk2-stable202305 support for MTL and RPL FSPs. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202305 https://github.com/tianocore/edk2.git commit hash: ba91d0292e593df8528b66f99c1b0b14fadc8e16 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add following fixes from older Edk2 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements cf4c6fd225 Remove FSPM_ARCH_UPD config guard dc781d3a83 Define FSP_SIG macro for FSP 2.x compatibility d045074b91 Remove wchar_t asserts Change-Id: I96f0d0e393d31b325f9e42e3494556a2f6e1228e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-07vc/amd/opensil/genoa_poc: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I83c3e5db85b98196c465146ba8e3481041d2f7eb Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84589 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-28vc/intel/fsp: Update PTL FSP headers from dummy headers to v2382_01Ronak Kanabar
Update generated FSP headers for Panther Lake from v2382_01 Changes include: - Update FspmUpd.h, FspsUpd.h, MemInfoHob.h and FirmwareVersionInfo.h BUG=b:348678529 TEST=Able to build google/fatcat Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2020 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-26vc/intel/fsp/fsp2_0/graniterapids: Update to formal FSP header filesJincheng Li
Change-Id: I6e94f44d50f2b53855adc1bb1cd6a1a5d9929003 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-09-25vc/amd/opensil: Move openSIL interface declarations to common headerNicolas Kochlowski
The declarations describing interface functions between SoCs and openSIL glue code are common for the stub and Genoa POC, and likely with future SoC openSIL implementations. Therefore, move these out of SoC-specific header files and into vc/amd/opensil/opensil.h. This change facilitates swapping out the stub for the actual openSIL glue code. Change-Id: Icc8783ddb868f9f0c4cd357245604313eadfe531 Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84428 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13vc/intel/fsp/fsp2_0/graniterapids: Update FSP headersJincheng Li
FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to pass compilation with full platform codes. Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-06vc/google/chromeos: Skip boot info logging if cse sync at payloadDinesh Gehlot
This patch skips event logging for current boot information at ramstage if CSE sync is scheduled at payload. Given that CSE sync could initiate a system reset, resulting in redundant boot information logs, the payload should handle the logging of boot information following CSE sync. BUG=b:360082747 TEST=Verified elog boot info is not logged at ramstage Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84120 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-26vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00KunYi Chen
Update generated FSP headers for ADL-N to MR5(5132_00) Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7 Signed-off-by: KunYi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-22soc/intel/jasperlake: Add CrashLog implementation for Intel JSLJędrzej Ciupis
Extend support for CrashLog to Intel Jasperlake based platforms. This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7, originally reviewed on https://review.coreboot.org/c/coreboot/+/49943. BUG=b:354834461 TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms and can generate a BERT table, if enabled. Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-19vc/wuffs: upgrade to Wuffs 0.4.0-alpha.8Nigel Tao
We were previously at Wuffs 0.4.0-alpha.2. The C file was copied from https://github.com/google/wuffs-mirror-release-c and its hash matches https://github.com/google/wuffs-mirror-release-c/blob/90e4d81a6a8b7b601e8e568da32a105d7f7705e5/sync.txt#L9-L10 $ sha256sum src/vendorcode/wuffs/wuffs-v0.4.c 6c22caff4af929112601379a73f72461bc4719a5215366bcc90d599cbc442bb6 src/vendorcode/wuffs/wuffs-v0.4.c Change-Id: Ie90d989384e0db2b23d7d1b3d9a57920ac8a95a2 Signed-off-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83894 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13vc/google/chromeos: Enable eSOL config with libgfx and uGOPJayvik Desai
This patch introduces a new early sign-of-life config option when libgfx or uGOP is enabled for early graphics initialization. BUG=b:352651132 TEST=Able to build google/rex and google/tivviks Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950 Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83705 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compileSaurabh Mishra
Details: - Skeleton files to compile google/fatcat mainboard. BUG=b:348678529 TEST=Build verified on with using PTL SOC and google/fatcat mainboard. Change-Id: I4c069ba64f487259ce746dc52296618d91209602 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83732 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-09vc/intel/raptorlake: Update header files from 4435_00 to 5045_00Kulkarni, Srinivas
Update header files for FSP for Raptor Lake refresh platform to version 5045_00, previous version being 4435_00. FSPM: 1. Add IgdGsm2Size UPD 2. Comment added for Offset 0x0AB6 FSPS: 1. Add CepEnable UPD 2. Offset size updated for UPD ReservedCpuPostMemProduction 2. Comment added for Offset 0x104C MemInfoHob: 1. Structure updated BUG=b:355384183 Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/ software-kits/kit-details.html?kitId=815173 Cq-Depend: chrome-internal:7554984 Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-06vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoCChen, Yuchi
Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83192 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-31device: introduce and use dev_get_domain_idFelix Held
To avoid having constructs like 'dev->path.domain.domain' in the SoC code, create the 'dev_get_domain_id' helper function that returns the domain ID of either that device if it's a domain device or the corresponding domain device's domain ID, and use it in the code. If this function is called with a device other than PCI or domain type, it won't have a domain number. In order to not need to call 'die', 'dev_get_domain_id' will print an error and return 0 which is a valid domain number. In that case, the calling code should be fixed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27vc/intel/fsp/twinlake: Update FSP headers to v5222.01Varun Upadhyay
- Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:354612775 TEST=Able to build and boot google/Tivviks Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22vc/google/chromeos: Add configurable compression for logo file in cbfsAshish Kumar Mishra
This patch enables LZMA or LZ4 compression algorithm for the logo cbfs file based on BMP_LOGO_COMPRESS_LZMA or BMP_LOGO_COMPRESS_LZ4 Kconfig. Logo cbfs file is compressed based on CBFS_COMPRESS_FLAG, by default. Based on logo file content and target platform, enabling LZ4 could save significant boot time, with increase in file size. For brox: cb_logo LZ4 is +1265 bytes than LZMA, saves ~0.760ms in decomp. cb_plus_logo LZ4 is +2011 bytes than LZMA, saves ~0.880ms in decomp. BUG=b:337330958 TEST=Able to boot brox and verified firmware splash screen display with LZMA and LZ4 compression. Change-Id: I57fbd0d3a39eaba3fb9d61e7a3fb5eeb44e3a839 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83420 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support 320Mhz Bandwidth Enablement per MCCPoornima Tom
Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support Bluetooth Regulator Domain SettingsJeremy Compostella
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This commit introduces a `bluetooth_companion' field to the generic Wi-Fi drivers chip data. This field can be set in the board design device tree to supply the bluetooth device for which the BRDS function must be created. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17vc/amd/opensil/*/opensil.h: add missing device/device.h includeFelix Held
device/device.h provides the definition of struct device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c3c09665e3eedec6055f4a0586016c5a5537bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/83083 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00Ronak Kanabar
Update generated FSP headers for Alder Lake N from v5021.00 Changes include: - Add FspProducerDataHeader.h header file - Open Usb4CmMode & CnviWifiCore Upd in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:296433836 TEST=Able to build and boot google/nivviks Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82780 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-04Revert "vc/intel/fsp2/alderlake_n: Drop unused header files"Ronak Kanabar
This reverts commit 79503ef515967ffceab7bd2a16a381e6a02c3d30. The Intel FSP repository at https://github.com/intel/FSP.git currently lacks the Client ADL-N headers. The existing coreboot code references the "IoT/AlderLakeN/" directory for these headers, but it is missing the crucial FspProducerDataHeader.h file. Without this header, the ADL-N platform is unable to utilize the appropriate MRC version needed for updating MRC caches. This patch aims to restore the necessary FSP headers for the ADL-N platform within the vendorcode directory. Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-31vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guardAppukuttan V K
This commit removes config guard around FSPM_ARCH_UPD from the FspApi.h header file. This change is done to ensure that this header file can be used with both x86_32 and x86_64 architectures and also with different FSP specification versions. The following modifications are made: - Removes PLATFORM_USES_FSP2_X86_32 config guard around FSPM_ARCH_UPD, this was added to isolate the structure from x64 build. This is not really required since the x64 build uses FSP2.4 structures. BUG=b:343428206 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82425 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-30vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headersAppukuttan V K
This commit introduces new header files of V3471.91 for the x86_64 architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP 64-bits support and the soc Kconfig file has been updated to select this new header path when FSP2.4 is in use. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30vc/intel/fsp/mtl: Organize FSP headers into x86_32 directoryAppukuttan V K
This commit moves FSP V3471.91 header files for Meteor Lake into a new x86_32 directory to better organize the files based on the architecture. The Kconfig file has been modified accordingly to reflect the new paths of the relocated headers. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12vc/amd/opensil: introduce common mpio/chip.h header fileFelix Held
The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account. Thanks to Matt for pointing out how to make the path to the actual MPIO chip.h file configurable via a Kconfig setting. This allows overriding this path from site-local without the need to have any reference to site-local in the upstream code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12vc/amd/opensil/*/mpio/chip.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idef3b661b1cf3008373e61e0760a7dd3b9e9fede Reviewed-on: https://review.coreboot.org/c/coreboot/+/82261 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25vc/google/chromeos: Move RAMOOPS region creation to BS_DEV_INIT_CHIPSAnil Kumar
RAMOOPS memory region was being overwritten by coreboot bmp_load_logo() function. The CBMEM_ID_FSP_LOGO region created during bmp_load_logo() was overlapping with RAMOOPS space created earlier. This resulted in memory corruption of RAMOOPS buffer. To prevent this, the RAMOOPS region allocation is moved to BS_DEV_INIT_CHIPS phase from earlier BS_WRITE_TABLES phase of boot. BUG=b:332910298 TEST=build and boot coreboot image on google/rex HW. Check RAMOOPS CBMEM region creation using cbmem -l command Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82042 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-22vc/amd/opensil/stub/ramstage: add acpi_add_opensil_tables stubFelix Held
In the non-stub openSIL coreboot glue code, this can be used to add the ALIB SSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3ccd2e81211417ad4ac94f208572e0fa4e1cf97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82012 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04Makefile.mk: Also add -libs to bootblock when !SEPARATE_ROMSTAGEArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I18bf67cae7af90a92a030e552af6dc6b134a8357 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-04vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibilitySubrata Banik
This change refactors EDK2 essential header management within the FSP directory to ensure compatibility. Header selection is now dynamically based on: * FSP specification version: Distinguishes between 1.1 and 2.x * EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header FSP Header | |-> FSP 1.1 specification FSP_INFO_HEADER |-> FSP 2.0 specification EDK2 release |-> EDK2_2017 FSP_INFO_HEADER |-> EDK2_2020 FSP_INFO_HEADER |-> EDK2_2021 FSP_INFO_HEADER |-> EDK2_2023 FSP_INFO_HEADER Any .C/.H file requires to include FSP_INFO_HEADER can now just add the FSP header alone. BUG=b:242829490 TEST=Able to build google/rex0 with 64-bit FSP. Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81623 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04vc/intel/edk2: Define FSP_SIG macro for FSP 2.x compatibilitySubrata Banik
This patch introduces the FSP_SIG macro into EDK2 headers to ensure compilation compatibility when using FSP 2.x specifications. Previously, the macro was only defined for FSP 1.1. BUG=b:242829490 TEST=Successful build of google/rex0 with 64-bit FSP. Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-03vendorcode/amd/opensil: Add CPP args to all stagesArthur Heymans
It does not hurt to do this and makes it possible to link romstage sources into bootblock. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79576 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headersJincheng Li
GNR N-1 FSP headers are a set of stub headers used to fulfill build sanity check for GNR SoC and CRB codes before the formal FSP headers are published. The N-1 headers are forward compatible with the later formal headers. Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-28security/tpm: replace CONFIG(TPMx) checks with runtime checkSergii Dmytruk
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2 during compilation, in which case actual TPM family in use can be determined at runtime. In some places both compile-time and runtime checks are necessary. Yet in places like probe functions runtime state checks don't make sense as runtime state is defined by results of probing. Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28security/tpm: resolve conflicts in TSS implementationsSergii Dmytruk
No functional changes. Refactor code such that there won't be any compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled in. One might want to support both TPM families for example if TPM is pluggable, while currently one has to reflash firmware along with switching TPM device. Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-23soc/amd/genoa_poc/domain: refactor read_soc_memmap_resourcesFelix Held
To bring genoa_poc more in line with the other AMD SoCs, move the reporting of the memory map up to cbmem_top from the openSIL-specific add_opensil_memmap function to read_soc_memmap_resources. This is a preparation for making this code common for all newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22vc/amd/opensil/genoa_poc/mpio: add debug output for unused chipFelix Held
Print that the MPIO chip of one of the MPIO-related PCI device functions is unused and is skipped, if the type is IFTYPE_UNUSED and the corresponding PCI device function isn't enabled. This allows to differentiate between this case and the case where the type isn't IFTYPE_UNUSED. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4fc28d39a229494b487b300b28f92bf3adad66f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22vc/amd/opensil/genoa_poc/mpio: fix unused MPIO chip warningFelix Held
When the chip of one of the MPIO-related PCI device functions has the type IFTYPE_UNUSED, there is no corresponding MPIO engine, so replace 'engine' with 'chip' in the warning. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f55a3f8e1d220d4eb7b0287d03b7af2e5d2889f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22vc/amd/opensil/genoa_poc/mpio: use device status for port_presentFelix Held
Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE macro parameter when the device is enabled; otherwise report the port as disabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81342 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: simplify per_device_config argumentsFelix Held
Since we're already passing a pointer to the corresponding device to per_device_config, we don't need to pass the chip_info as separate parameter. Before moving the PCIe port function device below the MPIO chip, the chip_info struct was from a different device, so that change allows this simplification. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chipFelix Held
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22vc/intel/fsp/twinlake: Add FspProducerDataHeader.h headerRonak Kanabar
This patch is to add FspProducerDataHeader.h header file to support MRC version Info in TWL. BUG=b:296433836 Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81037 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-22vc/intel/edk2-stable202111: Resolve compilation error in EDK2 202111Ronak Kanabar
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used with UDK_202111_BINDING Kconfig. Compilation error: src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25: error: static assertion failed: "sizeof (L\'A\') does not meet UEFI Specification Data Type requirements" src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25: error: static assertion failed: "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements" BUG=b:296433836 TEST=Able to build google/crassk with UDK_202111_BINDING. Change-Id: Ib2716436a910b43a5e546afdedb9eec88c5da8c6 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81328 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21vendorcode/cavium: Use unsigned integers in struct bitfieldsArthur Heymans
Bitfields with signed integers are not valid C code. This fixes compilation with clang v16.0.6. Change-Id: I0b2add2f1078a88347fea7dc65d422d0e5a210a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80638 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20vc/amd/opensil/*/mpio: add IFTYPE_UNUSED mpio_type enum elementFelix Held
Add IFTYPE_UNUSED as first element to the mpio_type enum. This allows checking if the type was set in the devicetree, since the default will now be IFTYPE_UNUSED. If the type is set to IFTYPE_UNUSED although the corresponding PCI device function, a warning is printed and the PCI device function is disabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85e2589c021b4f05662369fd551146b6f2fa0ad4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-20vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type valuesFelix Held
Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more specific names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20vc/amd/opensil/stub/mpio: change mpio_engine_type prefix to IFTYPEFelix Held
Change the prefix of the elements of the mpio_engine_type enum from ENGINE_ to IFTYPE_. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: If81c5ea01ba147b71b423004a2199b348ffac99a Reviewed-on: https://review.coreboot.org/c/coreboot/+/81346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-17vc/amd/opensil: don't use source path when using stubMarshall Dawson
Add a 'depends on' statement so that path/to/opensil/source is only active when the stub is not built. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81189 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14vendorcode/edk2-stable202302: Remove wchar_t assertsArthur Heymans
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used. The FSP interface does not depend on wchar_t. TEST: the resulting binaries are the same for intel/mtlrvp Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-11vc/amd/opensil/stub: add stub MPIO driverFelix Held
Add a stub MPIO chip driver to the openSIL stub code, so that the devicetree entries needed for the MPIO chip can already be added to the mainboard's devicetree files. This driver won't do anything, but still allows the register settings in the devicetree to be set to make switching over to the actual openSIL code and the corresponding glue code easier. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-08vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91Ronak Kanabar
Update header files for FSP for Meteor Lake platform to version 3471_91, previous version being 3471_85. FSPM: 1. Address offset changes BUG=b:327688959 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I5a71232018dfefec63b0a83d1e87717e238a4a0a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80782 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use GiB defineFelix Held
Use the GiB define to make the 4 GiB boundary used in some places in the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-05soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SPShuo Liu
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer to reduce the dependency. TEST=intel/archercity CRB Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05Revert "vc/intel/edk2: Remove edk2-stable202111 support"Ronak Kanabar
This reverts commit b5f6320c694766d10023fe8f5183c9c143441b2b. ADL-N FSP uses 202111 Edk2. There are structure definition changes between 202005 and 202111. One of change is in FSP_INFO_HEADER structure. This patch is to bring back support of edk2-stable202111. BUG=b:296433836 TEST=Able to build google/crassk. Change-Id: Id1d3e2c5b368a479e637f3ab3d18e242607849ed Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05vc/google/chromeos: Implement dynamic ChromeOS boot logo selectionSubrata Banik
* Introduces logic to display context-specific boot splash logos. * Logo selection considers: * Chromebook-Plus hardware compliance (using factory_config). * VPD-based product segmentation (soft-branded vs. regular chromebook). * Default Chromebook logo as fallback for regular Chromebook. This patch fixes the problem where existing logic was unable to pick correct ChromeOS boot splash logo based on the product segmentation. Relation between product segment and boot splash screen: 1. Chromebook-Plus Hard-branded device: Renders "cb_plus_logo.bmp" logo 2. Chromebook-Plus Soft-branded device: Renders "cb_plus_logo.bmp" logo 3. Regular Chromebook device: Renders "cb_logo.bmp" BUG=b:324107408 TEST=Verified logo selection based on compliance and product requirements. Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-23vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum nameFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23vc/intel/fsp2/twinlake: Add FSP headersKapil Porwal
Add FSP header files for Twin Lake. Currently these are just a copy of ADL-N headers. BUG=none BRANCH=firmware-nissa-15217.B TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I37579335c784866ebbf978e28936abf046a85b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-20soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI headerShuo Liu
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC are ACPI table specific, and could be used across Xeon-SP SoCs. This patch moves their definition from FSP header to Xeon-SP layer ACPI header. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-02-18Treewide: Fix incorrect SPDX license stringsMartin Roth
These strings didn't match the license names exactly, so update them to match. Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-12vc/amd/fsp/picasso: Bring picasso inline with other AMD SoCVarshit Pandya
In preparation to using gpp_clk_setup_common for picasso, bring enum defined in picasso more in line with other AMD SoC. Change-Id: I9753acdff15921c84516ec873c925f36afdd2aa3 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80412 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-02vc/amd/opensil: add openSIL stub implementationFelix Held
Add a stub implementation of the openSIL interface between coreboot and vendorcode. This can be used to add most of the coreboot-side support for a SoC using openSIL without the actual opnSIL code already being publicly available. Once the corresponding openSIL code is available, the SoC can then switch over to using the actual openSIL implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80292 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-02vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.hFelix Held
Provide 3 separate functions for each openSIL time point instead of one, so that we don't need the xSIM-api header file to be included in opensil.h to decouple the coreboot code more form the openSIL code. This will allow to create an openSIL stub implementation to already get most of the coreboot-side SoC code in place before the openSIL source code is done and released. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-01soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resourcesFelix Held
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the legacy PCI config space access is needed on all AMD SoCs, implement a common add_pci_cfg_resources function that reports both and gets called from amd_pci_domain_read_resources and don't report those in the SoC- specific code any more. The only functional change is that on Genoa now the IO ports used for the legacy PCI config space access get reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01vc/amd/opensil/genoa_poc/memmap: pass resource index as pointerFelix Held
To make add_opensil_memmap match the other function that are directly or indirectly called by amd_pci_domain_read_resources, pass the resource index as a pointer instead of passing it by value and then returning the new resource index. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource indexFelix Held
Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct and the functions to report the resources. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80265 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-26vc/amd: move verstage on PSP files to new psp_verstage folderFelix Held
Move the verstage on PSP files in vendorcode from the fsp subdirectory to a new psp_verstage subdirectory, since those files aren't specific to the case of the FSP being used for the silicon initialization. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80209 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-01-25vc/amd/opensil/genoa_poc/mpio: don't add duplicate MPIO descriptorsFelix Held
When the device right below the MPIO chip driver has downstream devices without another chip in between, those downstream devices will also have their chip_ops entry set to vendorcode_amd_opensil_genoa_poc_mpio_ops. To avoid adding the same MPIO descriptor again for those additional downstream devices, make sure that the chip_info pointer of the device isn't the same as the one of the parent device, since that's only the case for those additional downstream devices. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6ba90fdc83ba089127e6722778bfef29dd480bb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25soc/amd/genoa_poc: rely less on boot state hooksFelix Held
Call setup_opensil, opensil_entry, and fch_init in the right order from the init method of the SoC's chip operations. This brings this SoC both more in line with the other SoCs and avoids using boot state hooks for this which also makes the sequence in which those functions are called easier to understand. Previously the boot states were used so that setup_opensil was run before configure_mpio which was run before opensil_entry(SIL_TP1), but since configure_mpio is called from setup_opensil, this is no longer necessary. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same. The FCH init code now runs before the resource allocation like on the AMD SoCs that rely on FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensilFelix Held
Instead of calling configure_mpio from the init function of the MPIO chip struct for the first device that has this struct as chip_ops, call if from setup_opensil. This will allow to do the calls into openSIL from the SoC's chip_ops init function instead of having to rely on boot state hooks. configure_mpio needs to be called after the xSimAssignMemoryTp1 call which sets up the openSIL data structures, but before the opensil_entry(SIL_TP1) call for which the MPIO data structures need to be filled for it to be able to initialize the hardware accordingly. Since the vendorcode_amd_opensil_genoa_poc_mpio_ops struct now no longer assigns configure_mpio to the init function pointer, we have to check if the device's chip_ops pointer points to vendorcode_amd_opensil_genoa_poc_mpio_ops instead of checking if the chip_ops' init function is configure_mpio to match for the devices below the MPIO chips in the devicetree. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc/opensil_console: fix host debug print functionFelix Held
Since we pass va_list list to the print function, we need to use vprintk instead of printk. Earlier versions of this code used vsnprintf and a local buffer, but when that code was reworked to not need the temporary buffer, it was replaced by printk instead of the correct vprintk. TEST=Now the console output from openSIL looks as expected: Example line from openSIL's console output when it prints the MPIO configuration from a log some commits before this patch: Host PCI Address - -1352681400:-1353251983:7 Same line with this patch applied looks how it's supposed to: Host PCI Address - 0:0:0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ia931cc80dea5b7eabb75cfb19f8baa9a09cd2dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/80203 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpioFelix Held
As a preparation for the following patch, rename mpio_config to configure_mpio to make it both a bit more descriptive and to match the naming scheme used for the functions that get called by setup_opensil. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4b1aa6e964cbbb4affb89cacd33af8b24871bb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-01-24vendorcode: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I80559b7c86a8fd2583cb0335279f676e0aa0209e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80067 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-01-17vc/amd/psp: Remove unknown section flagsLennart Eichhorn
The `d` flag used in .section is unknown in LLVM/clang 17 and fails the build. It is also not documented in the ARM compiler manual. The GNU assembler supports the `d` flag but it also seems to compile without. ARM compiler manual: https://developer.arm.com/documentation/101754/0621/armclang-Reference/armclang-Integrated-Assembler/Section-directives GNU compiler manual: https://sourceware.org/binutils/docs/as/Section.html `coreboot.rom` does not change between compiling a google skyrim board with or without this patch. However the debug info for the following three files in the build directory changes with this patch: * build/verstage/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.o * build/cbfs/fallback/verstage.elf * build/cbfs/fallback/verstage.debug Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79366 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11vc/google: Show different logos for different ChromeOS devicesShelley Chen
This commit adds support for showing different logos on the ChromeOS firmware splash screen based on the device model (between Chromebook-Plus and regular ChromeOS devices like Chromebook and Chromebox). This allows OEMs to customize the branding on their devices. This patch also introduces three new Kconfigs: - CHROMEOS_FW_SPLASH_SCREEN - CHROMEOS_LOGO_PATH - CHROMEBOOK_PLUS_LOGO_PATH which allow users to enable the fw splash screen feature in the vendorcode. Previously, we were using the BMP_LOGO Kconfig in drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be located inside the architecture specific files. BUG=b:317880956 BRANCH=None TEST=emerge-rex coreboot chromeos-bootimage verify that FW splash screen appears Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79775 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-07vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85Kulkarni, Srinivas
Update header files for FSP for Meteor Lake platform to version 3471_85, previous version being 3424_88. FSPM: 1. Add 'DisplayGpioPinMux' UPDs 2. Address offset changes BUG=b:318772151 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-05vendorcode/google/chromeos: Use unsigned int for "factory_config"Subrata Banik
This patch ensures `chromeos_get_factory_config()` returns an unsigned integer value because factory config represents bit-fields to determine the Chromebook Plus branding. Additionally, introduced safety measures to catch future "factory_config" bit-field exhaustion. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79769 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-31vendorcode/google/chromeos: Add API for Chromebook Plus checkSubrata Banik
This patch implements an API which relies on the chromeos_get_factory_config() function to retrieve the factory config value. This information is useful to determine whether a ChromeOS device is branded as a Chromebook Plus based on specific bit flags: - Bit 4 (0x10): Indicates whether the device chassis has the "chromebook-plus" branding. - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus hardware specifications. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-31vendorcode/google/chromeos: Add API to read factory configSubrata Banik
This code leverages the TPM vendor-specific function tlcl_cr50_get_factory_config() to fetch the device's factory configuration. BUG=b:317880956 TEST=Able to retrieve the factory config from google/screebo. Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-20vc/intel/fsp/mtl: Add UPDs for Acoustic Noise MitigationSubrata Banik
Acoustic noise in PCBs is a common problem and be caused by a variety of factors, including: Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal expansion. This patch adds the UPDs to FSPM header file for mitigating the acoustic noise. FSPM: 1. AcousticNoiseMitigation 2. FastPkgCRampDisable 3. SlowSlewRate BUG=b:312405633 TEST=Able to build and boot google/rex. Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-17vc/intel/raptorlake: Update header files from 4301_01 to 4435_00Kulkarni, Srinivas
Update header files for FSP for Raptor Lake platform to version 4435_00, previous version being 4301_01. FSPM: 1. Options changed for Ppr Enable 2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's FSPS: 1. Add 'CpuPcieRpTestForceLtrOverride' UPD MemInfoHob: 1. Structure updated BUG=b:315234533 Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/ software-kits/kit-details.html?kitId=793230 Cq-Depend: chrome-internal:6786881, chrome-internal:6787635 Cq-Depend: chrome-internal:6719974, chromium:5125983 Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69 Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16vc/amd/opensil: add _POC suffix to SOC_AMD_OPENSIL_GENOAFelix Held
The openSIL code for the Genoa SoC is only a proof of concept, so change the name of the Kconfig option to include this code in the build from SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this is code that isn't intended or ready to be productized. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16soc/amd/genoa: rename to genoa_pocFelix Held
Even though this SoC is called 'Genoa', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15vc/amd: use 'openSIL' spelling in comments & help textFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I176182180f508a180726fca60064b16fad80e9d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-14vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_portsFelix Held
Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O ports in FADT that openSIL configured. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard pathKulkarni, Srinivas
Move the existing FSP 4301.01 headers for Raptor Lake out of subdirectory called 43101.01 to follow standard process. Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-13lib/jpeg: Replace decoder with Wuffs' implementationPatrick Georgi
To quote its repo[0]: Wuffs is a memory-safe programming language (and a standard library written in that language) for Wrangling Untrusted File Formats Safely. Wrangling includes parsing, decoding and encoding. It compiles its library, written in its own language, to a C/C++ source file that can then be used independently without needing support for the language. That library is now imported to src/vendorcode/wuffs/. This change modifies our linters to ignore that directory because it's supposed to contain the wuffs compiler's result verbatim. Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that implements our JPEG API. I further changed it a bit regarding data placement, dropped stuff from our API that wasn't ever used, or isn't used anymore, and generally made it fit coreboot a bit better. Features are Nigel's, bugs are mine. This commit also adapts our jpeg fuzz test to work with the modified API. After limiting it to deal only with approximately screen sized inputs, it fuzzed for 25 hours CPU time without a single hang or crash. This is a notable improvement over running the test with our old decoder which crashes within a minute. Finally, I tried the new parser with a pretty-much-random JPEG file I got from the internet, and it just showed it (once the resolution matched), which is also a notable improvement over the old decoder which is very particular about the subset of JPEG it supports. In terms of code size, a QEmu build's ramstage increases from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA). [0] https://github.com/google/wuffs Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Based-on-work-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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