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2021-12-01vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAMRyan Chuang
Fix the issue that power consumption of single rank DRAM is greater than dual rank DRAM due to incorrect settings of rank1 CKE. Set rank1 CKE to the correct state to fix this issue. BUG=b:196867407 TEST=DUT can boot to OS. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-01vc/mediatek/mt8195: Remove unused code and commentsRyan Chuang
Remove unused code and comment to align with the latest MTK memory reference code which is from MTK internal dram driver code without upstream. version: Ib59134533ced8de09d23dd9f347c934d315166e2 TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-08vc/mediatek/mt8195: fix misleading-indentation errorRex-BC Chen
Fix misleading-indentation error in dramc_pi_calibration_api.c. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-29vc/mediatek/mt8195: Remove unused codeRyan Chuang
Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03vc/mediatek/mt8195: Remove unused codeRyan Chuang
Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore settingRyan Chuang
Remove the unnecessary Vcore setting for the DVFS feature. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If3c28e57a559a7ec04319c1a489138817e44ec4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/ORyan Chuang
Disable reading of vdram/vddq/vmddr to reduce access of I2C to reduce DRAM init time by about 30ms. The values were only needed by HQA report and not needed on production units. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency countRyan Chuang
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM frequency counts to reduce DRAM initialization time by about 100ms. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-28vc/mediatek/mt8195: Improve DRAM stability by impedance trackingRyan Chuang
Enable the impedance tracking for channel 2 and channel 3. The impedance tracking can compensate the settings of impedance when the temperature changes. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13vc/mediatek/mt8195: Remove redundant codeRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-12vc/mediatek/mt8195: Enable DRAM Vcore DVFS settingsRyan Chuang
Add the implementation for vcore voltage control. Also remove the reporting of vio18 because it is fixed during DRAM init, and we won't provide drivers for reading or writing it. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12vc/mediatek/mt8195: add FOR_COREBOOT defineRex-BC Chen
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to identify implementations for Chromebooks (in coreboot) so we want to introduce a new flag FOR_COREBOOT to prevent confusion. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stabilityRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07vc/mediatek/mt8195: Improve settings of duty calibrationRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-30vc/mediatek/mt8195: Fix license headersRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If5e72b36242e1aff7ce2609ea6bdbaea53683bd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-24vc/mediatek/mt8195: Allow adjusting DRAM voltage in DRAM calibrationRyan Chuang
To support DRAM HQA HV/LV test, add an interface for adjusting the DRAM voltage in DRAM fast calibration flow. Normal boot flow will not be affected. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I4dbb4cb546e6e60693743ffe26b0df28ea501618 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55752 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-15vc/mediatek/mt8195: Match definition with declarationPatrick Georgi
gcc 11 insists. Change-Id: Icec68ab7a3c0bce9b18e37c1b6f41603c97181e2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-15vc/mediatek/mt8195: Fix code indentationPatrick Georgi
gcc 11 complains about it otherwise. Change-Id: Ic9b2124506f33c76902d3b44481f14182c1d74b9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-14vendor/mediatek: Add MT8195 dram initialization codeRyan Chuang
This is the DRAM initialization code from the reference implementation released by Mediatek for MT8195. The DRAM calibration code can be taken as a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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