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2022-09-22vc/intel/fsp/mtl: Update header files from 2304_01 to 2344_00Srinidhi N Kaushik
Update header files for FSP for Meteor Lake platform to version 2344_00, previous version being 2304_01. FSPM: 1. Address offset changes FSPS: 1. Deprecated CstateLatencyControlTimeUnit UPDs 2. Deprecated HybridStorageMode 3.Address offset changes BUG=b:245167089 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iaee5c66811c340d12921ff9247461df36de4739a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-04vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00Saurabh Mishra
Update generated FSP headers for Alder Lake N from v3267.01 to v3301.00. Changes include: - FspsUpd.h: 1. Add VccInAuxImonSlope UPD 2. Update UPD Offset in FspsUpd.h BUG=b:242152105 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-01vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1Sean Rhodes
Add the headers for 2.2.3.1, which includes the following changes over 2.2.0.0: • [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry failure in less than 5 cycles when a USB2 Ethernet Dongle is connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter 7.20.6 for new Register settings. • [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini Lake/Gemini Lake – R • [Update] MRC new version update to 1.38. • [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from S4 issue with latest Wifi driver. [Update] MRC new version update to 1.39. Included fix for MinRefRate2xEnable and support for Rowhammer mitigation. • [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This change specific to DDR4 memory configuration. • GLK Klocwork Fix • [Update] MRC new version update to 1.40. Added in a separate directory as the default. The 2.2.0.0 headers were left and will be used for Google boards, as some offsets have moved. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-31vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3301.03Selma Bensaid
The headers added are generated as per FSP v3301.03 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:243693364 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-07vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01Saurabh Mishra
Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01. Changes include: - Add UPD Lp5BankMode - Update UPD Offset in FspmUpd.h BUG=b:240373012 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-05vc/intel/fsp/mtl: Update header files from 2253_00 to 2304_01Srinidhi N Kaushik
Update header files for FSP for Meteor Lake platform to version 2304_01, previous version being 2253_00. FSPM: 1. Removed CpuCrashLogDevice 2. Address offset changes FSPS: Includes below new UPDs 1. VpuEnable 2. SerialIoI3cMode 3. ThcAssignment 4. PchIshI3cEnable BUG=b:240665069 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9740e5877af745124d573425da623e814d8df5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30vendorcode/intel/fsp: Fix wrong licenseBora Guvendik
Fix the license in header file. BUG=none BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I025f7c571d09e4cc63a659279e63d17c098c01cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-19vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3257_00_40Bora Guvendik
The headers added are generated as per FSP v3257_00_40. In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:238791453 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-18vc/intel/edk2/edk2-stable202111: Add `MpServices2.h` fileSubrata Banik
This patch fixes a missing header file compilation issue when coreboot selects MP_SERVICES_PPI_V2 config from MTL SoC. The `MpServices2.h` file doesn't exist in the upstreamed EDK2 repo (integrated with `edk2-stable202111` stable tag). Currently MpServices2.h file is being copied from the `edk2_stable202005` stable tag. BUG=b:237960384 ([Intel FSP][EDK2011] MpServices2.h header is missing in upstream EDKII git) TEST=Able to fix the compilation issue on Google/Rex (Meteor Lake) when MP_SERVICES_PPI_V2 kconfig is enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib7c406ff51439c93c6d15f3a69808b4d1590cfa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65624 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13vc/intel/fsp2_0: Update partial headers to MTL.FSP2253.00Kapil Porwal
Update partial headers to MeteorLake FSP v2253.00 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If2d6c80bd35afd68588fef57e38064c5b1e1a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-03vc/intel/fsp2_0: Add UPDs into the FSP partial header version 2222Subrata Banik
This patch adds below UPDs into the existing FSP partial header v2222.1 FSP-M UPD: DisableMc0Ch0 DisableMc0Ch1 DisableMc0Ch2 DisableMc0Ch3 DisableMc1Ch0 DisableMc1Ch1 DisableMc1Ch2 DisableMc1Ch3 DdrFreqLimit GpioOverride SerialIoUartDebugMode SerialDebugMrcLevel SmbusDynamicPowerGating WdtDisableAndLock SaIpuEnable SkipCpuReplacementCheck TcssDma0En TcssDma1En VtdBaseAddress CpuCrashLogDevice CpuCrashLogEnable LCT TdcEnable TdcTimeWindow Lp5CccConfig RMTBIT RmtPerTask RMTLoopCount MrcFastBoot EnCmdRate SaGvGear TAT PchHdaVcType BdatTestType RdEnergyMc0Ch0Dimm1 RdEnergyMc0Ch0Dimm0 CorePllVoltageOffset RdEnergyMc1Ch1Dimm1 RdEnergyMc1Ch1Dimm0 DciEn PchPort80Route ActEnergyMc0Ch1Dimm1 ActEnergyMc0Ch1Dimm0 HeciCommunication2 PcdSerialDebugBaudRate HeciTimeouts ThrtCkeMinDefeatLpddr PchPcieHsioRxSetCtle BdatEnable DisableCpuReplacedPolling PchSataHsioRxGen1EqBoostMagEnable CoreVoltageOffset PchPcieHsioTxGen1DownscaleAmp PchHdaDspUaaCompliance VddVoltage WRVC1D PreBootDmaMask tWR RingVoltageAdaptive PchSataHsioTxGen3DeEmphEnable PchPcieHsioRxSetCtleEnable RingPllVoltageOffset OcSupport WrEnergyMc0Ch0Dimm1 PdEnergyMc1Ch1Dimm1 PdEnergyMc1Ch1Dimm0 DmiGen3ProgramStaticEq SmramMask tRAS PerCoreHtDisable IdleEnergyMc1Ch0Dimm0 IdleEnergyMc1Ch0Dimm1 Gen3LtcoEnable tWTR RCVET DmiGen3UsPresetEnable tCWL PwdwnIdleCounter WRTC1D CLKTCO PrimaryDisplay DisableMessageCheck tFAW PchSataHsioTxGen2DeEmphEnable SerialIoUartDebugRtsPinMux GtExtraTurboVoltage TXTCO PchSataHsioTxGen3DownscaleAmp CpuRatioOverride PostCodeOutputPort DmiHweq CoreVfPointCount NModeSupport Ddr4DdpSharedZq RdEnergyMc1Ch0Dimm0 RdEnergyMc1Ch0Dimm1 PchSataHsioTxGen2DownscaleAmp DebugInterfaceEnable WrEnergyMc0Ch1Dimm0 WrEnergyMc0Ch1Dimm1 SaPllVoltageOffset DmiGen3EndPointPreset PchSataHsioRxGen2EqBoostMag VDDQT PvdRatioThreshold CoreVfPointOffsetMode DmiGen3DsPortRxPreset BclkRfiFreq SmbusArpEnable PowerDownMode DebugInterfaceLockEnable RingVoltageOffset EnableExtts SerialIoUartDebugCtsPinMux PchPcieHsioTxGen2DownscaleAmpEnable Avx2VoltageScaleFactor GearRatio GtVoltageOverride EccSupport RingMaxOcRatio TrainTrace EnablePwrDn IsTPMPresence OcLock DmaBufferSize SOT CoreVfPointRatio PchPcieHsioTxGen2DownscaleAmp TjMaxOffset CoreMaxOcRatio RingDownBin PchSataHsioRxGen1EqBoostMag BiosAcmSize tRFC PchPcieHsioTxGen1DownscaleAmpEnable PdEnergyMc0Ch1Dimm0 PdEnergyMc0Ch1Dimm1 RDMPRT TxtLcpPdBase CMDVC SerialIoUartDebugBaudRate PchTraceHubMemReg1Size CoreVoltageOverride McPllVoltageOffset PdEnergyMc1Ch0Dimm0 PdEnergyMc1Ch0Dimm1 GttMmAdr PchPcieHsioTxGen1DeEmphEnable ApStartupBase CoreVoltageAdaptive GtVoltageMode PcieImrRpSelection TxtLcpPdSize PchPcieHsioTxGen2DeEmph3p5 ThrtCkeMinTmr RealtimeMemoryTiming UserBudgetEnable PchPcieHsioTxGen3DownscaleAmpEnable GmAdr PchSataHsioTxGen1DeEmphEnable CrashLogGprs tRTP RMC PchSataHsioTxGen3DownscaleAmpEnable RDODTT RDVREFDC PerCoreRatio IdleEnergyMc0Ch1Dimm1 tRCDtRP DidInitStat SerialIoUartDebugRxPinMux SerialIoUartDebugMmioBase BiosSize MmioSizeAdjustment PchTraceHubMode DmiGen3Ltcpre CoreVoltageMode DmiGen3UsPortTxPreset Gen3EqPhase3Bypass BclkSource KtDeviceEnable DciUsb3TypecUfpDbg CoreVfPointOffset Gen3RtcoRtpoEnable TotalFlashSize BclkAdaptiveVoltage TvbRatioClipping EnablePwrDnLpddr WRTC2D RankInterleave PchSataHsioRxGen3EqBoostMag IdleEnergyMc0Ch0Dimm1 IdleEnergyMc0Ch0Dimm0 Ratio JWRL Avx3RatioOffset Avx2RatioOffset RDVC1D DCC PchSataHsioTxGen2DeEmph ExitOnFailure IdleEnergyMc1Ch1Dimm1 IdleEnergyMc1Ch1Dimm0 RingVoltageOverride SpdProfileSelected ScramblerSupport SaGvFreq WRVC2D DmiGen3EqPh3Method CMDSR RdEnergyMc0Ch1Dimm0 RdEnergyMc0Ch1Dimm1 UserThresholdEnable ThrtCkeMinDefeat DmiGen3EqPh2Enable tRRD ChHashEnable BistOnReset ChHashInterleaveBit RemapEnable RDVC2D DIMMRONT WrEnergyMc0Ch0Dimm0 DmiAspm PchPcieHsioTxGen2DeEmph6p0Enable PchSataHsioTxGen1DeEmph RDEQT TxtDprMemoryBase WrEnergyMc1Ch0Dimm1 WrEnergyMc1Ch0Dimm0 DmiGen3EndPointHint CleanMemory PchSmbAlertEnable SaOcSupport PchSataHsioTxGen3DeEmph TxtImplemented CoreVfPointOffsetPrefix PchHdaTestPowerClockGating DmaControlGuarantee DIMMODTT ERDMPRTC2D RootPortIndex SkipStopPbet VtdIopEnable DmiGen3DsPortTxPreset ActiveCoreCount PchLpcEnhancePort8xhDecoding GtVoltageOffset DisPgCloseIdleTimeout ActEnergyMc1Ch0Dimm1 ActEnergyMc1Ch0Dimm0 Idd3n Idd3p PchSataHsioTxGen1DownscaleAmpEnable BClkFrequency ActEnergyMc0Ch0Dimm0 ActEnergyMc0Ch0Dimm1 DdrFreqLimit Gen3EqPhase23Bypass WrEnergyMc1Ch1Dimm0 DmiGen3DsPresetEnable PcieImrSize EWRTC2D IbeccOperationMode VtdBaseAddress TvbVoltageOptimization DciDbcMode HobBufferSize PchHdaSdiEnable PcieImrEnabled IdleEnergyMc0Ch1Dimm0 SerialIoUartDebugAutoFlow tCL PdEnergyMc0Ch0Dimm1 PdEnergyMc0Ch0Dimm0 RDTC2D ERDTC2D SerialIoUartDebugParity PchPcieHsioTxGen2DeEmph3p5Enable PchPcieHsioTxGen1DeEmph DmiGen3Ltcpo PchSmbusIoBase RaplPwrFlCh1 RaplPwrFlCh0 EnhancedInterleave PchPcieHsioTxGen2DeEmph6p0 MemTestOnWarmBoot Ibecc PanelPowerEnable BiosAcmBase DmiGen3UsPortRxPreset DmiAspmL1ExitLatency CmdMirror PchSataHsioTxGen2DownscaleAmpEnable tREFI CpuBclkOcFrequency CridEnable EpgEnable SmbusSpdWriteDisable DdrSpeedControl PchSataHsioRxGen2EqBoostMagEnable GtMaxOcRatio DmiMaxLinkSpeed PchSataHsioRxGen3EqBoostMagEnable PcieImrRpLocation CmdRanksTerminated SkipMbpHob SerialIoUartDebugTxPinMux PchSataHsioTxGen1DownscaleAmp PchPcieHsioTxGen3DownscaleAmp PerCoreRatioOverride PchHdaAudioLinkDmicClockSelect SerialIoUartDebugDataBits SrefCfgEna Avx512VoltageScaleFactor MmioSize SaVoltageOffset SaIpuEnable ActEnergyMc1Ch1Dimm0 ActEnergyMc1Ch1Dimm1 ProbelessTrace VtdIgdEnable ALIASCHK PchTraceHubMemReg0Size DIMMODTCA TgaSize EWRDSEQ SerialIoUartDebugStopBits RDTC1D CMDNORM RingVoltageMode EnableAbove4GBMmio WrEnergyMc1Ch1Dimm1 Txt PcieMultipleSegmentEnabled CnviDdrRfim FSP-S UPD: CpuMpPpi LidStatus ITbtConnectTopologyTimeoutInMs D3HotEnable D3ColdEnable PchLockDownGlobalSmi PchLockDownBiosInterface PchUnlockGpioPads RtcMemoryLock SkipPamLock EndOfPostMessage CpuUsb3OverCurrentPin PcieRpHotPlug SerialIoUartAutoFlow TccActivationOffset VmdEnable Enable8254ClockGating Enable8254ClockGatingOnS3 HybridStorageMode PcieRpHotPlug Hwp Cx PsOnEnable EnergyEfficientTurbo PchPmDisableEnergyReport UfsEnable FspEventHandler GnaEnable VbtSize PcieComplianceTestMode CStatePreWake SerialIoUartDataBits SataPortsExternal CstateLatencyControl0TimeUnit SataP0Tinact PmcV1p05PhyExtFetControlEn ApIdleManner SataPortsSpinUp DisableProcHotOut ITbtPcieTunnelingForUsb4 SerialIoUartDmaEnable SaPcieItbtRpNonSnoopLatencyOverrideMode SaPcieItbtRpSnoopLatencyOverrideMode MlcSpatialPrefetcher PchXhciOcLock PmcPowerButtonDebounce TccOffsetClamp LogoPixelWidth AvxDisable Custom1PowerLimit1 Custom1PowerLimit2 PmcCpuC10GatePinEnable PchPmSlpStrchSusUp IshI2cSdaPadTermination Custom2PowerLimit1Time RtcBiosInterfaceLock WatchDogTimerBios SataP1TDisp PchPciePort8xhDecodePortIndex PcieRpImrSelection TcCstateLimit PchS0ixAutoDemotion PchFivrExtV1p05RailEnabledStates PcieRpSlotPowerLimitScale IshUartCtsPinMuxing PcieRpSnoopLatencyOverrideMode TTCrossThrottling PsysPowerLimit1 SataRstInterrupt IshSpiClkPadTermination PcieEnablePeerMemoryWrite SataP1T2M ChipsetInitBinPtr LogoPixelHeight PsysPowerLimit1Time HwpInterruptControl DevIntConfigPtr IshUartRtsPadTermination PsysPowerLimit1Power EnergyEfficientTurbo Custom3TurboActivationRatio PcieDpc TurboMode PchFivrExtVnnRailSupportedVoltageStates ITbtDmaLtr IshSpiClkPinMuxing PchSbAccessUnlock PcieRpSystemErrorOnCorrectableError PcieRpSlotPowerLimitValue SendEcCmd SataSpeedLimit SataRstPcieEnable PchUsb3HsioCtrlAdaptOffsetCfg SataP0T2M PchHdaVerbTableEntryNum DmiTS1TW DmiTS2TW PcieRpImrEnabled GpioIrqRoute SataPortsSolidStateDrive RaceToHalt PcieRpNonSnoopLatencyOverrideMultiplier PcieRpUnsupportedRequestReport AesEnable PchFivrExtVnnRailSxVoltage SataP1Tinact PkgCStateUnDemotion SataPortsZpOdd PchSerialIoI2cPadsTermination PchFivrExtV1p05RailSupportedVoltageStates PchUsbLtrLowIdleTimeOverride IshSpiMosiPinMuxing PchProtectedRangeLimit SaPcieItbtRpNonSnoopLatencyOverrideValue SataP1T3M PchPmWoWlanEnable IshUartRtsPinMuxing SataLedEnable VmdGlobalMapping PcieRpEnableCpm IshGpGpioPadTermination PchDmiCwbEnable ForcMebxSyncUp FspEventHandler PchFivrExtVnnRailIccMax PchPmMeWakeSts DisableD0I3SettingForHeci PcieRpNonSnoopLatencyOverrideMode PmgCstCfgCtrlLock PchUsbLtrHighIdleTimeOverride Usb3HsioTxRate2UniqTran SiNumberOfSsidTableEntry IshSpiMisoPadTermination IshUartRxPadTermination PcieRpSlotImplemented PchUsbOverCurrentEnable EndOfPostMessage SaPcieItbtRpSnoopLatencyOverrideValue EnableHwpAutoEppGrouping SerialIoUartDbg2 ConfigTdpLock EsataSpeedLimit PchTsnEnable PowerLimit3DutyCycle TTSuggestedSetting PchEnableDbcObs IehMode VmdPort PchFivrExtVnnRailCtrlRampTmr PchPmSlpAMinAssert CstateLatencyControl5TimeUnit ProcessorTraceEnable ChipsetInitBinLen PchTemperatureHotLevel Usb3HsioTxRate3UniqTranEnable NumberOfEntries Custom2ConfigTdpControl PowerLimit3Lock SiCustomizedSsid PchUsb3HsioFilterSelP DisableVrThermalAlert PchIoApicEntry24_119 SmbiosType4MaxSpeedOverride PowerLimit3Time C1StateUnDemotion PchDmiAspmCtrl PchUsb3HsioFilterSelN PchTTEnable PcieRpNoFatalErrorReport Custom1ConfigTdpControl PmcC10DynamicThresholdAdjustment PchFivrVccinAuxRetToLowCurModeVolTranTime BiProcHot VmdPortFunc PchUsb3HsioFilterSelNEnable PchHdaVerbTablePtr TurboPowerLimitLock PcieRpSystemErrorOnNonFatalError PmcUsb2PhySusPgEnable PcieRpSystemErrorOnFatalError PchProtectedRangeBase VccSt PchFivrExtVnnRailSxEnabledStates EnableHwpAutoPerCorePstate CstateLatencyControl1TimeUnit SaPcieItbtRpSnoopLatencyOverrideMultiplier PchPmSlpS4MinAssert PcieRpTransmitterHalfSwing Usb3HsioTxRate3UniqTran RenderStandby ProcessorTraceOutputScheme SkipFspGop PchHdaPme EcCmdProvisionEav BgpdtHash Usb3HsioTxRate0UniqTran UsbOverride PkgCStateDemotion EnableAllThermalFunctions PchPmWolEnableOverride IshSpiCsPinMuxing PchIshSpiCsEnable IshUartCtsPadTermination PmcV1p05IsExtFetControlEn MaxRingRatioLimit PchIshPdtUnlock IshUartTxPinMuxing PchFivrExtV1p05RailIccMax BiosGuardAttr LogoPtr CpuBistData ShowSpiController PchPmWolOvrWkSts SataP0T1M CstCfgCtrIoMwaitRedirection TcoIrqEnable PchHdaLinkFrequency ITbtForcePowerOnTimeoutInMs SerialIoSpiCsEnable VmdMemBar2Base TStates SiSkipSsidProgramming TccOffsetTimeWindowForRatl AmtSolEnabled PchUsb3HsioCtrlAdaptOffsetCfgEnable PchFivrExtVnnRailIccMaximum PchEspiLgmrEnable SkipPamLock IshGpGpioPinMuxing PchUsb3HsioFilterSelPEnable PchFivrExtVnnRailVoltage SataPortsDevSlpResetConfig ProcHotLock PchDmiTsawEn SerialIoSpiCsPolarity PkgCStateLimit EnableRsr PmcDbgMsgEn PchPmPwrCycDur NumOfDevIntConfig SerialIoSpiDefaultCsOutput PchPmPciePllSsc PxRcConfig CstateLatencyControl4TimeUnit PcieRpPmSci ConfigTdpBios PmcPdEnable PchT1Level PmcModPhySusPgEnable DisableTurboGt EnableTcoTimer IshSpiMisoPinMuxing IshI2cSclPinMuxing PcieRpCorrectableErrorReport C1StateAutoDemotion PchEspiLockLinkConfiguration PchFivrExtV1p05RailCtrlRampTmr SataRstPcieStoragePort PchFivrExtV1p05RailVoltage PchPmSlpSusMinAssert PchHotEnable PcieRpNonSnoopLatencyOverrideValue TcoIrqSelect PcieRpCompletionTimeout FwProgress StateRatioMax16 ConfigTdpLevel IshI2cSdaPinMuxing PcieRpPhysicalSlotNumber SerialIoUartParity TxtEnable PchLegacyIoLowLatency PchUsbLtrMediumIdleTimeOverride PchPmPmeB0S5Dis SerialIoUartPowerGating PcieRpSnoopLatencyOverrideValue PchPmSlpLanLowDc PchT2Level CstateLatencyControl2TimeUnit PchPmSlpS3MinAssert PchUsb3HsioOlfpsCfgPullUpDwnResEnable MonitorMwaitEnable Usb3HsioTxRate1UniqTran Eist IshSpiMosiPadTermination PowerLimit4Lock Custom3PowerLimit1Time PcieEnablePort8xhDecode DualTauBoost WatchDogEnabled MaxRatio Custom2TurboActivationRatio PchFivrExtVnnRailEnabledStates ApplyConfigTdp IshI2cSclPadTermination PowerLimit2Power ThermalMonitor CpuUsb3OverCurrentPin PchTTLock Custom1PowerLimit1Time PchEspiHostC10ReportEnable Usb3HsioTxRate2UniqTranEnable SataPortsInterlockSw EnablePerCorePState PsysPowerLimit2Power UfsEnable PchPmDisableNativePowerButton VmdVariablePtr Custom3PowerLimit2 PchPmDisableEnergyReport Custom3PowerLimit1 DmiTS3TW EnforceEDebugMode CstateLatencyControl3TimeUnit VmdCfgBarBase DmiSuggestedSetting SataPortsEnableDitoConfig SerialIoUartBaudRate Usb3HsioTxRate1UniqTranEnable SataPortsHotPlug MachineCheckEnable Custom1TurboActivationRatio Custom2PowerLimit1 Custom2PowerLimit2 VmdMemBar1Base SaPcieItbtRpLtrConfigLock SataP0TDispFinit PchFivrExtVnnRailSxIccMaximum PchTsnLinkSpeed SataThermalSuggestedSetting SaPcieItbtRpLtrEnable TimedMwait PchTsnMultiVcEnable PcieRpFunctionSwap PcieEqOverrideDefault SataP1T1M PsysPowerLimit2 PchLanLtrEnable SerialIoUartStopBits SciIrqSelect C1e PchFivrExtVnnRailSxIccMax PowerLimit3 PowerLimit2 PowerLimit1 MeUnconfigOnRtcClear PcieRpPcieSpeed PchUsbLtrOverrideEnable UsbPdoProgramming Custom3ConfigTdpControl SataP1TDispFinit PchFivrDynPm VmdPortDev EnableItbm MinRingRatioLimit PcieRpFatalErrorReport MctpBroadcastCycle EcCmdLock StateRatio PchPmVrAlert DmiTS0TW LogoSize PchIoApicId SaPcieItbtRpForceLtrOverride PcieRpSnoopLatencyOverrideMultiplier IshUartTxPadTermination PchCrid SataRstPcieDeviceResetDelay ProcHotResponse BltBufferSize MlcStreamerPrefetcher PcieRpLtrConfigLock SiSsidTablePtr SataP0TDisp PchUsb3HsioOlfpsCfgPullUpDwnRes BltBufferAddress PcieRpDetectTimeoutMs PpinSupport SataRstRaidDeviceId PchPmLatchEventsC10Exit IshUartRxPinMuxing PpmIrmSetting EnergyEfficientPState PchFivrExtV1p05RailIccMaximum PortResetMessageEnable PchReadProtectionEnable BiosGuardModulePtr PchWriteProtectionEnable AmtEnabled PchHdaCodecSxWakeCapability SiCustomizedSvid PcieEdpc TccOffsetLock PchPmPwrBtnOverridePeriod SaPcieItbtRpNonSnoopLatencyOverrideMultiplier WatchDogTimerOs PchTTState13Enable PowerLimit1Time PchT0Level IshSpiCsPadTermination SataP0T3M Usb3HsioTxRate0UniqTranEnable SataTestMode PmcOsIdleEnable PowerLimit4 PcieRpAcsEnabled PavpEnable UsbTcPortEn Additionally, optimize the `reserved` fields across header files. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I976a5762701711fbf000c43c5ff05f9bd93f688f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-23vc/intel/fsp/mtl: Update header files from 2173_00 to 2222_01 for MTLSrinidhi N Kaushik
Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00. FSPM: Includes below 2 UPDs 1. TdcEnable 2. TdcTimeWindow FSPS: Address Offset changes. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-09vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor LakeSrinidhi N Kaushik
Add header files generated from FSP 2173_00 source build for Meteor Lake platform. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-07vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3172Bora Guvendik
The headers added are generated as per FSP v3172 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I5aa0611b19bb4f6667a95d2539cc2d17de6dcf07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3127_05_8Bora Guvendik
The headers added are generated as per FSP v3127_05_8. In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I9dd14468ec09bfe1a0904686e66d37a7389efdd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-04-27soc/intel/jasperlake: Revert CdClock settingSimon Yang
Revert CdClock setting and use default value 0xff. Previous problem was fixed by Jasperlake FSP in version 1.3.09.31, so we can use the original CdClock setting in baseboard. BUG=b:206557434 BRANCH=dedede TEST="Built and verified on magolor platform to confirm FSP solution works" Cq-Depend: chrome-internal:4662167 Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-31vendorcode/intel: Remove UDK2015 headersPatrick Rudolph
The headers are now unused, drop them. Change-Id: Ibfaa3029ddc614935481ce736c9d971bf4831b5d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-18vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elementsSubrata Banik
Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. Change request here:https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. BUG=b:200113959 TEST=Verified on Meteor Lake platform, without any compilation error Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00Ronak Kanabar
The headers added are generated as per FSP v3091_00 Previous FSP version was v2511_04 Changes include: - Update MemInfoHob.h BUG=b:222415800 BRANCH=None Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-22vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02Ronak Kanabar
The headers added are generated as per FSP v3054.02. Previous FSP version was v2503_00. Changes Include: - UPD Offset Update in FspmUpd.h BUG=b:220076892 BRANCH=None TEST=Build and boot adlnrvp Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-16vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar
The headers added are generated as per Alder Lake N FSP v2503_00. Previous FSP version was v2503_00. Change include: Add following Emmc UPDs in Fsps.h - ScsEmmcEnabled - ScsEmmcHs400Enabled - EmmcUseCustomDlls - EmmcTxCmdDelayRegValue - EmmcTxDataDelay1RegValue - EmmcTxDataDelay2RegValue - EmmcRxCmdDataDelay1RegValue - EmmcRxCmdDataDelay2RegValue - EmmcRxStrobeDelayRegValue BUG=b:213828776 BRANCH=None Change-Id: I617673a0cb12e7165f2f63cce73fff38bc7bf827 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-09vendorcode/intel/fsp: Add FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar
The headers added are generated as per Alder Lake N FSP v2503_00. Changes include: - Add all header files for Alder Lake N FSP. - List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h, FspUpd.h, MemInfoHob.h - Select FSP_HEADER_PATH BUG=b:213828776 BRANCH=None Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro
The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-01vendorcode/intel/fsp/elkhartlake: Drop obsolete headersFelix Singer
Elkhart Lake was hooked up to the FSP repo with commit 79fcadb3c46 (soc/intel/elkhartlake: Use FSP from FSP repo by default) making these headers obsolete. Thus, drop them. Change-Id: I2d6a4d4614ae21d5b8e77eceb85baa13e491c2ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-01soc/intel/jasperlake: Add CdClock frequency configSimon Yang
Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-26Revert "Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP ↵Tim Wawrzynczak
v2471_02"" This reverts commit a4dddfc3a3a48727ebcec727a0b1fd87eb4c14ad. Reason for revert: Ready to land FSP 2471.02 Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-12-21Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"Nick Vaccaro
This reverts commit ae0ea32c52905d6bcb527b04727463bc2d1b9e09. This change should not have merged until the 2471_02 FSP change is ready for merge. BUG=b:211481222 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0 to kernel. Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02Ronak Kanabar
The headers added are generated as per FSP v2471_02. Previous FSP version was v2422_01. Changes Include: - UPDs description update in FspsUpd.h - Adjust UPD Offset in FspmUpd.h and FspsUpd.h BUG=b:208336249 BRANCH=None TEST=Build and boot brya Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-12-11vendorcode/intel: Add edk2-stable202111 supportSubrata Banik
This patch includes (edk2/edk2-stable202111) all required headers for edk2-stable202111 EDK2 tag from EDK2 github project using below command: >> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification. - Need to add ExtendedImageRevision in FSP_INFO_HEADER structure. - Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header. Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-12-10vendorcode/intel: Rework UDK binding KconfigSubrata Banik
coreboot code currently supports different UDK binding as per underlying FSP requirement, example: ICL and TGL uses UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig. These UDK binding Kconfigs are being used to choose the correct UDK_VERSION. This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION if clause don't need to add specific UDK binding Kconfig everytime with introduction of newer UDK bindings in future. Tested with BUILD_TIMELESS=1, Hatch remains identical. Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68 Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01Ronak Kanabar
The headers added are generated as per FSP v2422_01. Previous FSP version was v2374_01. Changes Include: - Add CnviDdrRfim UPD in FspmUpd.h - UPDs description update in FspmUpd.h BUG=b:205512463 BRANCH=None TEST=Build and boot brya Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2374_01Ronak Kanabar
The headers added are generated as per FSP v2374_01. Previous FSP version was v2347_00. Changes Include: - Offset change in FspmUpd.h and FspsUpd.h BUG=b:201239436 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4150766 Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23soc/intel/xeon_sp/cpx: Use FSP repoArthur Heymans
Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPPArthur Heymans
coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-10vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2347_00Ronak Kanabar
The headers added are generated as per FSP v2347_00. Previous FSP version was v2265_01. Changes include: - UserBd UPD description update in FspmUpd.h BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I5e4dd58e5fb1a744b035a4de96986053a02610d3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-30vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01Ronak Kanabar
The headers added are generated as per FSP v2265_01. Previous FSP version was v2237_00. Changes Include: - Add Irms UPD in FspsUpd.h - Adjust Reserved UPD Offset in FspsUpd.h - Few UPDs description update in FspmUpd.h BUG=b:194032028 BRANCH=None TEST=Build and boot brya Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f Cq-Depend:chrome-internal:4004482 Cq-Depend:chrome-internal:4003608 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai
Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00Ronak Kanabar
The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-26vendorcode/intel/fsp: Remove deprecated headerRonak Kanabar
FirmwareVersionInfoHob.h is removed in JSL FSP v2376 so remove it from Jasper Lake vendorcode. BUG=b:153038236 BRANCH=None TEST=Verify JSLRVP build with all the patch in relation chain and verify the version output prints no junk data observed. couple of lines from logs are as below. Display FSP Version Info HOB Reference Code - CPU = 8.7.16.10 uCode Version = 0.0.0.1 Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45908 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.hRonak Kanabar
Update MdePkg/Include/IndustryStandard/SmBios.h to avoid compilation errors through safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2 Kconfig. BUG=b:153038236 BRANCH=None TEST=Verify JSLRVP build with all the patches in relation chain and verify the version output prints no junk data observed. Couple of lines from logs are as below. Display FSP Version Info HOB Reference Code - CPU = 8.7.16.10 uCode Version = 0.0.0.1 Change-Id: I9698861be1f969ddca7f171767a54ac486502c74 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45906 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01Ronak Kanabar
The headers added are generated as per FSP v2207_01. Previous FSP version was v2162_00. Changes Include: - Add IbeccProtectedRangeEnable, IbeccProtectedRangeBase and IbeccProtectedRangeMask in FspmUpd.h - Add UsbTcPortEn in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:189731004 BRANCH=None TEST=Build and boot brya Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Cq-Depend: chrome-internal:3876956, chrome-internal:3909162, chrome-internal:3909163 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55094 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai
Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-10vc/intel/fsp2_0/tigerlake: Remove unused headersFelix Singer
These headers are unused since CB:48713. Therefore, remove them. Change-Id: Id1bd074015769a33d98bb83134eb56b9de281d20 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48714 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger LakeSrinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v3162Tan, Lean Sheng
The FSP-M/S/T related headers added are generated as per FSP v3162. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ie6e6db704bcf86034fc9a3423101f0391ba2327e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54869 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar
The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2117_00Ronak Kanabar
The headers added are generated as per FSP v2117_00. Previous FSP version was v2081_02. Changes Include: - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:184129128 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b Cq-Depend: TBD Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-15vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v4133Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4133. Previous version was 4043. BUG=b:185463045 BRANCH=none TEST=build and boot voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I27d8f7783a944bdd21e3615799b1342ffb0edd22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-10vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v4043Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4043. Previous version was 3444. BUG=b:178846052 BRANCH=none TEST=none Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibada380fe757d9a8b50b2ddfeb2c86b4a98cb5e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-06vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packedDeomid "rojer" Ryabkov
It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP but won't be fixed for CPX. This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200 Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-23vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar
The headers added are generated as per FSP v2081_02. Previous FSP version was v2081_02. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add UPDs in Fsps.h and Fspm.h BUG=b:180918805 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15vc/intel/fsp/fsp2_0/cooperlake_sp: Update memory map hob for WW06 FSPJohnny Lin
Change-Id: Id534e1b73e73bbb9d944c988d1ef66bc1f463eff Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50867 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar
The headers added are generated as per FSP v2081_02. Previous FSP version was v2037. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h BUG=b:180758116 BRANCH=None TEST=Build and boot ADLRVP Cq-Depend: chrome-internal:3669105 Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2037Ronak Kanabar
The headers added are generated as per FSP v2037. Previous FSP version was v2037. Changes Include: - add BootFrequency, RMTBIT, RmtPerTask, RMTLoopCount and MrcFastBoot UPDs in Fspm.h - add EnableFastMsrHwpReq, VbtSize, CpuPcieComplianceTestMode, LidStatus and PcieComplianceTestMode UPDs in Fsps.h BUG=b:178461282,b:180627057 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I5496dfebc7b65a94abb31244ef2b400d89d6d444 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50914 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
CrashLog is a diagnostic feature for Intel TGL based platforms. It is meant to capture the state of the platform before a crash. The state of relevant registers is preserved across a warm reset. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17vc/intel/fsp: Change line endings to unixMartin Roth
These files have windows line endings. Change to unix to match the rest of the tree. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17treewide: Remove trailing whitespaceMartin Roth
Remove trailing whitespace in files that aren't typically checked. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8dfffbdeaadfa694fef0404719643803df601065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-04vendorcode/intel/Makefile: Add x86_64 supportPatrick Rudolph
This allows to compile FSP related tools (like the FSP loader) in x86_64 mode, but it doesn't add support for properly running x86_32 FSP on x86_64. This is handled in a separate patch. Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.hSubrata Banik
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. BUG=b:178846328 Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang
According to Tigerlake TDP specifications (doc #575683, table 4-2), TGL supports different TDP levels depends on CPU segement/package, IA Cores and graphics configuration. For example, UP3 4-Core GT2 suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable TDP-Down_2=12W. This configurable value can be used to select suitable TDP level Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-03vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037Subrata Banik
List of changes: 1. FSP-M Header: - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11{soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer
Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11vc/intel/FSP2_0/CPX-SP: update to FSP ww01 releaseJonathan Zhang
With Intel CPX-SP FSP ww01 release, CidBitMap field is added to DimmDevice struct in hob_memmap.h. The copyright statements were updated to accomodate year 2021. gpio_fsp.h is not needed any more as coreboot takes over GPIO configuration. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11vendorcode/intel/fsp: Update Tiger Lake v3444 FSP HeadersSrinidhi N Kaushik
Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-09vc/intel/fsp1_1/skylake: Remove unused header fileFelix Singer
Change-Id: I329a1484cbd16296a2aa047876c2506c74d4452d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-23vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1514_11Subrata Banik
List of changes: FSP-S Header: - Add UPD MicrocodeRegionBase and MicrocodeRegionSize - Adjust UPD Offset for Reservedxx Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2020-12-18vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11Subrata Banik
List of changes: FSP-S Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45 Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-07vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOBJohnny Lin
Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-02vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341Tan, Lean Sheng
The FSP-M/S/T related headers added are generated as per FSP v2341. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I98f738402490b47efa1a346f81db47857e384e13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-02vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04Ronak Kanabar
The headers added are generated as per FSP v2385_04. Previous FSP version was 2385_02. Changes Include: - add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and RampDown UPDs in Fsps.h BUG=b:174330941 BRANCH=dedede TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3438485 Change-Id: I477af05c34f767a43990670a711992641eaf6000 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47862 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-26vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11Subrata Banik
List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11Subrata Banik
List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20vc/intel/fsp2/denverton_ns: Remove unused filesFelix Singer
The Denverton-NS SoC uses the header files from the FSP git repository. Therefore, remove these from coreboot source. Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field inTim Chu
SystemMemoryMapHob This field from SystemMemoryMapHob can be used to define error correction type in SMBIOS type 16. Tested=On OCP Delta Lake, the value is expected. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02Ronak Kanabar
The headers added are generated as per FSP v2385_02. Previous FSP version was 2376. Changes Include: - add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h TEST=Build and boot JSLRVP Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatchJohnny Lin
Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-15vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425. BUG=b:173160613 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3403586, chrome-internal:3403392 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454Subrata Banik
List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark optionJonathan Zhang
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-02vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373. BUG=b:172045149 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3373431 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432Subrata Banik
List of changes: 1. FSP-M Header: - Add new UPD GpioOverride - Change help text for PlatformDebugConsent UPD - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust Reservedxx UPD Offset - PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew by 4 elements Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376Ronak Kanabar
The headers added are generated as per FSP v2376. Previous FSP version was 2295. Changes Include: - add GpioOverride UPD in Fspm.h - add new header FirmwareVersionInfo.h Cq-Depend: TBD Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45899 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01Subrata Banik
List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3373. Previous version was 3333. Changes include below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp Cq-Depend:chrome-internal:3308203, chrome-internal:3308204 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45630 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fieldsJohnny Lin
The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17. Tested=On OCP Delta Lake, verify the values are expected. Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 releaseJonathan Zhang
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs. Update FspmUpd.h and HOB header files. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP releaseJonathan Zhang
Intel CPX-SP FSP ww38 release made some changes to FSP-M header file. Those changes do not need corresponding soc code change. TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake DVT to target OS. Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header fileJonathan Zhang
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating error status registered (such as MCA MSRs) to list fatal errors happened during the previous boot session. The header file supports 3 different error source types. CPX-SP FSP supports only McBankType. Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issueSubrata Banik
FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h) hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing compilation issue. Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-09vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332Subrata Banik
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-08vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM definition in SystemMemoryMapHobJohnny Lin
Most of them are needed for SMBIOS type 17 creation. Tested=With FSP WW36 verified the printed hob values match with FSP hob data. Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08vendorcode/intel/FSP2_0/CPX-SP: update to ww36Jonathan Zhang
Intel CPX-SP FSP ww36 release has following changes: * Update FSP header version to change among FSP releases. * Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11 (OEM strings) generation. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08vendorcode/intel/fsp/fsp2_0/cpx_sp: Set correct stack number for IOU3Johnny Lin
PSTACK2 (IOU3) should be stack number 4, mainboard uses stack number as the index to access the bus number array read by get_stack_busnos(). Without the fix it would get the wrong bus number (0xb1). Tested=On OCP Delta Lake, dmidecode -t 9 to verify slots bus number on IOU3 are correct (0xb2). Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3333. Previous version was 3313. Changes Include: 1. Update comments 2. Add new UPD for Gpio Override support BUG=b:166790597 BRANCH=none TEST=build and boot volteer proto2 Cq-Depend:chromium-internal:3240396,chromium-internal:2870145 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-25vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2295. Previous FSP version was 2194. Changes Include: - Update comments - UPD offset updates - add FSPS_ARCH_UPD BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 04:54:57 +0000