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2019-08-09src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1263Aamir Bohra
Change-Id: Ia29769f1fc9947d9e37de2534c9486d21a4c9eae Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09vendorcode/intel/../icelake: Update ICL FSP header BIOS version 3092Subrata Banik
After building from here : https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/icl/+/refs/tags/upstream/BIOS_Version_3092 Change-Id: I8924dbf4a8d6a303540ced1c9c48586d26d6beaa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-04-04Make common macros double-evaluation safeJulius Werner
I just got hit by a double-evaluation bug again, it's time to attempt to fix this once more. Unfortunately there are several issues that don't make this easy: - bitfield variables don't support typeof() - local macro variables that shadow others trigger -Werror=shadow - sign warnings with integer literal and unsigned var in typeof-MIN() - ({ statement expressions }) can not be used outside functions - romcc doesn't support any of the fancy GCC/clang extensions This patch tries to address all of them as far as possible with macro magic. We don't have the technology to solve the bitfield and non-function context issues yet (__builtin_choose_expr() still throws a "no statement expression outside a function" error if it's only in the branch that's not chosen, unfortunately), so we'll have to provide alternative macros for use in those cases (and we'll avoid making __ALIGN_MASK() double-evaluation safe for now, since it would be annoying to do that there and having an alignment mask with side effects seems very unlikely). romcc can continue using unsafe versions since we're hopefully not writing a lot of new code for it. Sign warnings can be avoided in literal/variable comparisons by always using the type of the variable there. Shadowing is avoided by picking very explicit local variable names and using a special __COUNTER__ solution for MIN() and MAX() (the only ones of these you're likely to nest). Also add DIV_ROUND_UP() to libpayload since it's a generally quite useful thing to have. Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-15vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for CannonlakeJohn Zhao
Update FSP header files for Cannonlake platform. Change-Id: I7f1a1f61c32510062a440c14a897e95bed7a9718 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-12vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeRonak Kanabar
Update header files for FSP for cometlake platform version 1065 BUG=b:125439832 Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-06vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeSubrata Banik
Update header files for FSP for cometlake platform version 1065 Change-Id: I7be7535975b442490cc77c9c1dca4ef7a2d43a58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-02-28vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for CometlakeMaulik V Vaghela
Adding header files for FSP for cometlake platform version 1034 Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-11mb/intel/galileo: Drop the FSP1.1 optionArthur Heymans
This board is EOL and has FSP2.0 support, so drop the older version. Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-30soc/intel/apollolake: Sync fsp upd structure updateJohn Zhao
FSP 2.0.9 provides UPD interface to adjust integrated filter value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd structure to sync with fsp 2.0.9 release. BUG=b:123398358 CQ-DEPEND=CL:*817128 TEST=Verified yorp boots to kernel. Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/31131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-17vendorcode/{amd,cavium,intel}: Remove trailing whitespacePeter Lemenkov
find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \; Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30959 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15vendorcode/intel/fsp1_0/broadwell_de: Use FSP from 3rdparty/fspPatrick Rudolph
Default to FSP binary and headers shiped in 3rdparty/fsp. * Drop headers and code from vendorcode/intel/fsp1_0/broadwell_de * Select HAVE_FSP_BIN to build test the platform * Fetch FSP repo as submodule * Make FSP_HEADER_PATH known from FSP2.0 useable on FSP1.0 * Introduce FSP_SRC_PATH for FSP source file * Add sane defaults for FSP_FILE Tested on wedge100s. Change-Id: I46f201218d19cf34c43a04f57458f474d8c3340d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-14[RFC]util/checklist: Remove this functionalityArthur Heymans
It was only hooked up for galileo board when using the obsolete FSP1.1. I don't see how it can be useful... Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30691 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18Fix typos involving "the the"Jonathan Neuschäfer
Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-23soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-19northbridge/intel/fsp_*: Remove legacy SoCszaolin
* Remove FSP Sandy/Ivybrige which are unused. * Open Source implementation isn't final but good enough to replace FSP version. * For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE and NORTHBRIDGE_INTEL_SANDYBRIDGE Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29402 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08soc/intel/apollolake: Improve cold boot and S3 resumeJohn Zhao
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-26vendorcode/intel/fsp/icelake: Add icelake FSP header file templateRizwan Qureshi
icelake FSP is still under development and hence the FSP header files and binaries are not available on github. Meanwhile add basic header files required to compile the SoC and mainboard with FSP2.0. BUG=None BRANCH=None TEST=Build for icelake_rvp board successfull. Change-Id: I9ab8f180b572ec553e7531f7483d091f6897c462 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/29163 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24intel/fsp: Fix license header for MeminfoHob.hLijian Zhao
Current header file included a proprietary license, fix that by using same license shared on public fsp release on fsp. BUG=https://ticket.coreboot.org/issues/177 TEST=N/A Change-Id: I129c8a465e702d3885d994f4fab352b34d46f177 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Kelling <ian@iankelling.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23src: Typo fix (cosmetic)Peter Lemenkov
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28fsp/fsp2_0/coffeelake: Update CFL FSP headersLijian Zhao
Coffeelake FSP headers had been updated to version 7.0.3D.60. Original file location from https://github.com/IntelFsp/FSP/tree/master/ CoffeeLakeFspBinPkg/Include . BUG=N/A TEST=Build and flash, able to boot up into OS on whiskeylake rvp platform. Change-Id: I656da83e9042642576b785643e423ba47da8dd73 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28286 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt ConfigKane Chen
From doc 571118, the bit 5 of OdtConfig is nWR config. If the bit 5 is set, MRC will set MR1 nWR field to 24. If the bit 5 is clear, MRC will set MR1 nWR field to 6. Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/27814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5John Zhao
Update FSP header files to match FSP Reference Code Release v2.0.5 for Geminilake BUG=b:111683980 CQ-DEPEND=CL:*653835 Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.3 for Gemimilake CQ-DEPEND=CL:*627827 Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26285 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18intel/fsp: Update Cannonlake FSP headerLijian Zhao
Update Cannonlake FSP header to version 7.x.2E.50, the following changes were made, Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 2. Remove Fixed mid option for SaGv. 3. Add DualDimm per channel board type. 4. Remove PEG IMR options. Silicon Init UPD: 1. Add CD clock selections of 675MHz. 2. Remove Pcode PreWake/Rampup/RampDn time selections. 3. Remove C3 state demotion/unDemotion selections. BUG=None TEST=Build and boot up on meowth platform. Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26148 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.2 for Gemimilake CQ-DEPEND=CL:*594651,CL:*598345 Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD HeadersNg Kin Wai
Header files based on FSP 7.0.25.34 BUG=none BRANCH=none TEST=built coreboot without build error. Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com> Reviewed-on: https://review.coreboot.org/25335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-04-05intel/fsp: Update cannonlake fsp headerLijian Zhao
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17 Offset 15h Speed report incorrectly issue. BUG=None TEST=Boot up with meowth platform and run dmidecode to see two dimm entries under Type 17. Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25378 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23vendorcode/intel: Update FSP Header files per v2.0.0Srinidhi N Kaushik
Update FSP header files to match GLK FSP Reference Code Release v2.0.0 Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-22intel/fsp: Update Cannonlake FSP headerLijian Zhao
Update Cannonlake FSP header to version 7.x.2A.20, the following changes were made: 1. Add MemtestonWarmBoot option. 2. Add enable8254clockgatingonS3 option. 3. Default disable Tccoffsetlock BUG=None TEST=None Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-14intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Reviewed-on: https://review.coreboot.org/23677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31vendorcode/intel/fsp/fsp2_0: Add CannonLake FirmwareVersionInfoHob headerSubrata Banik
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot platform using CannonLake FSP new feature. Expectation is that, FSP will provide version information of all Firmware ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code, CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version, PCH Ref Code version etc.) Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.20.52. Following changes had been made: 1. Hide internal EV related options. 2. Add GT voltage override options. 3. Add PEG IMR selection. 4. Add PCH DMI ASPM options. TEST=NONE Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31vendorcode/intel/fsp: Remove TODOs and make use of EDK2 headerSubrata Banik
This patch ensures MemInfoHob.h file can make use of existing UEFI headers as is rather than redefining the same structure locally. TEST=Download BIOS_Version_122.3 from external github and build MemInfoHob.h without any compilation error. Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add Kconfig option to get UDK_VERSIONSubrata Banik
This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform. Change-Id: I3120ce512255ed6f2a40413e8e6d8000c7285b39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add UDK2017 supportSubrata Banik
This patch includes (edk2/UDK2017) all required headers for UDK2017 from EDK2 github project using below command >> git clone https://github.com/tianocore/edk2.git vUDK2017 commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47 Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-05vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v77_12Srinidhi N Kaushik
Update FSP header files to match FSP v77_12 Following fields have been added in FSP-S UPD: - SkipPunitInit (Skip P-unit Initialization) - HgSubSystemId (Sub system Vendor ID VGA) Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22820 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-22vendor/intel/skykabylake: Update FSP header files to version 2.9.2Balaji Manigandan B
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source(s) of PCIe Root Ports. This UPD is used to disable clock source(s) of disabled PCIe Root Port which has active device connected. CQ-DEPEND=CL:*520658,CL:*520659 BUG=b: BRANCH=None TEST= Build and boot soraka Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/22692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-09soc/intel/skylake: add acoustic noise mitigation params for FSP 1.1Matt DeVillier
Adapted from Chromium commit d6655eb [Skylake: create UPD Interface for acoustic noise tuning] Add FSP 1.1 params needed for acoustic mitigation on google/caroline (to be upstreamed in a subsequent commit). TEST: build/boot google/caroline Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51Ravi Sarawadi
Update FSP header files to match FSP v69_51. UPD updates in FSP v69_51 are: - SGX Epoch - Sub/System Vendor ID - Remove deprecated UPD Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/22391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-11intel/fsp: Update cannonlake FSP headerLijian Zhao
Update cannonlake FSP header to revision 7.x.11.43. Following changes had been made: 1.Remove Minimum control ration from FSPM UPD. 2.Add Intersil VR command option in FSPS UPD. 3.Add minimum and maxiam ring ratio override. TEST=None Change-Id: I63c990e5766370a82dc1c044bcf744612229a605 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19intel/fsp: Update cannonlake FSP headerLijian Zhao
Update cannonlake FSP header file to revision 7.x.15.46. The following item had been updated: 1. Remove/Hide restricted structure. 2. Add EBR as extention of RMT features. 3. Add cpu wakeup timer UPD. 4. Remove XHCI access lock UPD. TEST=NONE Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05vendor/intel/skykabylake: Update FSP header files to version 2.7.2Balaji Manigandan B
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-04intel/fsp: Update cannonlake FSP headerLijian Zhao
Update FSP header file to latest version, cannonlake reference code 7.0.14.11. Details of FSP changes can be find in FSP release notes. Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0Martin Roth
Cherry-pick from Chromium 414024e. Update the FSP 1.1 header to version 1.1.7.0, required for susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices. As this header update doesn't shift offsets, only adds new fields in previously unused/reserved space, it should not negatively impact existing boards built against the older header version. Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020 Original-Signed-off-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Tested-by: Martin Roth <martinroth@chromium.org> Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22vendorcode/intel/fsp/fsp2_0/denverton_ns: Add FSP header files for ↵Mariusz Szafranski
Denverton_NS SoC This change adds the FSP header files for FSP version 2.0 (15D50) for the Intel Denverton_NS SoC. Change-Id: I9672610df09089c549e74072345781bea0b4d06f Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-07-26vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v52_27Ravi Sarawadi
Update glk header files as per v52_27 FSP code. Change-Id: I8e313a2b854e60b1ad8a5c6e080641e323de56a8 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25vendercode/intel/fsp/skykabylake: Add new UPD SpiFlashCfgLockDownBarnali Sarkar
A new UPD named SpiFlashCfgLockDown is added in the FSP-S header file. This change is going to come in FSP in the next FSP release. This patch is pushed to urgently fix the SPI FPR locking issue. CQ-DEPEND=CL:*414049 BUG=b:63049493 BRANCH=none TEST=Built and boot poppy Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18KBL: Update FSP headers - upgrade to FSP 2.5.0Balaji Manigandan B
Additional UPDs included with FSP 2.5.0: FspsUpd.h: *SataRstOptaneMemory *Additional Upds for Core Ratio limit FspmUpd.h: *RingDownBin *PcdDebugInterfaceFlags *PcdSerialDebugBaudRate *PcdSerialDebugLevel *GtPllVoltageOffset *RingPllVoltageOffset *SaPllVoltageOffset *McPllVoltageOffset *RealtimeMemoryTiming *EvLoader *Avx3RatioOffset CQ-DEPEND=CL:*388108,CL:*388109 BUG=None BRANCH=None TEST=Build and test on Soraka Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Change-Id: Id31ddd4595e36c91ba7c888688114c4dbe4db86a Reviewed-on: https://review.coreboot.org/20123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12vendorcode/intel: Add initial FSP headers for CannonlakeAndrey Petrov
Intial FSP headers with FSP version 1.5.30 Change-Id: I4471c6aa40ff23179b033a873aec1887b8b4370e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-12vendorcode/intel/fsp/fsp2_0/glk: Add FSP header files for GLKHannah Williams
from FSP release V030_61 Change-Id: I5ecba08de851ee2e362f9ac31e1fa8bf3dfceebb Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19605 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-04-07KBL: Update FSP headers - upgrade to FSP 2.0.0Balaji Manigandan B
Updating headers corresponding to FSP 2.0.0 Below UPDs are added to FspmUpd.h * PeciC10Reset * PeciSxReset rest of the changes are update to comments CQ-DEPEND=CL:*340004,CL:*340005,CL:*340006 BUG=None BRANCH=None TEST=Build and test on Poppy Change-Id: Id8ecea6fa5f4e7a72410f8da535ab9c4808b3482 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/19109 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01src/vendorcode: Add Memory Info Data HOB HeaderBarnali Sarkar
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the MEM_INFO_DATA_HOB. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-08vendorcode/intel/skykabylake: Update FSP UPD header filesAamir Bohra
Update FSP UPD header files as per version 1.6.0. Below UPDs are added to FspsUpd.h: * DelayUsbPdoProgramming * MeUnconfigIsValid * CpuS3ResumeDataSize * CpuS3ResumeData CQ-DEPEND=CL:*322871,CL:*323186,CL:*322870 BUG=None BRANCH=None TEST=Build and boot on RVP3 and poppy Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/18289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-08vendorcode/intel/skykabylake: Update CpuConfigFspData.h fileBarnali Sarkar
The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=chrome-os-partner:61548 BRANCH=none TEST=Built and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18285 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-14apollolake: Update UPD header files for FSP 1.3.0Brandon Breitenstein
These updated header files contain USB tuning parameters as well as some general cleanup of unused parameters in the UPD Headers. This patch along with the upcoming FSP 1.3.0 release will allow for USB tuning on apollolake platforms. CQ-DEPEND=CL:*315403 BUG=chrome-os-partner:61031 Change-Id: Id7cce1ea83057630d508523ada18c5425804535e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/18046 Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30vendorcode/skykabylake: Update header to fsp v1.4.0Naresh G Solanki
Add header files as is from FSP build output without any adaptations. Change-Id: Ic4b33c42efe8c9dbe9f9e2b11bf6344c9487d86e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17556 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30vendorcode/intel: Update apollolake UPD headers to SIC 1.2.3 releaseBrandon Breitenstein
This header update contains updates for skipping punit as well as some MRC related UPD values. BUG=chrome-os-partner:60068 BRANCH=none TEST=built with FSP 1.2.3 and MRC patches for coreboot CQ-DEPEND=CL:*307357 Change-Id: I8c66c0c0febba5e67ae3290034e9b095c9e68f07 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/17631 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-07vendorcode/intel/fsp: Update UPD headers for FSP 157_10Brandon Breitenstein
These header files contain a few new UPDs. The EnableS3Heci2 UPD will be used to save ~100ms from the S3 resume time on Apollolake chrome platforms. BUG=chrome-os-partner:58121 BRANCH=none TEST=built coreboot for reef and verified no regressions Change-Id: I1f324d00237c7150697800258a2f7b7eed856417 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30mainboard/intel/quark: Add FSP selection valuesLee Leahy
Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12vendorcode/skylake: Add FSP header files without any adaptationsRizwan Qureshi
Add header files as is from FSP build output. Move the FSP header files to new location as in apollolake. Update all the FSP structure references now that they are typedef'd. Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16517 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06vendorcode/intel/Makefile.inc: Remove extraneous underscoreMartin Roth
Commit e96543e1 (vendorcode/intel: Add UDK 2015 Bindings) had an extra underscore at the end of one of the make lines that we missed in the review. Remove it. Fixes this build warning: .../Makefile.inc:34: Extraneous text after `ifeq' directive Change-Id: I0bc76d827207b4f641ac5ff08f540a114347533b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16411 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-09-02apollolake: relocate fsp header files to vendorcodeBrandon Breitenstein
FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02vendorcode/intel: Add UDK 2015 BindingsRizwan Qureshi
Add UDK 2015 Bindings for FSP header compatibility. These bindings add the necessary code to read FSP Headers without any modifications from FSP Source. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image and verified boot Change-Id: I2887f55b6e63cd0a2b2add9a521be9cfaf875e7d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16307 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11vendorcode/intel/fsp: Add fsp 2.0 header files for skylake and kabylakeRizwan Qureshi
Add FSP 2.0 header files, these files are common for Skylake and Kabylake, name the folder as skykabylake to signify the same. Change-Id: I71b43a59c9a9b0adf1ee48285e4a72e24a13df2d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-10soc/intel/quark: Switch to using serial routines for FSPLee Leahy
Switch from passing FSP the serial port address to passing FSP the serial port output routine. This enables coreboot to use any UART in the system and also log the FSP output. TEST=Build and run on Galileo Gen2 Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-09soc/intel/quark: Remove TODO message from FspUpdVpd.hLee Leahy
Remove the TODO message from FspUpdVpd.h TEST=Build and run on Galileo Gen2 Change-Id: Icd565c6062ef59b1e4a68310bb6f9ed62fb014af Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16114 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-08soc/intel/quark: Pass in the memory initialization parametersLee Leahy
Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09util/checklist: Add bootblock supportLee Leahy
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK selected. TEST=Build and run with Galileo Gen2 Change-Id: I922f761c31e95efde0975d8572c47084b91b2879 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15130 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09vendorcode/intel/fsp1_1/checklist: romstage - Add car_stage_entryLee Leahy
Add car_stage_entry as an optional routine in the checklist. TEST=Build and run on Galileo Gen2 Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09soc/intel/quark: Pass serial port address to FSPLee Leahy
Pass the serial port address to FSP using a UPD value in the MemoryInit API. TEST=Build and run on Galileo Gen2 Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15079 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03Add Board Checklist SupportLee Leahy
Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-13vendorcode/intel/fsp1_0: Don't break GCC strict aliasingStefan Reinauer
Change-Id: I6b345670db7df652b8b712b721dfe2905373e0d5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14630 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-05-13HobLib: Don't break GCC strict aliasingStefan Reinauer
Change-Id: I1bd33e423b0fcb69597e001b61c6ea916f5fe44a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14622 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-03vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.hLee Leahy
Update the file to match the QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: I090578d32165d34863548aec0e4a38fe915683c6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14452 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-18vendorcode/intel: Remove temporary Broadwell DE Kconfig symbolMartin Roth
This symbol was added to fix a Kconfig lint error after the Broadwell DE vendorcode was added. Now that the chipset's in the codebase, it's no longer needed. Change-Id: Iedb166129c9265cc2cfcc406d98bde92c1a82d2f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14384 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-03-15vendorcode/intel/Kconfig: Add broadwell_de symbol to fix lintMartin Roth
The Kconfig lint tool is complaining because this symbol doesn't exist. Create a temporary definition that can be removed when the chipset is added. Change-Id: I6a8abffcc91773aae16721ee1f48c4c64bd6b486 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14091 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-14vendorcode/intel/fsp1_0: Add Broadwell-DE SoC vendor codeYork Yang
Initial vendor codes to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I9262c9d70a58f0c7427f0658948adf080f2f6d8f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14030 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0Aaron Durbin
The previous copy of FspUpdVpd.h was not up to date w.r.t. the FSP release being used for skylake boards. Fix that. BUG=chrome-os-partner:50863 BRANCH=None TEST=Built and booted on chell. Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7 Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331290 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13984 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/quark: Set the UPD values for MemoryInitLee Leahy
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-10soc/fsp_baytrail: Add support for FSP MR 005Ben Gardner
Baytrail FSP MR 005 adds two new fields: AutoSelfRefreshEnable APTaskTimeoutCnt Add the device tree definitions. Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12973 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-02-04soc/intel/quark: Add minimal Quark SoC X1000 filesLee Leahy
Add the files for minimal Quark X1000 SoC support: * Declare pei_data structure * Declare sleep states and chipset_power_state structure * Specify top of memory * Empty FspUpdVpd.h file TEST=None Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31vendorcode/intel: remove unused apple specific assembler macrosStefan Reinauer
Since this code is pulled in through commonlib, it will break compilation of cbfstool on OSX. Change-Id: I342bfa7e755aa540c4563bb5cd8cccacee39d188 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13525 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-27soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEnHannah Williams
Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16vendorcode/intel/.../skylake: Update FspUpdVpd.h to v1.8.1Martin Roth
This corresponds with the changes that have already gone into the soc/intel/skylake chip.h file and is needed to get skylake platforms building again. Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13022 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04braswell/skylake: Add FspUpdVpd.h to fix compilationStefan Reinauer
Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins)
2015-11-18fsp1_0: Update rangeley to revision POSTGOLD4Marcin Wojciechowski
Alignment of Intel Firmware Support Package 1.0 Rangeley header and source files to the revision: POSTGOLD4 Detail changelog can be found at http://www.intel.com/fsp FSP release date September 24, 2015 Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: http://review.coreboot.org/12418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10southbridge/intel: Add FSP based i89xx southbridge supportMarc Jones
The Intel i89xx is a communications chipset that pairs with Sandy(Ivy)bridge processors. It has a lot in common with the bd82x6x chipset, but fewer devices and options. Change-Id: I11bcd1edc80f72a1b2521def9be0d1bde5789a79 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12166 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
Please don't remove chipsets and mainboards without discussion and input from the owners. Someone was asking about cougar canyon 2 just a couple of weeks ago - there's obviously still interest. This reverts commit fb50124d22014742b6990a95df87a7a828e891b6. Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/12128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
This chip is still being used and should not have been deleted. It's a current intel chip, and doesn't even require an ME binary. This reverts commit 959478a763c16688d43752adbae2c76e7764da45. Change-Id: I78594871f87af6e882a245077b59727e15f8021a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11860 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
mohonpeak is the reference board for Rangeley. I doubt anyone uses it or cares about it. We jokingly refer to it as "Moron Peak". It's code with no known users, so we shouldn't be hauling it around for the eventuality that someone might use it in the future. Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11790 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
We already have two other code paths for this silicon. Maintaining the FSP path as well doesn't make much sense. There was only one board to use this code, and it's a reference board that I doubt anyone still owns or uses. Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11789 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-02fsp1_1: move relocation algorithm to commonlibAaron Durbin
In order to support FSP 1.1 relocation within cbfstool the relocation code needs to be moved into commonlib. To that end, move it. The FSP 1.1 relocation code binds to edk2 UEFI 2.4 types unconditionally which is separate from the FSP's version binding. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Ib2627d02af99092875ff885f7cb048f70ea73856 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11772 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-10fsp1_1: provide binding to UEFI versionAaron Durbin
FSP has some unique attributes which makes integration cumbersome: 1. FSP header files do not include the types they need. Like EDKII development it's expected types are provided by the build system. Therefore, one needs to include the proper files to avoid compilation issues. 2. An implementation of FSP for a chipset may use different versions of the UEFI PI spec implementation. EDKII is a proxy for all of UEFI specifications. In order to provide flexibility one needs to binding a set of types and structures from an UEFI PI implementation. 3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h file which defines it's own types. Commonality between FSP chipset implementations are only named typedef structs. The fields within are not consistent. And because of FSP's insistence on typedefs it makes it near impossible to forward declare structs. The above 3 means one needs to include the correct UEFI type bindings when working with FSP. The current implementation had the SoC picking include paths in the edk2 directory and using a bare <uefi_types.h> include. Also, with the prior fsp_util.h implementation the SoC's FSP FspUpdVpd.h header file was required since for providing all the types at once (Generic FSP 1.1 and SoC types). The binding has been changed in the following manner: 1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1 selects. No other bindings are currently available, but this provides the policy. 2. Based on CONFIG_UEFI_2_4_BINDING the proper include paths are added to the CPPFLAGS_common. 3. SoC Makefile.inc does not bind UEFI types nor does it adjust CPPFLAGS_common in any way. 4. Provide a include/fsp directory under fsp1_1 and expose src/drivers/intel/fsp1_1/include in the include path. This split can allow a version 2, for example, FSP to provide its own include files. Yes, that means there needs to be consistency in APIs, however that's not this patch. 5. Provide a way for code to differentiate the FSP spec types (fsp/api.h) from the chipset FSP types (fsp/soc_binding.h). This allows for code re-use that doesn't need the chipset types to be defined such as the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Signed-off-by: Aaron Durbin <adubin@chromium.org> Change-Id: I894165942cfe36936e186af5221efa810be8bb29 Reviewed-on: http://review.coreboot.org/11606 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2015-07-21intel/fsp_baytrail: Support Baytrail FSP Gold4 releaseYork Yang
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10838 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-15intel/fsp_baytrail: Remove PcdEnableLan optionYork Yang
Bay Trail SOCs do not integrate LAN controller hence Baytrail FSP has no LAN control function. Remove PcdEnableLan option from UPD_DATA_REGION structure. Change-Id: I9b4ec9d72c8c60b928a6d9755e94203fb90b658f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10837 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-08vendorcode/intel/edk2: Fix EFI_PEI_GRAPHICS_INFO_HOB structureLee Leahy
Change the FrameBufferSize field from UINT64 to UINT32 to match the Platform Initialization 2.4 specification. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I28dc0608675ed5840863ecd15bd2f57e6b2f4c1d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10834 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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