coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-05-29	UEFI: Conditionally define the ASSERT macro	Lee Leahy
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-30	vendorcode/intel: Add EDK2 header files	Lee Leahy
2015-04-29	vendorcode/intel: Add FSP 1.1 header files	Lee Leahy
2015-04-24	fsp: Move fsp to fsp1_0	Marc Jones
2015-01-31	intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP	York Yang
2015-01-13	vendorcode/intel: remove DebugDeadLoop() from fsptypes.h	Martin Roth
2014-12-01	Mark non-executable files non-executable	Patrick Georgi
2014-11-29	vendorcode/intel/fsp: Update FSP_VENDORCODE_HEADER_PATH	FEI WANG
2014-11-21	intel/fsp_baytrail: add Gold3 FSP support	York Yang
2014-08-11	vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files	Martin Roth
2014-08-01	vendorcode/intel/fsp/rangeley/include: Missing 'fsptypes.h'	Edward O'Callaghan
2014-07-08	vendorcode/intel: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-05-23	vendorcode/intel/fsp/rangeley: remove extra file	Martin Roth
2014-05-21	baytrail: Fix some minor errors in FSP	David Hendricks
2014-05-19	build: move include paths where they belong	Patrick Georgi
2014-05-06	Introduce stage-specific architecture for coreboot	Furquan Shaikh
2014-04-11	Add the Rangeley FSP include & srx directories	Martin Roth
2014-04-11	Add the Bay Trail FSP include & srx directories	Martin Roth
2014-04-11	Add the ivybridge i89xx FSP include & srx directories	Martin Roth
2014-04-11	Update vendorcode/intel/makefile for coming FSPs	Martin Roth
2013-12-07	Correct file permissions.	Idwer Vollering
2013-12-04	Add Intel FSP northbridge support Sandybridge and Ivybridge	Marc Jones