coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-03-08	soc/intel/quark: Set the UPD values for MemoryInit	Lee Leahy
2016-02-04	soc/intel/quark: Add minimal Quark SoC X1000 files	Lee Leahy
2016-01-27	soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn	Hannah Williams
2016-01-16	vendorcode/intel/.../skylake: Update FspUpdVpd.h to v1.8.1	Martin Roth
2015-12-04	braswell/skylake: Add FspUpdVpd.h to fix compilation	Stefan Reinauer
2015-10-02	fsp1_1: move relocation algorithm to commonlib	Aaron Durbin
2015-04-29	vendorcode/intel: Add FSP 1.1 header files	Lee Leahy
2015-04-24	fsp: Move fsp to fsp1_0	Marc Jones
2015-01-31	intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP	York Yang
2015-01-13	vendorcode/intel: remove DebugDeadLoop() from fsptypes.h	Martin Roth
2014-12-01	Mark non-executable files non-executable	Patrick Georgi
2014-11-21	intel/fsp_baytrail: add Gold3 FSP support	York Yang
2014-08-11	vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files	Martin Roth
2014-08-01	vendorcode/intel/fsp/rangeley/include: Missing 'fsptypes.h'	Edward O'Callaghan
2014-07-08	vendorcode/intel: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-05-23	vendorcode/intel/fsp/rangeley: remove extra file	Martin Roth
2014-05-21	baytrail: Fix some minor errors in FSP	David Hendricks
2014-04-11	Add the Rangeley FSP include & srx directories	Martin Roth
2014-04-11	Add the Bay Trail FSP include & srx directories	Martin Roth
2014-04-11	Add the ivybridge i89xx FSP include & srx directories	Martin Roth
2013-12-07	Correct file permissions.	Idwer Vollering
2013-12-04	Add Intel FSP northbridge support Sandybridge and Ivybridge	Marc Jones