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2020-06-12vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSP-M: SkipCpuReplacementCheck PCH HSIO Tuning UPDs FSP-S: PcieRpHotPlug TccActivationOffset TccOffsetClamp TccOffsetLock TccOffsetTimeWindowForRatl USB3 HSIO Tuning UPDs BUG=none BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib40d226dd2ecc4fb34965e1f2c416c53edef01d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSPS: ITbtConnectTopologyTimeoutInMs Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/42046 Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197, which includes below additional UPDs: FSPM: CmdMirror RMTBIT FSPS: SataPortsEnableDitoConfig BUG=b:157725468 BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41974 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3163, which includes below additional UPDs: FSPM: TcssDma0En TcssDma1En FSPS: PchFivrExtV1p05RailEnabledStates PchFivrExtV1p05RailSupportedVoltageStates PchFivrExtVnnRailEnabledStates PchFivrExtVnnRailSupportedVoltageStates PchFivrExtVnnRailSxVoltage PchFivrExtV1p05RailIccMaximum CstateLatencyControl5TimeUnit VmdEnable BUG=none BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icc893073629df59aef60162bed126d1f4b936e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41377 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3163. Which includes below additional UPDs: FSPM: -BootFrequency -SerialIoUartDebugMode FSPS: -PcieRpPmSci -PchPmWoWlanEnable -PchPmWoWlanDeepSxEnable -PchPmLanWakeFromDeepSx BUG=b:155315876 BRANCH=none TEST=build and boot ripto/volteer Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ida87ac7dd7f5fd7ee0459ae1037a8df816976083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40898 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 2527. Which includes below additional UPDs: FSPM: - PchTraceHubMode - CpuTraceHubMode - CpuPcieRpEnableMask FSPS: - D3HotEnable - D3ColdEnable - RtcMemoryLock - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchUnlockGpioPads - CpuMpPpi - ThcPort0Assignment - ThcPort1Assignment BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31vendorcode/intel/fsp: Update FSP header for Tiger LakeRonak Kanabar
Update FSPM header to include DisableDimmCh Upds for Tiger Lake platform version 2457. BUG=b:152000235 BRANCH=none TEST="Build and Boot on Ripto/Volteer" Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-09vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger LakeSrinidhi N Kaushik
Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-03vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger LakeSrinidhi N Kaushik
Update FSPM header to add Vtd related Upds for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-26vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger LakeRonak Kanabar
Update FSP header file for Tiger Lake platform version 2457. Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-25vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger LakeSrinidhi N Kaushik
Update FSP header files for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I47574844a8b5fd888e8e75ed2f60f6df465b33ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/38555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-12-26vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger LakeSubrata Banik
Add header files for FSP for Tiger Lake platform version 2457. Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-08 21:26:35 +0000