Age | Commit message (Collapse) | Author |
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Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs:
FSPM:
- PchTraceHubMode
- CpuTraceHubMode
- CpuPcieRpEnableMask
FSPS:
- D3HotEnable
- D3ColdEnable
- RtcMemoryLock
- PchLockDownGlobalSmi
- PchLockDownBiosInterface
- PchUnlockGpioPads
- CpuMpPpi
- ThcPort0Assignment
- ThcPort1Assignment
BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform
version 2457.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Update FSP header file for Tiger Lake platform version 2457.
Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD
Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update FSP header files for Tiger Lake platform version 2457.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I47574844a8b5fd888e8e75ed2f60f6df465b33ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Add header files for FSP for Tiger Lake platform version 2457.
Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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