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Update FSP header file to match GLK FSP v2.2.0
BUG=none
BRANCH=none
TEST=none
Change-Id: I515b4c44439e3404d3b06d587f0846457000fdb4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marx Wang <marx.wang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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FSP 2.0.9 provides UPD interface to adjust integrated filter
value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd
structure to sync with fsp 2.0.9 release.
BUG=b:123398358
CQ-DEPEND=CL:*817128
TEST=Verified yorp boots to kernel.
Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/31131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.
BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified system_resume_firmware_ec time reduction.
Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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From doc 571118, the bit 5 of OdtConfig is nWR config.
If the bit 5 is set, MRC will set MR1 nWR field to 24.
If the bit 5 is clear, MRC will set MR1 nWR field to 6.
Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/27814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update FSP header files to match FSP Reference Code Release v2.0.5
for Geminilake
BUG=b:111683980
CQ-DEPEND=CL:*653835
Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update FSP header files to match FSP Reference Code Release v2.0.3 for
Gemimilake
CQ-DEPEND=CL:*627827
Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26285
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update FSP header files to match FSP Reference Code Release v2.0.2 for
Gemimilake
CQ-DEPEND=CL:*594651,CL:*598345
Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update FSP header files to match GLK FSP Reference Code Release v2.0.0
Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update FSP header files to match FSP v77_12
Following fields have been added in FSP-S UPD:
- SkipPunitInit (Skip P-unit Initialization)
- HgSubSystemId (Sub system Vendor ID VGA)
Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22820
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update FSP header files to match FSP v69_51.
UPD updates in FSP v69_51 are:
- SGX Epoch
- Sub/System Vendor ID
- Remove deprecated UPD
Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/22391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update glk header files as per v52_27 FSP code.
Change-Id: I8e313a2b854e60b1ad8a5c6e080641e323de56a8
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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from FSP release V030_61
Change-Id: I5ecba08de851ee2e362f9ac31e1fa8bf3dfceebb
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19605
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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