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Intel CPX-SP FSP ww36 release has following changes:
* Update FSP header version to change among FSP releases.
* Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11
(OEM strings) generation.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.
In addition, there are some changes to HOB data structures.
Update UPD and HOB header files and adapt soc accordingly.
TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel CPX-SP ww32 release has a number of bug fixes:
a. It fixed the issue related to some PCIe ports being hidden. This
affected DeltaLake config A, made the onboard PCIe NIC device not
working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu.
b. It fixed the regression related to MRC cache.
c. It fixed the issue related to VT-d support, and added X2apic UPD
paramter. A separate PR will be submitted to enable VT-d in coreboot.
d. It fixed the issue related to enabling thermal device with PCI
or ACPI mode. [CB:44075] was submitted to enable it in coreboot.
e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel
not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS
remotely.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.
Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.
The CPX-SP soc code is updated accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The previous Intel CPX-SP FSP release was ww20 release.
The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end
flow of using memory training data to generate FSP_NV_STORAGE HOB and
using memory training data passed from bootloader to skip memory
training, works now. This saves 8 minutes of boot time (with FSP verbose
logging enabled on DeltaLake server).
This release also adds UPD parameters to support IIO bifuration.
The ww24 release has following updates:
a. Removed a number of unnecessary UPD parameters, such as mmiolSize,
mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate.
b. Added UPD parameters to support PCIe ports configuration.
c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit
fields, in addition to PCIe resource memory base/limit fields.
With ww24 release, the issue with PCIe link training persists. On YV3
config A, the onboard NIC card has x4 connection to port 2D. This
NIC device is not recognized by FSP.
Corresponding soc/intel/xeon_sp/cpx change is made:
* There are changes in PLATFORM_DATA structure, so hob_display.c
is updated.
* There are changes in UPD parameters, so romstage.c is updated.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release.
As CPX-SP FSP engineering is on-going (the processor Mass Production
is some time in this year). These header files will be adjusted when
changes are necessary with newer FSP release. This commit corresponds
to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65).
Also update soc/xeon_sp code file and Skylake-SP header file accordingly
to use FsptPort80RouteDisable instead of PcdPort80RouteDisable.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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These header files are just placeholders. Currently FSP does not
look into any real platform-specific UPD fields anyway, so having
padding instead of real thing makes no difference.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Id123f4386124b2ceb7776ab719a9970c9c23a0e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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