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List of changes:
1. FSP-M Header:
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx
Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
FSP-S Header:
- Add UPD MicrocodeRegionBase and MicrocodeRegionSize
- Adjust UPD Offset for Reservedxx
Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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List of changes:
FSP-S Header:
- Adjust UPD Offset for Reservedxx
- Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45
Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
1. FSP-M Header:
- Adjust UPD Offset for Reservedxx
- Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29
2. FSP-S Header:
- Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44
Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. FSP-M Header:
- Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx
Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. FSP-M Header:
- Add new UPD Lp5CccConfig
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport,
GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi,
PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45
Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. FSP-M Header:
- Add new UPD GpioOverride
- Change help text for PlatformDebugConsent UPD
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust Reservedxx UPD Offset
- PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew
by 4 elements
Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h)
hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing
compilation issue.
Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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List of changes:
1. Select FSP_HEADER_PATH
2. Select FSP_FD_PATH
3. Select PLATFORM_USES_FSP2_2
4. Select UDK_202005_BINDING
Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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