Age | Commit message (Collapse) | Author |
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Fix an undefined reference error with GCC 8.1
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-size.o: In function `bdk_dram_get_size_mbytes':
/home/coreboot/slave-root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-test.o: In function `bdk_get_num_cores':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal
/bdk-utils.h:164: undefined reference to `bdk_dpop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram
/dram-init-ddr3.o: In function `init_octeon3_ddr3_interface':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk/libdram/dram-init-
ddr3.c:7550: undefined reference to `bdk_pop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram
/dram-l2c.o: In function `bdk_get_num_cores':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal
/bdk-utils.h:164: undefined reference to `bdk_dpop'
make[1]: *** [src/arch/arm64/Makefile.inc:119: /cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/cbfs/fallback/romstage.debug]
Error 1
Change-Id: Ifcde5476c6f347c0eac7ca44bac88d3fa4017fb7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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* Make it compile.
* Fix whitespace errors.
* Fix printf formats.
* Add missing headers includes
* Guard headers with ifdefs
Compile DRAM init code in romstage.
Compile QLM, PCIe, RNG, PHY, GPIO, MDIO init code in ramstage.
Change-Id: I0a93219a14bfb6ebe41103a825d5032b11e7f2c6
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25089
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This imports common BDK sources that will be used in subsequent
patches.
The BDK is licensed under BSD and will be reduced in size and optimized to
compile under coreboot.
Change-Id: Icb32ee670d9fa9e5c10f9abb298cebf616fa67ad
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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